From patchwork Thu Aug 29 20:48:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823586 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D74F18C003; Thu, 29 Aug 2024 20:49:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964557; cv=none; b=Cbwg8F5GbxEfK8z+E5H5xpjUQ2RDa3u6tMHRM1N4ic/MCe3NSQEeNCKf8g28keSg7+SfzWT+iTfeA4BzPVGrozjRCZXVeSODYiXUM2hJhi6p1fXqGGxaWQ5bH3pNXZ6IcwbBmKkudDLQL1O40xApnUfQmALCsbgDoI0QZANmcbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964557; c=relaxed/simple; bh=dR2G/MD6yM3cOdkFd3LB/ulhZzh5I4UbvIhzhfe8P0U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=c8lTRlqANp6XhLL5wolzg6ujgCF3R8ECpnFtIaK8oNQv9pOI3pdv0k+JoWeREAiEWsMNpEcvv3u5u4qgttqZR3VN8V+bzC+MCeHK1fVTbYo1GGVJjlL11toQFzjUOjkMbDvX52VZfQcidsTQKn5PFfTBnT1uZLrE/IzaPMBKRho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XDCJws7w; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XDCJws7w" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGYXKe020024; Thu, 29 Aug 2024 20:49:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= gqb2UzyXCprwQxN+jRDsHSNUSPIyeNgE724FJcAyVKs=; b=XDCJws7w3USJKy28 w2IAYk6TTwh4wlFe6QON69V2nAQeVF0A3T9wgwW8C6xJQs3LjM0c50bB5+lgKn25 vSOHvlJL4So9Cr2JmHB1p5SncVpGxNIOKNsIztdSedUlOqlggsQ0Yk3/4sLcE25N 9fhe/Po5mjk8Mh6k7KsyNuUNvSoowezj1R3B2OoAesaSMdpRZoxEsuE9WrMaJLSt lCKuVpKnCr7rOe93Qe/YFuxEMuG/uqsre0Dty2pLzwMP5P3uahFPVUlueC+7cBhj FMGPryYkxcSTEFGWP2sgAmX80cT6Gt9NKiMCqG8m+0Mf8A13Bvpu7WBa5YYAkSjc pHmAvQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419putpnc0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:00 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKmxDL020564 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:48:59 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:48:59 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:22 -0700 Subject: [PATCH 01/21] drm: add clone mode check for CRTC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-1-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=799; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=dR2G/MD6yM3cOdkFd3LB/ulhZzh5I4UbvIhzhfe8P0U=; b=TvXkjmvu+zsZtd+1ybktZpZOmh4GmSflM3w4MQVEPLPin2U542DT2Z0Q9N4VzjwrxubgbWS1y S+QSdH78ROiBjqLvR5xC4/Hy7u+/aKANCp5crB2VIP6Y1E6uQ0GrORB X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qjurr45G4WYarkFUrfuKuFxW1gldVwSP X-Proofpoint-ORIG-GUID: qjurr45G4WYarkFUrfuKuFxW1gldVwSP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 mlxlogscore=988 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Add helper to check if the given CRTC state is in clone mode Signed-off-by: Jessica Zhang --- include/drm/drm_crtc.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8b48a1974da3..ecb93e2c4afc 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1323,5 +1323,12 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); +static inline bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state) +{ + if (!crtc_state) + return false; + + return hweight32(crtc_state->encoder_mask) > 1; +} #endif /* __DRM_CRTC_H__ */ From patchwork Thu Aug 29 20:48:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824071 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8126E18C001; Thu, 29 Aug 2024 20:49:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964556; cv=none; b=RenGUjktH8fcTzUxbK5mL/XUq6W7r6rUsj7qSXaSu/sh6GRmIjCe0w4jCtiO2KjT9xlYcdU9nUVw/RDXhJ7X/odCskoNBGhAtBr9/awjYKaNGqUhvfEQDT/hxzFzXeOn4ooYPv+MnklQ8nYqr6DPWlYzX5Cb9d2MNi2/pPv5ZxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964556; c=relaxed/simple; bh=e096vd+UGNu8nhPc7VODA2MS7X3rPYMs4TqTAd6/p+w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=uUp1SPOH+B5cT5qwJLIHEBZeJw4cM95cDw2hOD423QpACjARmn3ghsD4B+rLqLIRd20huO9BZojYlgWOxgt6gUF77rQHko3wdc8Njo/9JRovwbE9Z5yg+ImConOUcT5awc68IBzrxPuGtbzs4EJRSl5BKe3YPb/tM8ecLiXAjpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cRbDHi1o; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cRbDHi1o" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TIHdZt029683; Thu, 29 Aug 2024 20:49:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qODsJSNBUwNBwv/NnQmyvRkfF2gKRPblTOuINE501Gs=; b=cRbDHi1otFM6YmpH lku8z6H+4bqd+/ZAwHjo1iYQ4iQg8dfRy02xnxai3umvJc08AXxSNcbC2OIgz3gZ 0trm0w+MCB8AV4OPshDvj7jIBsCAoNYIGTmTiEBI/SeQCiRm9BhQQvQ8Fa9bOGNb 6Bn0gsEmKsEg/XrYQ7eZP4qg4q/sOBFtIcsLZHeED0vkRNmpqJOSuWE99M6W9DV4 cPYVKSmW7nsT1qArrmOvv/LKAwomMNKdYYSQ8COqfWr8R/mj1eAGhUyFbLQsx1+y YhBNNdUpH5858RVkSCk4IorYLOsimL6kovza6kdDOV5pO3D7g2ypv5N1AAByqmUu TLc8UA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41ax4mgard-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:00 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn0mK003214 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:00 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:48:59 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:23 -0700 Subject: [PATCH 02/21] drm: print clone mode status in atomic state Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-2-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=849; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=e096vd+UGNu8nhPc7VODA2MS7X3rPYMs4TqTAd6/p+w=; b=NT2w9k5F2A+JMojngiiGVRCD8/ifOy/8GoDaMcu1bm945Z5XKcDhDtNmfuYB3eyXFBgipNrIP SJQU79RtCioCufAjF3iN6v3xKSRR+agrvi5+5oSK+VQVbQzm2VPRPiS X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: q1DI6H_2SWl0D5MnYhAhmiC4Wex6LSSM X-Proofpoint-ORIG-GUID: q1DI6H_2SWl0D5MnYhAhmiC4Wex6LSSM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Add clone mode status to the DRM atomic print state Signed-off-by: Jessica Zhang --- drivers/gpu/drm/drm_atomic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 07b4b394e3bf..145d6a758d4d 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -455,6 +455,7 @@ static void drm_atomic_crtc_print_state(struct drm_printer *p, drm_printf(p, "\tconnector_mask=%x\n", state->connector_mask); drm_printf(p, "\tencoder_mask=%x\n", state->encoder_mask); drm_printf(p, "\tmode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(&state->mode)); + drm_printf(p, "\tin_clone_mode=%d\n", drm_crtc_in_clone_mode(crtc->state)); if (crtc->funcs->atomic_print_state) crtc->funcs->atomic_print_state(p, state); From patchwork Thu Aug 29 20:48:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824065 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1569E1BAEED; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; cv=none; b=jakgzubRdEuPez+0XzUohdlA9dK0LmWT1nv1baW6M4RbKtKcwjb9oxyqHOUPMWmQdGQOi3C7fjNkKY+N8DFFnoK1q749tMuls88TmdousjURlJTLYEymxtiFWjp9OX9eZqLVEQmk1OiwwXehx5KtEZ05zkHsDmizdb7aVWVe3Ds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; c=relaxed/simple; bh=07G9gzQAACsgw4H/K4Ow69xRYTcM1prqrUAwLtCURgU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ZHvHjyCFOZz3RsjPvhPOW/adtdxzLH27Ssbyadf0R9d6sH1ong20x1ZqOVCv1HjIosR5NAFDqzcA6BOkA3FimLW1o5YBKWXMO4iq+TpVTew4krpcpMoWcztO7Bfqfpngau+n8i/SiY3mMFStBZuIHgrVI86dxr2/KkQRaFF9pWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ij8WmQZT; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ij8WmQZT" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47THagsi020435; Thu, 29 Aug 2024 20:49:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Hb20sF5pC2/rTIwg1n6j/suu4nVbt039Nev1W+s3TRY=; b=ij8WmQZTH2uxNzAv TVbT/02q3hqeeJOdytKxSf0ANq/BuWptE4jhLPvdcCfTzSCwHX/M5Db67hl/pZic Pzm1XGMHQ6NQodWqz3Z4kSJ7H8eKT/xqHdWtlup+e6w9qtwNKwcZI0Wom7xbfaLn vRTjC4SAc6I3/7fLFfIoZ3NMyroUOfv9lfbqt3gCsjfaXI+mwrjGiL5j+s8jCrQY 241dDuw/nXHCL381NIZ4W0Vg5wenFmfBFLhVWqpjowi+mj1iOfSxpr5a/uRs7UP5 89s04OLwsnn9WhmIxXMYSxElKBewC8NqXWqzhXvCV3V0iE6nJNHweeEPivrdjr6F xDuzog== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419q2xxk9m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn0w8024999 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:00 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:48:59 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:24 -0700 Subject: [PATCH 03/21] drm/msm/dpu: get rid of struct dpu_rm_requirements Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-3-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=8793; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=BtjfoFa7Sc1KYJR0US8P5QJOsTWJhBDWuRPihcWh590=; b=jP625lSxLulc5JtlqBHWm32YJWCvVAx6B8yEavBanUkFvvKePXQo2D+Xlr3bs4IASDIkJ/rT+ Xn5x0BMP+BxAS0VXKTLsr3r9WAPmUHDjmoQi0P9tRLsF7g91FJvkOsq X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MBYrj3Z0xhfu4E7lmAo-AJiZLNpDRlXC X-Proofpoint-GUID: MBYrj3Z0xhfu4E7lmAo-AJiZLNpDRlXC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290145 From: Dmitry Baryshkov The struct dpu_rm_requirements was used to wrap display topology and hw resources, which meant INTF indices. As of commit ef58e0ad3436 ("drm/msm/dpu: get INTF blocks directly rather than through RM") the hw resources struct was removed, leaving struct dpu_rm_requirements containing a single field (topology). Remove the useless wrapper. Signed-off-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 71 ++++++++++------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +- 3 files changed, 25 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 3b171bf227d1..6293e716a1c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -691,7 +691,7 @@ static int dpu_encoder_virt_atomic_check( if (!crtc_state->active_changed || crtc_state->enable) ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); + drm_enc, crtc_state, &topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 44938ba7a2b7..8193c3d579df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -4,6 +4,7 @@ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include "msm_drv.h" #define pr_fmt(fmt) "[drm:%s] " fmt, __func__ #include "dpu_kms.h" #include "dpu_hw_lm.h" @@ -26,14 +27,6 @@ static inline bool reserved_by_other(uint32_t *res_map, int idx, return res_map[idx] && res_map[idx] != enc_id; } -/** - * struct dpu_rm_requirements - Reservation requirements parameter bundle - * @topology: selected topology for the display - */ -struct dpu_rm_requirements { - struct msm_display_topology topology; -}; - int dpu_rm_init(struct drm_device *dev, struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, @@ -231,14 +224,13 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) * mixer in rm->pingpong_blks[]. * @dspp_idx: output parameter, index of dspp block attached to the layer * mixer in rm->dspp_blks[]. - * @reqs: input parameter, rm requirements for HW blocks needed in the - * datapath. + * @topology: selected topology for the display * Return: true if lm matches all requirements, false otherwise */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, - struct dpu_rm_requirements *reqs) + struct msm_display_topology *topology) { const struct dpu_lm_cfg *lm_cfg; int idx; @@ -263,7 +255,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, } *pp_idx = idx; - if (!reqs->topology.num_dspp) + if (!topology->num_dspp) return true; idx = lm_cfg->dspp - DSPP_0; @@ -285,7 +277,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, - struct dpu_rm_requirements *reqs) + struct msm_display_topology *topology) { int lm_idx[MAX_BLOCKS]; @@ -293,14 +285,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, int dspp_idx[MAX_BLOCKS] = {0}; int i, lm_count = 0; - if (!reqs->topology.num_lm) { - DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm); + if (!topology->num_lm) { + DPU_ERROR("invalid number of lm: %d\n", topology->num_lm); return -EINVAL; } /* Find a primary mixer */ for (i = 0; i < ARRAY_SIZE(rm->mixer_blks) && - lm_count < reqs->topology.num_lm; i++) { + lm_count < topology->num_lm; i++) { if (!rm->mixer_blks[i]) continue; @@ -309,14 +301,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, i, &pp_idx[lm_count], - &dspp_idx[lm_count], reqs)) { + &dspp_idx[lm_count], topology)) { continue; } ++lm_count; /* Valid primary mixer found, find matching peers */ - if (lm_count < reqs->topology.num_lm) { + if (lm_count < topology->num_lm) { int j = _dpu_rm_get_lm_peer(rm, i); /* ignore the peer if there is an error or if the peer was already processed */ @@ -329,7 +321,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, j, &pp_idx[lm_count], &dspp_idx[lm_count], - reqs)) { + topology)) { continue; } @@ -338,7 +330,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, } } - if (lm_count != reqs->topology.num_lm) { + if (lm_count != topology->num_lm) { DPU_DEBUG("unable to find appropriate mixers\n"); return -ENAVAIL; } @@ -347,7 +339,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; global_state->dspp_to_enc_id[dspp_idx[i]] = - reqs->topology.num_dspp ? enc_id : 0; + topology->num_dspp ? enc_id : 0; trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, pp_idx[i] + PINGPONG_0); @@ -584,28 +576,28 @@ static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, struct drm_encoder *enc, - struct dpu_rm_requirements *reqs) + struct msm_display_topology *topology) { int ret; - ret = _dpu_rm_reserve_lms(rm, global_state, enc->base.id, reqs); + ret = _dpu_rm_reserve_lms(rm, global_state, enc->base.id, topology); if (ret) { DPU_ERROR("unable to find appropriate mixers\n"); return ret; } ret = _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, - &reqs->topology); + topology); if (ret) { DPU_ERROR("unable to find appropriate CTL\n"); return ret; } - ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + ret = _dpu_rm_reserve_dsc(rm, global_state, enc, topology); if (ret) return ret; - if (reqs->topology.needs_cdm) { + if (topology->needs_cdm) { ret = _dpu_rm_reserve_cdm(rm, global_state, enc); if (ret) { DPU_ERROR("unable to find CDM blk\n"); @@ -616,20 +608,6 @@ static int _dpu_rm_make_reservation( return ret; } -static int _dpu_rm_populate_requirements( - struct drm_encoder *enc, - struct dpu_rm_requirements *reqs, - struct msm_display_topology req_topology) -{ - reqs->topology = req_topology; - - DRM_DEBUG_KMS("num_lm: %d num_dsc: %d num_intf: %d cdm: %d\n", - reqs->topology.num_lm, reqs->topology.num_dsc, - reqs->topology.num_intf, reqs->topology.needs_cdm); - - return 0; -} - static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, uint32_t enc_id) { @@ -662,9 +640,8 @@ int dpu_rm_reserve( struct dpu_global_state *global_state, struct drm_encoder *enc, struct drm_crtc_state *crtc_state, - struct msm_display_topology topology) + struct msm_display_topology *topology) { - struct dpu_rm_requirements reqs; int ret; /* Check if this is just a page-flip */ @@ -679,13 +656,11 @@ int dpu_rm_reserve( DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", enc->base.id, crtc_state->crtc->base.id); - ret = _dpu_rm_populate_requirements(enc, &reqs, topology); - if (ret) { - DPU_ERROR("failed to populate hw requirements\n"); - return ret; - } + DRM_DEBUG_KMS("num_lm: %d num_dsc: %d num_intf: %d\n", + topology->num_lm, topology->num_dsc, + topology->num_intf); - ret = _dpu_rm_make_reservation(rm, global_state, enc, &reqs); + ret = _dpu_rm_make_reservation(rm, global_state, enc, topology); if (ret) DPU_ERROR("failed to reserve hw resources: %d\n", ret); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index e63db8ace6b9..62cc2edd2ee0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -70,7 +70,7 @@ int dpu_rm_reserve(struct dpu_rm *rm, struct dpu_global_state *global_state, struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state, - struct msm_display_topology topology); + struct msm_display_topology *topology); /** * dpu_rm_reserve - Given the encoder for the display chain, release any From patchwork Thu Aug 29 20:48:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824061 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A082B1BC072; Thu, 29 Aug 2024 20:49:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964564; cv=none; b=ArOT5iEecCVsgZvUTot3vj6PvAfjvfQ+Yus94v/8ILkmVGXaKeDQrp8hH+cGVO9sH9BgK9JQFKWrxiJ4h/fJv+YcD/E/A0UcW+GG78V5AT1vmyWrNUijIkosKFPOsNOGyk5v2z4fK15JIVQy1fdGLRZO7wa3sN1sBFHsTHYYqkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964564; c=relaxed/simple; bh=7V4kPfOp6UMn+ynrpIRZ1jkIDGGaQWWHCrzuxgpBnL8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JXnWN0s2Ko10Nv0eEqKJsEQtt5R/IWGHbvoE1TJzxY9zMZ3HH4p38t+HZQWmeEmY7kyor44KI8e8lRUN9tq6NZmR/Qnz5bh5BEuKY4wM76VAkUyX5/gTtUwbs07DIfkx8P+y452xRHiGwuSONExXLVWE1eSjpBey79MCwx50Mlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ckbqZdRc; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ckbqZdRc" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGVh6U024190; Thu, 29 Aug 2024 20:49:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pz3XvA3NR3VJ2DdILpReUGeE4OqNSzymv1hDLbeufng=; b=ckbqZdRciO9TPPjr DtJ4R9RLet6sGfHQJwyyzkIfy+WRDdTxhNGcaLB64C2qKBiHYwdo3M/YOZRSUa1Z 9wRpbiY8hlj0X2bJSYYo4Ct3sao+6PROYASJufvn3IkZzQbEaw84GcCqszv00Joq kkvFpv5ij/VlLPm0sn1qOlEpdHREZQ8a/S3u79hci3uKosjcbJrXMicPaFc8uWPD cYOc8USDPrX0+nwOukoO0Pirvzn1jBHXv38qPCbyJV25/1Yp914vihDA32TA/uNy XHJjEoHNQdpki0gmD1st2t3RBIxTKfhU+HdnLSjN8ypopQ135nm+1ZcE3GlFTni3 PvWJhQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41a612mhr9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn0M3025005 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:00 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:00 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:25 -0700 Subject: [PATCH 04/21] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-4-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=24013; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=tZcim61kNk804Zbix3YxYvhLVe04nn7WrjSzhfB8zaw=; b=7bAu5gxtcEpbjEI9pU+NB8ZCB201q2xEA/wL0Bli3PXL0edF7TCNk84oSY9vj6Yug/N4E6Y8K njetjYIGHmMD0DiaMYFRCVs146tOZ0ReYA2H9iV1aBD1HbdgeDk7u2j X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: niSYJh4zF1EipcZL-NIQMy61F6-TQOt3 X-Proofpoint-ORIG-GUID: niSYJh4zF1EipcZL-NIQMy61F6-TQOt3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 From: Dmitry Baryshkov Up to now the driver has been using encoder to allocate hardware resources. Switch it to use CRTC id in preparation for the next step. Signed-off-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 182 ++++++++++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 +- 4 files changed, 108 insertions(+), 116 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 6293e716a1c3..4a9edcfbcaae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -687,11 +687,11 @@ static int dpu_encoder_virt_atomic_check( * Dont allocate when active is false. */ if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + dpu_rm_release(global_state, crtc_state->crtc); if (!crtc_state->active_changed || crtc_state->enable) ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, &topology); + crtc_state->crtc, &topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); @@ -1125,14 +1125,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, /* Query resource that have been reserved in atomic check step. */ num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, + drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) @@ -1140,7 +1140,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, : NULL; num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSC, + drm_enc->crtc, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); for (i = 0; i < num_dsc; i++) { dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); @@ -1154,7 +1154,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_cdm = NULL; dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CDM, + drm_enc->crtc, DPU_HW_BLK_CDM, &hw_cdm, 1); dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } @@ -2021,7 +2021,7 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, - phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); for (i = 0; i < num_lm; i++) { hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 935ff6fd172c..4fdc5f933261 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -122,12 +122,12 @@ struct dpu_global_state { struct dpu_rm *rm; - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; - uint32_t mixer_to_enc_id[LM_MAX - LM_0]; - uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; - uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; - uint32_t cdm_to_enc_id; + uint32_t pingpong_to_crtc_id[PINGPONG_MAX - PINGPONG_0]; + uint32_t mixer_to_crtc_id[LM_MAX - LM_0]; + uint32_t ctl_to_crtc_id[CTL_MAX - CTL_0]; + uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_crtc_id[DSC_MAX - DSC_0]; + uint32_t cdm_to_crtc_id; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 8193c3d579df..bc99b04eae3a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -22,9 +22,9 @@ static inline bool reserved_by_other(uint32_t *res_map, int idx, - uint32_t enc_id) + uint32_t crtc_id) { - return res_map[idx] && res_map[idx] != enc_id; + return res_map[idx] && res_map[idx] != crtc_id; } int dpu_rm_init(struct drm_device *dev, @@ -216,7 +216,7 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) * pingpong * @rm: dpu resource manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc_id: encoder id requesting for allocation * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function checks * if lm, and all other hardwired blocks connected to the lm (pp) is * available and appropriate @@ -229,14 +229,14 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t crtc_id, int lm_idx, int *pp_idx, int *dspp_idx, struct msm_display_topology *topology) { const struct dpu_lm_cfg *lm_cfg; int idx; /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { + if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) { DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); return false; } @@ -248,7 +248,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, return false; } - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, lm_cfg->pingpong); return false; @@ -264,7 +264,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, return false; } - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, lm_cfg->dspp); return false; @@ -276,7 +276,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, struct msm_display_topology *topology) { @@ -300,7 +300,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_idx[lm_count] = i; if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], + crtc_id, i, &pp_idx[lm_count], &dspp_idx[lm_count], topology)) { continue; } @@ -319,7 +319,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, + global_state, crtc_id, j, &pp_idx[lm_count], &dspp_idx[lm_count], topology)) { continue; @@ -336,12 +336,12 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, } for (i = 0; i < lm_count; i++) { - global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] = - topology->num_dspp ? enc_id : 0; + global_state->mixer_to_crtc_id[lm_idx[i]] = crtc_id; + global_state->pingpong_to_crtc_id[pp_idx[i]] = crtc_id; + global_state->dspp_to_crtc_id[dspp_idx[i]] = + topology->num_dspp ? crtc_id : 0; - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, crtc_id, pp_idx[i] + PINGPONG_0); } @@ -351,7 +351,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, static int _dpu_rm_reserve_ctls( struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int ctl_idx[MAX_BLOCKS]; @@ -370,7 +370,7 @@ static int _dpu_rm_reserve_ctls( if (!rm->ctl_blks[j]) continue; - if (reserved_by_other(global_state->ctl_to_enc_id, j, enc_id)) + if (reserved_by_other(global_state->ctl_to_crtc_id, j, crtc_id)) continue; ctl = to_dpu_hw_ctl(rm->ctl_blks[j]); @@ -394,8 +394,8 @@ static int _dpu_rm_reserve_ctls( return -ENAVAIL; for (i = 0; i < ARRAY_SIZE(ctl_idx) && i < num_ctls; i++) { - global_state->ctl_to_enc_id[ctl_idx[i]] = enc_id; - trace_dpu_rm_reserve_ctls(i + CTL_0, enc_id); + global_state->ctl_to_crtc_id[ctl_idx[i]] = crtc_id; + trace_dpu_rm_reserve_ctls(i + CTL_0, crtc_id); } return 0; @@ -403,12 +403,12 @@ static int _dpu_rm_reserve_ctls( static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_state, int start, - uint32_t enc_id) + uint32_t crtc_id) { int i; for (i = start; i < (PINGPONG_MAX - PINGPONG_0); i++) { - if (global_state->pingpong_to_enc_id[i] == enc_id) + if (global_state->pingpong_to_crtc_id[i] == crtc_id) return i; } @@ -429,7 +429,7 @@ static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int pp_idx) static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc = 0; @@ -442,10 +442,10 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (!rm->dsc_blks[dsc_idx]) continue; - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id)) continue; - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; @@ -453,7 +453,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (ret) return -ENAVAIL; - global_state->dsc_to_enc_id[dsc_idx] = enc_id; + global_state->dsc_to_crtc_id[dsc_idx] = crtc_id; num_dsc++; pp_idx++; } @@ -469,7 +469,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc = 0; @@ -484,11 +484,11 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; /* consective dsc index to be paired */ - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || - reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id) || + reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx + 1, crtc_id)) continue; - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; @@ -498,7 +498,7 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, crtc_id); if (pp_idx < 0) return -ENAVAIL; @@ -508,8 +508,8 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } - global_state->dsc_to_enc_id[dsc_idx] = enc_id; - global_state->dsc_to_enc_id[dsc_idx + 1] = enc_id; + global_state->dsc_to_crtc_id[dsc_idx] = crtc_id; + global_state->dsc_to_crtc_id[dsc_idx + 1] = crtc_id; num_dsc += 2; pp_idx++; /* start for next pair */ } @@ -525,11 +525,9 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, const struct msm_display_topology *top) { - uint32_t enc_id = enc->base.id; - if (!top->num_dsc || !top->num_intf) return 0; @@ -545,16 +543,16 @@ static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, /* num_dsc should be either 1, 2 or 4 */ if (top->num_dsc > top->num_intf) /* merge mode */ - return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc_pair(rm, global_state, crtc_id, top); else - return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc(rm, global_state, crtc_id, top); return 0; } static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc) + uint32_t crtc_id) { /* try allocating only one CDM block */ if (!rm->cdm_blk) { @@ -562,12 +560,12 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, return -EIO; } - if (global_state->cdm_to_enc_id) { + if (global_state->cdm_to_crtc_id) { DPU_ERROR("CDM_0 is already allocated\n"); return -EIO; } - global_state->cdm_to_enc_id = enc->base.id; + global_state->cdm_to_crtc_id = crtc_id; return 0; } @@ -575,30 +573,31 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, struct msm_display_topology *topology) { int ret; - ret = _dpu_rm_reserve_lms(rm, global_state, enc->base.id, topology); + ret = _dpu_rm_reserve_lms(rm, global_state, crtc_id, topology); if (ret) { DPU_ERROR("unable to find appropriate mixers\n"); return ret; } - ret = _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, + + ret = _dpu_rm_reserve_ctls(rm, global_state, crtc_id, topology); if (ret) { DPU_ERROR("unable to find appropriate CTL\n"); return ret; } - ret = _dpu_rm_reserve_dsc(rm, global_state, enc, topology); + ret = _dpu_rm_reserve_dsc(rm, global_state, crtc_id, topology); if (ret) return ret; if (topology->needs_cdm) { - ret = _dpu_rm_reserve_cdm(rm, global_state, enc); + ret = _dpu_rm_reserve_cdm(rm, global_state, crtc_id); if (ret) { DPU_ERROR("unable to find CDM blk\n"); return ret; @@ -609,103 +608,98 @@ static int _dpu_rm_make_reservation( } static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, - uint32_t enc_id) + uint32_t crtc_id) { int i; for (i = 0; i < cnt; i++) { - if (res_mapping[i] == enc_id) + if (res_mapping[i] == crtc_id) res_mapping[i] = 0; } } void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc) + struct drm_crtc *crtc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, - ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, - ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, - ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dspp_to_enc_id, - ARRAY_SIZE(global_state->dspp_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); + uint32_t crtc_id = crtc->base.id; + + _dpu_rm_clear_mapping(global_state->pingpong_to_crtc_id, + ARRAY_SIZE(global_state->pingpong_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->mixer_to_crtc_id, + ARRAY_SIZE(global_state->mixer_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->ctl_to_crtc_id, + ARRAY_SIZE(global_state->ctl_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dsc_to_crtc_id, + ARRAY_SIZE(global_state->dsc_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dspp_to_crtc_id, + ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(&global_state->cdm_to_crtc_id, 1, crtc_id); } int dpu_rm_reserve( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology *topology) { int ret; - /* Check if this is just a page-flip */ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return 0; - if (IS_ERR(global_state)) { DPU_ERROR("failed to global state\n"); return PTR_ERR(global_state); } - DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", - enc->base.id, crtc_state->crtc->base.id); + DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc->base.id); DRM_DEBUG_KMS("num_lm: %d num_dsc: %d num_intf: %d\n", topology->num_lm, topology->num_dsc, topology->num_intf); - ret = _dpu_rm_make_reservation(rm, global_state, enc, topology); + ret = _dpu_rm_make_reservation(rm, global_state, crtc->base.id, topology); if (ret) DPU_ERROR("failed to reserve hw resources: %d\n", ret); - - return ret; } int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) { + uint32_t crtc_id = crtc->base.id; struct dpu_hw_blk **hw_blks; - uint32_t *hw_to_enc_id; + uint32_t *hw_to_crtc_id; int i, num_blks, max_blks; switch (type) { case DPU_HW_BLK_PINGPONG: hw_blks = rm->pingpong_blks; - hw_to_enc_id = global_state->pingpong_to_enc_id; + hw_to_crtc_id = global_state->pingpong_to_crtc_id; max_blks = ARRAY_SIZE(rm->pingpong_blks); break; case DPU_HW_BLK_LM: hw_blks = rm->mixer_blks; - hw_to_enc_id = global_state->mixer_to_enc_id; + hw_to_crtc_id = global_state->mixer_to_crtc_id; max_blks = ARRAY_SIZE(rm->mixer_blks); break; case DPU_HW_BLK_CTL: hw_blks = rm->ctl_blks; - hw_to_enc_id = global_state->ctl_to_enc_id; + hw_to_crtc_id = global_state->ctl_to_crtc_id; max_blks = ARRAY_SIZE(rm->ctl_blks); break; case DPU_HW_BLK_DSPP: hw_blks = rm->dspp_blks; - hw_to_enc_id = global_state->dspp_to_enc_id; + hw_to_crtc_id = global_state->dspp_to_crtc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break; case DPU_HW_BLK_DSC: hw_blks = rm->dsc_blks; - hw_to_enc_id = global_state->dsc_to_enc_id; + hw_to_crtc_id = global_state->dsc_to_crtc_id; max_blks = ARRAY_SIZE(rm->dsc_blks); break; case DPU_HW_BLK_CDM: hw_blks = &rm->cdm_blk; - hw_to_enc_id = &global_state->cdm_to_enc_id; + hw_to_crtc_id = &global_state->cdm_to_crtc_id; max_blks = 1; break; default: @@ -715,17 +709,17 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, num_blks = 0; for (i = 0; i < max_blks; i++) { - if (hw_to_enc_id[i] != enc_id) + if (hw_to_crtc_id[i] != crtc_id) continue; if (num_blks == blks_size) { - DPU_ERROR("More than %d resources assigned to enc %d\n", - blks_size, enc_id); + DPU_ERROR("More than %d resources assigned to crtc %d\n", + blks_size, crtc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("Allocated resource %d unavailable to assign to enc %d\n", - type, enc_id); + DPU_ERROR("Allocated resource %d unavailable to assign to crtc %d\n", + type, crtc_id); break; } blks[num_blks++] = hw_blks[i]; @@ -755,37 +749,37 @@ void dpu_rm_print_state(struct drm_printer *p, drm_puts(p, "resource mapping:\n"); drm_puts(p, "\tpingpong="); - for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->pingpong_blks[i], - global_state->pingpong_to_enc_id[i]); + global_state->pingpong_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tmixer="); - for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->mixer_blks[i], - global_state->mixer_to_enc_id[i]); + global_state->mixer_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tctl="); - for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->ctl_blks[i], - global_state->ctl_to_enc_id[i]); + global_state->ctl_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tdspp="); - for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dspp_blks[i], - global_state->dspp_to_enc_id[i]); + global_state->dspp_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tdsc="); - for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dsc_blks[i], - global_state->dsc_to_enc_id[i]); + global_state->dsc_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tcdm="); dpu_rm_print_state_helper(p, rm->cdm_blk, - global_state->cdm_to_enc_id); + global_state->cdm_to_crtc_id); drm_puts(p, "\n"); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 62cc2edd2ee0..36a0b6ed628d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -61,32 +61,30 @@ int dpu_rm_init(struct drm_device *dev, * HW blocks can then be accessed through dpu_rm_get_* functions. * HW Reservations should be released via dpu_rm_release_hw. * @rm: DPU Resource Manager handle - * @drm_enc: DRM Encoder handle - * @crtc_state: Proposed Atomic DRM CRTC State handle + * @crtc: DRM CRTC handle * @topology: Pointer to topology info for the display * @Return: 0 on Success otherwise -ERROR */ int dpu_rm_reserve(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology *topology); /** * dpu_rm_reserve - Given the encoder for the display chain, release any * HW blocks previously reserved for that use case. * @rm: DPU Resource Manager handle - * @enc: DRM Encoder handle + * @crtc: DRM CRTC handle * @Return: 0 on Success otherwise -ERROR */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc); + struct drm_crtc *crtc); /** * Get hw resources of the given type that are assigned to this encoder. */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); /** From patchwork Thu Aug 29 20:48:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823577 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2D9618C003; Thu, 29 Aug 2024 20:49:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964563; cv=none; b=B3T/AjH6XvnTBS4oLiXMRPPEHw7AXr9Rm3HsdNCgtmB1PHNmz3NEnttYKOTwHQs6IQ2iPW+wqyJCDqH2NPjFjaG5bfJQ4uXlut1buCf5EAcxk7oq3l0Yx2e7BJOrEfvXIHK6K5vGS63bMlQQVTHXvpyc/8YvaTpHF4MCq/lZp18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964563; c=relaxed/simple; bh=lOayLCVCOpm0+AWyM8ORjLae8iqSoAYwRZXbabucgbY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tkQSsTvng5nPzd9mGgafhMvEfS/hG/JQ3jPFgBQ2YbAiIs68z4QwLjOuMzQb48fUAtRiLcz8zkbkCG0jzI3pc+RfLPhcvD4eDMW5wwJET0XjwMgE/9ODOVa0dHW/37QZjmFobUQ08gKBz5dc/SfalfMEpdfKc/5I/NXC2/GZfL4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ScxyCt7q; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ScxyCt7q" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGW0jL011195; Thu, 29 Aug 2024 20:49:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= BEjV3FK2n/+UUN/XNulqeJViTjFnBa5vRWj3KyHIQzk=; b=ScxyCt7qT89/7Ru2 NxgYQIacV46NCqTI55lpLqjvOLEg91iDbE1B759LwIJwEVCHGeIsIxo6kr70PeBV MBQ+eBqhqmicBAbZ7LCK9xjcsRXqTFow6/c7t3hsQAyq7tg8NuYmMQJm7MSkkDnQ uvBQOTGkoOC1CVoZfNrywLDQ2kg74j4mVVGcywiq1XMSlOqKz0Dr6JVOdd9uFMzy ka0f1afVJfXW1VlSJ+IDn8YpttiDGdKpb/pEZcqBDnSsitxK463marNk+FDuL/v0 YztnlhbwwPBIa342MWO/1fiXppWjvZoJGd5IUixiFhbPOed/wreMlGIUXpNheSik GbCbdg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419pv0pq95-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn09x016013 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:00 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:00 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:26 -0700 Subject: [PATCH 05/21] drm/msm/dpu: move resource allocation to CRTC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-5-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=14841; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=PuZF6J6wM0h7D/RzAFBZ73AicHGq2rFilv128WxCEP0=; b=kzXz8hpqpZw1xI0/a3rX3S/G391rEPBZjfI0HZ4P7JrJZI5M+y2gsqn+FR47P73Eh7l1wl4RT dFl4iWYoifwDTaunEZWFLkgiORGssp1f81o+zELEtOKLlENHfrgwdFI X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mj6v13o_O1dsjeMAhprfniFD2aU6aYG0 X-Proofpoint-ORIG-GUID: mj6v13o_O1dsjeMAhprfniFD2aU6aYG0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 From: Dmitry Baryshkov All resource allocation is centered around the LMs. Then other blocks (except DSCs) are allocated basing on the LMs that was selected, and LM powers up the CRTC rather than the encoder. Moreover if at some point the driver supports encoder cloning, allocating resources from the encoder will be incorrect, as all clones will have different encoder IDs, while LMs are to be shared by these encoders. Signed-off-by: Dmitry Baryshkov [quic_abhinavk@quicinc.com: Refactored resource allocation for CDM] Signed-off-by: Abhinav Kumar [quic_jesszhan@quicinc.com: Changed to grabbing exising global state and dropped clearing num_mixers in crtc_disable] Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 89 +++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 201 +++++++++++----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 19 +++ 3 files changed, 183 insertions(+), 126 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 4c1be2f0555f..3296b0650056 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1091,9 +1091,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, dpu_core_perf_crtc_update(crtc, 0); - memset(cstate->mixers, 0, sizeof(cstate->mixers)); - cstate->num_mixers = 0; - /* disable clk & bw control until clk & bw properties are set */ cstate->bw_control = false; cstate->bw_split_vote = false; @@ -1163,6 +1160,78 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) return false; } +#define MAX_HDISPLAY_SPLIT 1080 + +static struct msm_display_topology dpu_crtc_get_topology( + struct drm_crtc *crtc, + struct dpu_kms *dpu_kms, + struct drm_crtc_state *crtc_state) +{ + struct drm_display_mode *mode = &crtc_state->adjusted_mode; + struct msm_display_topology topology = {0}; + struct drm_encoder *drm_enc; + + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) + dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, + &crtc_state->adjusted_mode); + + /* + * Datapath topology selection + * + * Dual display + * 2 LM, 2 INTF ( Split display using 2 interfaces) + * + * Single display + * 1 LM, 1 INTF + * 2 LM, 1 INTF (stream merge to support high resolution interfaces) + * + * Add dspps to the reservation requirements if ctm is requested + */ + + if (topology.num_intf == 2) + topology.num_lm = 2; + else if (topology.num_dsc == 2) + topology.num_lm = 2; + else if (dpu_kms->catalog->caps->has_3d_merge) + topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + else + topology.num_lm = 1; + + if (crtc_state->ctm) + topology.num_dspp = topology.num_lm; + + return topology; +} + +static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) +{ + struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); + struct dpu_global_state *global_state; + struct msm_display_topology topology; + int ret; + + /* + * Release and Allocate resources on every modeset + * Dont allocate when enable is false. + */ + global_state = dpu_kms_get_existing_global_state(dpu_kms); + if (IS_ERR(global_state)) + return PTR_ERR(global_state); + + dpu_rm_release(global_state, crtc); + + if (!crtc_state->enable) + return 0; + + topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state); + ret = dpu_rm_reserve(&dpu_kms->rm, global_state, + crtc, &topology); + if (ret) + return ret; + + return 0; +} + static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -1174,10 +1243,24 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, const struct drm_plane_state *pstate; struct drm_plane *plane; + struct drm_encoder *drm_enc; + int rc = 0; bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); + /* there might be cases where encoder needs a modeset too */ + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) { + if (dpu_encoder_needs_modeset(drm_enc, crtc_state->state)) + crtc_state->mode_changed = true; + } + + if (drm_atomic_crtc_needs_modeset(crtc_state)) { + rc = dpu_crtc_assign_resources(crtc, crtc_state); + if (rc < 0) + return rc; + } + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 4a9edcfbcaae..ada9119326ca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -58,8 +58,6 @@ #define IDLE_SHORT_TIMEOUT 1 -#define MAX_HDISPLAY_SPLIT 1080 - /* timeout in frames waiting for frame done */ #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 @@ -544,159 +542,117 @@ void dpu_encoder_helper_split_config( } } -bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) +void dpu_encoder_update_topology(struct drm_encoder *drm_enc, + struct msm_display_topology *topology, + struct drm_atomic_state *state, + const struct drm_display_mode *adj_mode) { struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); - int i, intf_count = 0, num_dsc = 0; + struct drm_connector *connector; + struct drm_connector_state *conn_state; + struct msm_display_info *disp_info; + struct drm_framebuffer *fb; + struct msm_drm_private *priv; + int i; for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) if (dpu_enc->phys_encs[i]) - intf_count++; + topology->num_intf++; - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ + /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ if (dpu_enc->dsc) - num_dsc = 2; + topology->num_dsc += 2; - return (num_dsc > 0) && (num_dsc > intf_count); -} + connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); + if (!connector) + return; + conn_state = drm_atomic_get_new_connector_state(state, connector); + if (!conn_state) + return; -struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) -{ - struct msm_drm_private *priv = drm_enc->dev->dev_private; - struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); - int index = dpu_enc->disp_info.h_tile_instance[0]; + disp_info = &dpu_enc->disp_info; - if (dpu_enc->disp_info.intf_type == INTF_DSI) - return msm_dsi_get_dsc_config(priv->dsi[index]); + priv = drm_enc->dev->dev_private; - return NULL; + /* + * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. + * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() + * earlier. + */ + if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { + fb = conn_state->writeback_job->fb; + + if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) + topology->needs_cdm = true; + } else if (disp_info->intf_type == INTF_DP) { + if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) + topology->needs_cdm = true; + } } -static struct msm_display_topology dpu_encoder_get_topology( - struct dpu_encoder_virt *dpu_enc, - struct dpu_kms *dpu_kms, - struct drm_display_mode *mode, - struct drm_crtc_state *crtc_state, - struct drm_dsc_config *dsc) +static bool dpu_encoder_needs_dsc_merge(struct drm_encoder *drm_enc) { - struct msm_display_topology topology = {0}; - int i, intf_count = 0; + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); + u32 num_intf = 0; + u32 num_dsc = 0; + int i; for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) if (dpu_enc->phys_encs[i]) - intf_count++; - - /* Datapath topology selection - * - * Dual display - * 2 LM, 2 INTF ( Split display using 2 interfaces) - * - * Single display - * 1 LM, 1 INTF - * 2 LM, 1 INTF (stream merge to support high resolution interfaces) - * - * Add dspps to the reservation requirements if ctm is requested - */ - if (intf_count == 2) - topology.num_lm = 2; - else if (!dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm = 1; - else - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - - if (crtc_state->ctm) - topology.num_dspp = topology.num_lm; - - topology.num_intf = intf_count; + num_intf++; - if (dsc) { - /* - * In case of Display Stream Compression (DSC), we would use - * 2 DSC encoders, 2 layer mixers and 1 interface - * this is power optimal and can drive up to (including) 4k - * screens - */ - topology.num_dsc = 2; - topology.num_lm = 2; - topology.num_intf = 1; - } + /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ + if (dpu_enc->dsc) + num_dsc += 2; - return topology; + return (num_dsc > 0) && (num_dsc > num_intf); } -static int dpu_encoder_virt_atomic_check( - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state) { - struct dpu_encoder_virt *dpu_enc; - struct msm_drm_private *priv; - struct dpu_kms *dpu_kms; - struct drm_display_mode *adj_mode; - struct msm_display_topology topology; - struct msm_display_info *disp_info; - struct dpu_global_state *global_state; + struct drm_connector *connector; + struct drm_connector_state *conn_state; struct drm_framebuffer *fb; - struct drm_dsc_config *dsc; - int ret = 0; - - if (!drm_enc || !crtc_state || !conn_state) { - DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", - drm_enc != NULL, crtc_state != NULL, conn_state != NULL); - return -EINVAL; - } - - dpu_enc = to_dpu_encoder_virt(drm_enc); - DPU_DEBUG_ENC(dpu_enc, "\n"); - - priv = drm_enc->dev->dev_private; - disp_info = &dpu_enc->disp_info; - dpu_kms = to_dpu_kms(priv->kms); - adj_mode = &crtc_state->adjusted_mode; - global_state = dpu_kms_get_global_state(crtc_state->state); - if (IS_ERR(global_state)) - return PTR_ERR(global_state); + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); - trace_dpu_enc_atomic_check(DRMID(drm_enc)); + if (!drm_enc || !state) + return false; - dsc = dpu_encoder_get_dsc_config(drm_enc); + connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); + if (!connector) + return false; - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); + conn_state = drm_atomic_get_new_connector_state(state, connector); - /* - * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. - * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() - * earlier. - */ - if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { + if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { fb = conn_state->writeback_job->fb; - - if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) - topology.needs_cdm = true; - } else if (disp_info->intf_type == INTF_DP) { - if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) - topology.needs_cdm = true; + if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) { + if (!dpu_enc->cur_master->hw_cdm) + return true; + } else { + if (dpu_enc->cur_master->hw_cdm) + return true; + } } - if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) - crtc_state->mode_changed = true; - else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) - crtc_state->mode_changed = true; - /* - * Release and Allocate resources on every modeset - * Dont allocate when active is false. - */ - if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, crtc_state->crtc); + return false; +} - if (!crtc_state->active_changed || crtc_state->enable) - ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - crtc_state->crtc, &topology); - } +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) +{ + struct msm_drm_private *priv = drm_enc->dev->dev_private; + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); + int index = dpu_enc->disp_info.h_tile_instance[0]; - trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); + if (dpu_enc->disp_info.intf_type == INTF_DSI) + return msm_dsi_get_dsc_config(priv->dsi[index]); - return ret; + return NULL; +} + +bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) +{ + return dpu_encoder_needs_dsc_merge(drm_enc); } static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, @@ -2449,7 +2405,6 @@ static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, .atomic_disable = dpu_encoder_virt_atomic_disable, .atomic_enable = dpu_encoder_virt_atomic_enable, - .atomic_check = dpu_encoder_virt_atomic_check, }; static const struct drm_encoder_funcs dpu_encoder_funcs = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index f7465a1774aa..0d27e50384f0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -169,6 +169,25 @@ int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos); */ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc); +/** + * dpu_encoder_update_topology - update topology with the requirements for the encoder + * @drm_enc: Pointer to previously created drm encoder structure + * @topology: Topology to be updated + * @state: Current DRM atomic state + * @adj_mode: Current DRM display mode associated with the crtc + */ +void dpu_encoder_update_topology(struct drm_encoder *drm_enc, + struct msm_display_topology *topology, + struct drm_atomic_state *state, + const struct drm_display_mode *adj_mode); + +/** + * dpu_encoder_update_topology - update topology with the requirements for the encoder + * @drm_enc: Pointer to previously created drm encoder structure + * @topology: Current DRM atomic state + */ +bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state); + /** * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. * @drm_enc: Pointer to previously created drm encoder structure From patchwork Thu Aug 29 20:48:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823585 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E1B018B497; Thu, 29 Aug 2024 20:49:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964558; cv=none; b=G5LPdi9tBgXKD6pml3iI7Onqaht/E7ybqXX/7o3aBdPmcnGyh/ltCOYoPwQOKnlPg61eSqVytV7p6PKTkbYjjyPKL2ySsssndGr0P0iuR2EPER+OsAZhj7FgUkEgXOxibAzkxKbN2h7Ktm14qD6VkM5KWvAYslDSHy7VhNBSitI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964558; c=relaxed/simple; bh=6HvjfEhWQFY3huyz7vMEw2Z82rvFGUv2z2Uz0oW+7AM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jkmkeWZS0aLu4QJ86rCzUGKIX05wJ02Ek6X7R9MRwdh42csxsInbszicltrYuxG3V3TZB2P2hBUqPWBGP8b++p4m5NQKpMchGZXL+cTYgMCQ6TxcVD4/w3mKyx50/PYa5WPZW3KcfxFvaH75GDx4+u1wk1kRX7+BcohkpVjbzd0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DumiMlLx; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DumiMlLx" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGKTh9003416; Thu, 29 Aug 2024 20:49:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jBrx90YhSsmV3NSLJgtsBsDEa84oIzSMjdJL1CYo5PE=; b=DumiMlLxXIa/3cwO uTSGbiFDDZb418SsgCvfegZ/oTWggFd6KcIYkAtg3/9Z1Iq5NzKA+iromOJVbrd+ IC5hje0uRlJHd3qqNRNrFmhS+nkrEuFWq4Q8lII7hIlfpsWeUqqZqcaqbTlfO3QA k+rKRu/+DqwymfXd3n2ueCX3wAq54jOjwVwaaUU4gn2fcHhkH4VhM7K7Fyx+y/iP IzYkx0c/hp7TAh18iC7TRXsOHwUvex3mnfCe937jJKuP7VBrbSDoaUpVidSioOs4 Nkr/fxtgaTRFx9zv+0mLlqjip7MOo3ZnRSebkErqUDC2rMghXNj6B3W0rkbTxMWA va2XDg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419putxpbp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn1Nv020971 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:00 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:27 -0700 Subject: [PATCH 06/21] drm/msm/dpu: fill CRTC resources in dpu_crtc.c Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-6-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=4931; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=q16T7B3NimIh9lntrE0BMMwe7YT1wPhDvloEWCh46/Y=; b=Q42l22Hby4xvoktCWKvpAUKYg7GBTSMo4EIr1JBGd9+aCZBae4DshojLC9hhHQbxpGBDuRn4f IdWX0iSZEZWCGlTghmAIZJUsOiCdGJRNxD1+9tOEl8wC8n/awYIH12L X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sOXveLZRMevr1u2szjtXMzKj4aCFh1gM X-Proofpoint-GUID: sOXveLZRMevr1u2szjtXMzKj4aCFh1gM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 From: Dmitry Baryshkov Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources from dpu_crtc_assign_resources(). Signed-off-by: Dmitry Baryshkov [quic_abhinavk@quicinc.com: cleaned up formatting] Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 24 ++---------------------- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 3296b0650056..5ec1b5a38922 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1161,6 +1161,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) } #define MAX_HDISPLAY_SPLIT 1080 +#define MAX_CHANNELS_PER_CRTC 2 static struct msm_display_topology dpu_crtc_get_topology( struct drm_crtc *crtc, @@ -1205,9 +1206,14 @@ static struct msm_display_topology dpu_crtc_get_topology( static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { + struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC]; + struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC]; + int i, num_lm, num_ctl, num_dspp; struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); struct dpu_global_state *global_state; struct msm_display_topology topology; + struct dpu_crtc_state *cstate; int ret; /* @@ -1229,6 +1235,26 @@ static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_stat if (ret) return ret; + cstate = to_dpu_crtc_state(crtc_state); + + num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + crtc, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); + + for (i = 0; i < num_lm; i++) { + int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); + + cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); + cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); + if (i < num_dspp) + cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); + } + + cstate->num_mixers = num_lm; + return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index ada9119326ca..36b677cf9c7a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1049,14 +1049,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc; struct msm_drm_private *priv; struct dpu_kms *dpu_kms; - struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_pp, num_dsc; unsigned int dsc_mask = 0; int i; @@ -1083,13 +1080,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); - num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); - num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp, - ARRAY_SIZE(hw_dspp)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) @@ -1115,18 +1107,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } - cstate = to_dpu_crtc_state(crtc_state); - - for (i = 0; i < num_lm; i++) { - int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); - - cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); - cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); - cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); - } - - cstate->num_mixers = num_lm; - for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; From patchwork Thu Aug 29 20:48:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824070 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E1F818B498; Thu, 29 Aug 2024 20:49:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964557; cv=none; b=fMZWfovUuOsJySYUvjnEfsrQ7GDAvhEOTYKLl5xTd0ciRSoTGt7hwxSblEnU/7U6wjUc+O7QvLYJWyrmkBU/MAVKTDBycNxn/4QRF4fohPDgYgHIdVtESzjMdwUVmJNPI3zbJmiquL5zXH7wxgWw1QHjxW6lHKntgRyoQWvmuUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964557; c=relaxed/simple; bh=f5sIg4wgMLNdE3+UAOj+ZHkuNzYnLi/WcPHfusX2d3M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=dXuuIfofDwEApOPZqoQMSNGTqtqyhqdODpYGlQ022fKtu/b4OyY+inAvm/gpvM5ZhnHCOptzHuvY1s4iZZtpJ5CLqcQ+g6zmzw7pUVDBoBRg/oSewIYoh8oUh91r7oAXoHVhv32NgXPs+WXucYreRG6yHiHl3MQQMI669fOEvKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=lPcEFT9X; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="lPcEFT9X" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47THQoJY015412; Thu, 29 Aug 2024 20:49:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bofpdI2gbabYFx6LiDsw0TOf5qtpihr9aTfkXO0rKpk=; b=lPcEFT9XP/8BTSQU MXJq/7uArFLofuUFgHSPzVFW2SfMmVLmFE6s0ZowdG4+zsRfsoImIP0lwOJqepfz /jEG3yBDISoEE3BTeczcR/r9Fnwt2aH8meAa4FW5p77VQVer8aJS0nO1BCTQ0Gq2 oHW2VFyo7+s6UoYm1vfH35KDEsAlZw0J4eomcvb62UfyRvDv7Ej+hCl4KVWA9c9O RngtwKHyF28u1V/pkCwl+RDWvaUhxU1vznh6XgQ4t5BvuE9ygze/GtYWZJAYUrX8 pgxSagUeLrxzlK9DaKNtrPO5IwafIrtVC15rCUPByO4o5SttqS5FRtAHZgpCWAD0 vHHjoQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419px5pgwc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn1KJ015097 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:00 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:28 -0700 Subject: [PATCH 07/21] drm/msm/dpu: Check CRTC encoders are valid clones Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-7-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=2507; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=f5sIg4wgMLNdE3+UAOj+ZHkuNzYnLi/WcPHfusX2d3M=; b=EiuZK9aND+DH1dbOFOaAmpB/VPlex7J7foWCO9t29ZFC4J7eDrlfCuIDqBIymPTkf+7f4xnoz zL8OYwi1c0CBzqWvAFPYgrq1yNvwUa3D/X0wyTDMKw6zjBdJHsghBr0 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FxTCpGOas7SrAWo6MJaE9hD65tARmmZJ X-Proofpoint-GUID: FxTCpGOas7SrAWo6MJaE9hD65tARmmZJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Check that each encoder in the CRTC state's encoder_mask is marked as a possible clone for all other encoders in the encoder_mask and that only one CRTC is in clone mode at a time Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 36 +++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 5ec1b5a38922..bebae365c036 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -1204,6 +1204,36 @@ static struct msm_display_topology dpu_crtc_get_topology( return topology; } +static bool dpu_crtc_has_valid_clones(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + struct drm_encoder *drm_enc; + struct drm_crtc *temp_crtc; + int num_cwb_sessions = 0; + + drm_for_each_crtc(temp_crtc, crtc->dev) + if (drm_crtc_in_clone_mode(temp_crtc->state)) + num_cwb_sessions++; + + /* + * Only support a single concurrent writeback session running + * at a time + */ + if (num_cwb_sessions > 1) + return false; + + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) { + if ((crtc_state->encoder_mask & drm_enc->possible_clones) != + crtc_state->encoder_mask) { + DPU_ERROR("crtc%d failed valid clone check for mask 0x%x\n", + crtc->base.id, crtc_state->encoder_mask); + return false; + } + } + + return true; +} + static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; @@ -1287,6 +1317,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, return rc; } + if (drm_crtc_in_clone_mode(crtc_state) && + !dpu_crtc_has_valid_clones(crtc, crtc_state)) + return -EINVAL; + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, From patchwork Thu Aug 29 20:48:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824063 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7475F1BBBC3; Thu, 29 Aug 2024 20:49:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; cv=none; b=B4qPVz3nqm8l9qdVJF3cg48CoO5QtE6HjzrHCycG7e2XoJlh0xrMf+MrXGTBd1ii/Z9fVViWgH48vsqkBYLcQJGofOoexVxvZcVz4HNQoDngr/SSqdKoBn/aCNhUD7bTSvKeI274wj1ywkN2D+IuqwPrr6AMavoQSCj+FFgkiTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; c=relaxed/simple; bh=JkX9fQxiciPLoMTQdwQ4igRB4WUAo3Tm/RDa3hmZ4dU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XE5Bi48+8fRXdoVD3+6GXTXPb61Fh6SXN8nsElLL7FSChjMBBQY0mWANeRcVO0PjhJ+/cWZzPg1JK0TfYMWkdOcLpjTKn2Jb7WWsrYoLF51yv/tNT+/B5fI9mdgaLsm8wVesJOKyJTHT70hYoOVpeIULU27K09bERbKud3qSXP8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=bM2yjMsm; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="bM2yjMsm" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGteHm023072; Thu, 29 Aug 2024 20:49:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +ZeUUL918hB5/3j1/SiUmUATGuqYer+DI/apE79HVpA=; b=bM2yjMsmNgr3VNA0 g1rOXlqWhxnBtfj3VZV2TIwvBW/uKFRiZKtotWogClrKU2Lda6OXtQBZtYL+5y1l NOibqy11dtkmUrgmUpW2D6znrc4t5dpi5QiwzJvgaCMIliCUWtwzpfxitC5/7SDf GkQbN5U1dK769ppB9nil+DkhSsF+IFxNrtD/DT2VuLJp//m2O7ZupsX+PE49bG0X 3moYdQrttI2uFGVrLN+CDZDDtiuFZ2yCfqh41bRgzADyhg+2xfrYsaKT11Pmcejq 5AA4lJp+XaY+yY+pyH6Fe4sXofwQgDjQ5cTfajBkznoqyq19Awfi8NtbrMRX/h+6 tk9XFA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41a612mhra-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn1jH016028 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:01 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:29 -0700 Subject: [PATCH 08/21] drm/msm/dpu: add CWB entry to catalog for SM8650 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-8-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=7161; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=846JHV+mtQr7NiOLUZ1OiNov0n5kp+HPtQKYkefdNkM=; b=vjf8dkS2BsFm1NdR2IfWiV+o06plDp8niVADM23gwoVuQBsQ4nt8J51g2pyN0AS9fwVrF9Kf9 Q1JBA33gaFoDyDbslBBeiBUBpXPZqgF/5fxs7mY22qMNYSSZskjDYxc X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DwKBKJhkT12OhQMhYYPIEXTmVYsQ0qUv X-Proofpoint-ORIG-GUID: DwKBKJhkT12OhQMhYYPIEXTmVYsQ0qUv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 From: Esha Bharadwaj Add new block for concurrent writeback mux to HW catalog and change pingpong index names to distinguish between general use pingpong blocks and pingpong blocks dedicated for concurrent writeback Signed-off-by: Esha Bharadwaj Signed-off-by: Jessica Zhang --- .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 29 +++++++++++++++++++--- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 +-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 +-- .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 8 +++--- 6 files changed, 48 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index eb5dfff2ec4f..ce2773029763 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -252,25 +252,25 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { .merge_3d = MERGE_3D_2, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { - .name = "pingpong_6", .id = PINGPONG_6, + .name = "pingpong_6", .id = PINGPONG_CWB_0, .base = 0x66000, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { - .name = "pingpong_7", .id = PINGPONG_7, + .name = "pingpong_7", .id = PINGPONG_CWB_1, .base = 0x66400, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { - .name = "pingpong_8", .id = PINGPONG_8, + .name = "pingpong_8", .id = PINGPONG_CWB_2, .base = 0x7e000, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_4, }, { - .name = "pingpong_9", .id = PINGPONG_9, + .name = "pingpong_9", .id = PINGPONG_CWB_3, .base = 0x7e400, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, @@ -350,6 +350,25 @@ static const struct dpu_wb_cfg sm8650_wb[] = { }, }; +static const struct dpu_cwb_cfg sm8650_cwb[] = { + { + .name = "cwb_0", .id = CWB_0, + .base = 0x66200, .len = 0x8, + }, + { + .name = "cwb_1", .id = CWB_1, + .base = 0x66600, .len = 0x8, + }, + { + .name = "cwb_2", .id = CWB_2, + .base = 0x7E200, .len = 0x8, + }, + { + .name = "cwb_3", .id = CWB_3, + .base = 0x7E600, .len = 0x8, + }, +}; + static const struct dpu_intf_cfg sm8650_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -447,6 +466,8 @@ const struct dpu_mdss_cfg dpu_sm8650_cfg = { .merge_3d = sm8650_merge_3d, .wb_count = ARRAY_SIZE(sm8650_wb), .wb = sm8650_wb, + .cwb_count = ARRAY_SIZE(sm8650_cwb), + .cwb = sm8650_cwb, .intf_count = ARRAY_SIZE(sm8650_intf), .intf = sm8650_intf, .vbif_count = ARRAY_SIZE(sm8650_vbif), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index a1779c5597ae..c5c95c6654dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -257,13 +257,13 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { .merge_3d = MERGE_3D_2, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { - .name = "pingpong_6", .id = PINGPONG_6, + .name = "pingpong_6", .id = PINGPONG_CWB_0, .base = 0x65800, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { - .name = "pingpong_7", .id = PINGPONG_7, + .name = "pingpong_7", .id = PINGPONG_CWB_1, .base = 0x65c00, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index ad48defa154f..31c4a3025e51 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -251,13 +251,13 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .merge_3d = MERGE_3D_2, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { - .name = "pingpong_6", .id = PINGPONG_6, + .name = "pingpong_6", .id = PINGPONG_CWB_0, .base = 0x66000, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { - .name = "pingpong_7", .id = PINGPONG_7, + .name = "pingpong_7", .id = PINGPONG_CWB_1, .base = 0x66400, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index a3e60ac70689..24bb6b13eaba 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -251,13 +251,13 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { .merge_3d = MERGE_3D_2, .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { - .name = "pingpong_6", .id = PINGPONG_6, + .name = "pingpong_6", .id = PINGPONG_CWB_0, .base = 0x66000, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, .merge_3d = MERGE_3D_3, }, { - .name = "pingpong_7", .id = PINGPONG_7, + .name = "pingpong_7", .id = PINGPONG_CWB_1, .base = 0x66400, .len = 0, .features = BIT(DPU_PINGPONG_DITHER), .sblk = &sc7280_pp_sblk, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 37e18e820a20..b42d8b3640e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -621,6 +621,16 @@ struct dpu_wb_cfg { enum dpu_clk_ctrl_type clk_ctrl; }; +/* + * struct dpu_cwb_cfg : MDP CWB mux instance info + * @id: enum identifying this block + * @base: register base offset to mdss + * @features bit mask identifying sub-blocks/features + */ +struct dpu_cwb_cfg { + DPU_HW_BLK_INFO; +}; + /** * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting * @pps pixel per seconds @@ -823,6 +833,9 @@ struct dpu_mdss_cfg { u32 dspp_count; const struct dpu_dspp_cfg *dspp; + u32 cwb_count; + const struct dpu_cwb_cfg *cwb; + /* Add additional block data structures here */ const struct dpu_perf_cfg *perf; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index a2eff36a2224..c17d2d356f7a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -181,10 +181,10 @@ enum dpu_pingpong { PINGPONG_3, PINGPONG_4, PINGPONG_5, - PINGPONG_6, - PINGPONG_7, - PINGPONG_8, - PINGPONG_9, + PINGPONG_CWB_0, + PINGPONG_CWB_1, + PINGPONG_CWB_2, + PINGPONG_CWB_3, PINGPONG_S0, PINGPONG_MAX }; From patchwork Thu Aug 29 20:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823582 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140EB1BAEEC; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; cv=none; b=MjzTjrKe0bUSldaZBAp0IFG8JbwCHksOUI4mITkaMcOHMw+5l8WFB4Zv2eRv4qZmPTEAlI/u1j2cxSNuZPswgPaBZUSiuhxaEPQAMP0jOAzyt9VZQxF+BZYUODFIACOV7Gk4+cjAZX5l705bmSMwvdRmWMMvCyyfp53MxcDhQr0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; c=relaxed/simple; bh=rV38pUjQATMZW2bX0YqB44oTApf4ol9ff7trbEnkmx0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nVAwwEVd3+zQPxAyjUySC21JZJjtNwV0hwctwMH0V6eT4LvNuBhWD5Z1NcnOHSVq+mKdh29TYPb72NiYvkyjgUewzgjoZakuBjYskJnwbffkaBJ955ZosTOXuVgO6Gdz2bGF9ZJIpJfQCJGrgQoQXRB/qL3OGPU9LaJ9ovZ4fiA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Ve9U8gZY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Ve9U8gZY" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TI3mkN019847; Thu, 29 Aug 2024 20:49:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= r5mMPkv37s5CmsvZPmT50lWHA90Q444v18qNmMzX81Q=; b=Ve9U8gZYD54/WPQ7 87aJLjhtDwEYLhM4lkv1SZu32vq1mskPx/jh8eHfi9Fx6EJTDAA55ffWvC7EyW9s yIK+sBkLMCFpE9Cz6G6JI3DEGg16Xz3sDZYIJIfFPUYTr0NM8I1P/eNP0kwn0Mgf URvvApINDa0Hb7jhGxKuI0QksLUehd8Um40G69LSBrRukaUFFqf6kJIgFN2WSlo6 H9VP2j6QgLkqMVSBZohHi8AUzfSEfEk25K5sgi12EKq0BVGDkYXLG+DDq6LUQ9Jb nt7KOVlWSJUBPuUvnHufxT7gDCqeBwgHhvwB7mjiQET19T4fUkE/6I2/g2podLEe PXPFRA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419q2xxk9p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn1Rh016033 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:01 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:01 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:30 -0700 Subject: [PATCH 09/21] drm/msm/dpu: add devcoredumps for cwb registers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-9-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=1033; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=Lsi5u5MKQM9ftfBPtBVwmlyW3xI2JXKRPLVXT4zgDug=; b=QojlAhkJcCC3rY8YgpLUSeGPwWOlTAA/tCJnD9DooOIjG/Q5wRm2cgFTGKCCW+ENR1faazoW7 RSd0uIxNQ4KBJ3sAQaTROTe6dOF2W7f+7lZN9ccX1h4e0KaPATT8pPH X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Rj9g2N99kDFM6aPpq0-cwpzlu65rDZvc X-Proofpoint-GUID: Rj9g2N99kDFM6aPpq0-cwpzlu65rDZvc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290145 From: Esha Bharadwaj Implement instance of snapshot function to dump new registers used for cwb Signed-off-by: Esha Bharadwaj Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index d1e2143110f2..87526d3c224a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -989,6 +989,11 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k dpu_kms->mmio + cat->mdp[0].base, "top"); } + /* dump CWB sub-blocks HW regs info */ + for (i = 0; i < cat->cwb_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->cwb[i].len, + dpu_kms->mmio + cat->cwb[i].base, cat->cwb[i].name); + /* dump DSC sub-blocks HW regs info */ for (i = 0; i < cat->dsc_count; i++) { base = dpu_kms->mmio + cat->dsc[i].base; From patchwork Thu Aug 29 20:48:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823583 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A81411BAEC7; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964560; cv=none; b=n2IYvIjcnf0sdib4Z5W6/fMhwUIIPF9fyTxRL+4cieEnlpOutN/P9MqbkqX8pbwgnOyPafEiIBArgKkrjgbVaAU+I90Yg7Btov+Vq38PAJ5lMklXB2pZRPPQnJFD97924yM3kgjTHJbD7JTfWS8GKP3aBA4uQZg8y2uf+zVu94I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964560; c=relaxed/simple; bh=g8PMs0/5THp7pnWJ3sFUwG9OKDIcV4rcazSrk2PTfy0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XE+cEMAKFqxtbyB6eDO3n15Zzb4PALhcu75I37RI3ESdqHDVywjIJxnUNwbDq4V5DxBLQQqgkwGmcLyJtlXvLGWTmN9a8BzDoQDq5sgTE7N+NNaKTPDVp08mSR09SsWXsQvzndT8LRe8RxBLtPt/kRmJ8kTHFQYaL5Bf+c6hOAg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Psbpt5ba; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Psbpt5ba" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47THYNM7023078; Thu, 29 Aug 2024 20:49:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= s+G2kkMQ8TnXwCTM/TwOBgMy3uKDyGscra9WHgOwvYg=; b=Psbpt5baDbSIdHjZ 3vCAqVp/Y9m4101Q15aEtnCCPMG17ab5JNuT4Wb40tfrCd6NKxI2Pa+OAqnyHYrB cza6rfeEV2RUZ1v0vZpvCMeML02ddmvbFDbf1lW1OM+goeD69GghFGe0IP58yCwj DbZuDIOM8JXhmh0jCSLjwb5t0B0xMO1mZ2xgYYgYHe+23fEQXiOFVK7eMy85ba7l 8cIJfSnPKeicAw25X2cTRJjBauY8TkMCynSFYtgvAtSW6UrvLCnabF/zGfwjJoHN YqeTQpZaePzIzUAgGiwnxF2KrIh4h4eSb1ARh1w+UnoXNpdeWVZcBx4HxWTMlhTS yBOukg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41a612mhrb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn2Dn016049 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:01 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:31 -0700 Subject: [PATCH 10/21] drm/msm/dpu: add CWB support to dpu_hw_wb Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-10-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=5764; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=CINrKbIYUJRTpydRBpX5tiHGlXO142E4eg9FZgW+2ic=; b=my15j97ZNkfXH9f8DLhNeDBNnTzfqmVzDseeNEGuRlhREosKpf15KqEtTyDqUElOxzLMAIHNY d7NIbUkLChbDwxzKphIUYMCfia0TOxhhjctcbA/dedC/elyttMnKXYl X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oDkuOf6QudPc-DCfFwSL9tuc3EL0cz-q X-Proofpoint-ORIG-GUID: oDkuOf6QudPc-DCfFwSL9tuc3EL0cz-q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 From: Esha Bharadwaj Add function ops to allow hw_wb to configure CWB registers and adjust the WB_MUX configuration to account for using dedicated CWB pingpong blocks. Signed-off-by: Esha Bharadwaj Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 69 ++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 34 +++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index 93ff01c889b5..998c9fbd22a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -51,6 +51,12 @@ #define WB_CDP_CNTL 0x2B4 #define WB_OUT_IMAGE_SIZE 0x2C0 #define WB_OUT_XY 0x2C4 +#define CWB_MUX 0x000 +#define CWB_MODE 0x004 + +/* CWB mux block bit definitions */ +#define CWB_MUX_MASK GENMASK(3, 0) +#define CWB_MODE_MASK GENMASK(2, 0) static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *data) @@ -173,7 +179,9 @@ static void dpu_hw_wb_bind_pingpong_blk( mux_cfg = DPU_REG_READ(c, WB_MUX); mux_cfg &= ~0xf; - if (pp) + if (pp >= PINGPONG_CWB_0) + mux_cfg |= (pp < PINGPONG_CWB_2) ? 0xd : 0xb; + else if (pp) mux_cfg |= (pp - PINGPONG_0) & 0x7; else mux_cfg |= 0xf; @@ -237,3 +245,62 @@ struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev, return c; } + +static void dpu_hw_cwb_setup_input_ctrl(struct dpu_hw_wb *ctx, + enum dpu_cwb cwb_idx, + const enum dpu_pingpong pp) +{ + struct dpu_hw_blk_reg_map *c; + int cwb_mux_cfg = 0xF; + + if (cwb_idx < CWB_0 || cwb_idx >= CWB_MAX) + return; + + c = &ctx->cwb_hw[cwb_idx - CWB_0]; + + /* + * The CWB_MUX register takes the pingpong index relative to + * PINGPONG_CWB_0 and not PINGPONG_0 + */ + if ((pp != PINGPONG_NONE) && (pp < PINGPONG_MAX)) + cwb_mux_cfg = FIELD_PREP(CWB_MUX_MASK, pp - PINGPONG_CWB_0); + + DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg); +} + +static void dpu_hw_cwb_setup_input_mode(struct dpu_hw_wb *ctx, + enum dpu_cwb cwb_idx, + const enum cwb_mode_input input) +{ + struct dpu_hw_blk_reg_map *c; + int cwb_mux_cfg; + + if (cwb_idx < CWB_0 || cwb_idx >= CWB_MAX || input >= INPUT_MODE_MAX) + return; + + c = &ctx->cwb_hw[cwb_idx - CWB_0]; + cwb_mux_cfg = FIELD_PREP(CWB_MODE_MASK, input); + + DPU_REG_WRITE(c, CWB_MODE, cwb_mux_cfg); +} + +static void _setup_cwb_ops(struct dpu_hw_wb_ops *ops) +{ + ops->setup_input_ctrl = dpu_hw_cwb_setup_input_ctrl; + ops->setup_input_mode = dpu_hw_cwb_setup_input_mode; +} + +struct dpu_hw_wb *dpu_hw_wb_init_with_cwb(struct drm_device *dev, + const struct dpu_wb_cfg *cfg, + void __iomem *addr, + const struct dpu_mdss_version *mdss_rev, + struct dpu_hw_blk_reg_map *cwb_hw) +{ + struct dpu_hw_wb *c = dpu_hw_wb_init(dev, cfg, addr, mdss_rev); + + c->cwb_hw = cwb_hw; + + _setup_cwb_ops(&c->ops); + + return c; +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index 37497473e16c..1ff40f8325e5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -21,6 +21,12 @@ struct dpu_hw_wb_cfg { struct drm_rect crop; }; +enum cwb_mode_input { + INPUT_MODE_LM_OUT, + INPUT_MODE_DSPP_OUT, + INPUT_MODE_MAX +}; + /** * * struct dpu_hw_wb_ops : Interface to the wb hw driver functions @@ -31,6 +37,8 @@ struct dpu_hw_wb_cfg { * @setup_cdp: setup chroma down prefetch block for writeback block * @setup_clk_force_ctrl: setup clock force control * @bind_pingpong_blk: enable/disable the connection with ping-pong block + * @setup_ctrl: setup ctrl register for cwb + * @setup_mode: setup mode register for cwb */ struct dpu_hw_wb_ops { void (*setup_outaddress)(struct dpu_hw_wb *ctx, @@ -54,11 +62,20 @@ struct dpu_hw_wb_ops { void (*bind_pingpong_blk)(struct dpu_hw_wb *ctx, const enum dpu_pingpong pp); + + void (*setup_input_ctrl)(struct dpu_hw_wb *ctx, + enum dpu_cwb cwb_idx, + const enum dpu_pingpong pp); + + void (*setup_input_mode)(struct dpu_hw_wb *ctx, + enum dpu_cwb cwb_idx, + const enum cwb_mode_input input); }; /** * struct dpu_hw_wb : WB driver object * @hw: block hardware details + * @cwb_hw: block hardware details of cwb_muxes * @idx: hardware index number within type * @wb_hw_caps: hardware capabilities * @ops: function pointers @@ -66,6 +83,9 @@ struct dpu_hw_wb_ops { struct dpu_hw_wb { struct dpu_hw_blk_reg_map hw; + /* cwb data */ + struct dpu_hw_blk_reg_map *cwb_hw; + /* wb path */ int idx; const struct dpu_wb_cfg *caps; @@ -87,4 +107,18 @@ struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev, void __iomem *addr, const struct dpu_mdss_version *mdss_rev); +/** + * dpu_hw_wb_init_with_cwb() - Initializes the writeback hw driver object with cwb. + * @dev: Corresponding device for devres management + * @cfg: wb_path catalog entry for which driver object is required + * @addr: mapped register io address of MDP + * @hw: array of cwb muxes + * Return: Error code or allocated dpu_hw_wb context + */ +struct dpu_hw_wb *dpu_hw_wb_init_with_cwb(struct drm_device *dev, + const struct dpu_wb_cfg *cfg, + void __iomem *addr, + const struct dpu_mdss_version *mdss_rev, + struct dpu_hw_blk_reg_map *hw); + #endif /*_DPU_HW_WB_H */ From patchwork Thu Aug 29 20:48:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824066 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13D121BAEEA; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; cv=none; b=IqHhGFYEWHcNEX83pyzMRr0z7DQ2lWKZHrGWDWBUy+2vq2IEdZtbTDi0ixP3nM6EEIlYe6b+YFVi83qO9QAi7bL1lkJ9Fot1jKNDk12VR7JiFne1rzB8PdRBJqxe6zF7MIPyicDEfQtuEcHBoPiATsyt+d48wHemkKSoCN8yvDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; c=relaxed/simple; bh=g/6444LSdexGBzRzk11CQN1324zV0WLFsQMmtUfOVIo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=WpNoyY0K5TearMfUKJoGtuJ3xAtPHlJnoYiUmhpmC3/kaw9waA27i/LaaelFMdrECX7L8ppIv2DEoKdbg8zQlkJaRXbeO15zS0TmtkUVyK1Snd01AEZ6ThS0TVrPZcTUwSd2sEFr3H19AV3ptgjSAj2JQWdjsYLnqc8519VAvGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=R1jHdCmO; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="R1jHdCmO" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TIUtmu007794; Thu, 29 Aug 2024 20:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= B89Ltkh6etkL3tOFSAau8gpedGTqLIwCFaNGVkQkuIg=; b=R1jHdCmOKUSOfdJU 2zPeAl7BxllnHEKdGR70oUUamRdSymFsLvFDxJX8vWtw1FoFbbav7BYSwwIT/svB xT0t3rcti50urRQYCycdw00Jm99hJnj0zZvJT0yM5YayOf+cJ9tcQt5qe2uaPjmq sBdlPfDiV3fY+qm2qEc6eVVIHvWD7e4JwyCxsNIAt9wsMI3CxdXOO5/g5+zYuf8X t1oSpryoO5fn8HCZIL5gnmXQ+l1heJYvIQvLGkCM8KrcUN44vBUcpATGB4SKS5oQ 7celKPPXzOWGQOGptNG84nzfo4yxtOotierB+SlK+oPZflxLDWkFzsdwFnukttWP C4hmTg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419pv0en2c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn2Po025041 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:02 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:32 -0700 Subject: [PATCH 11/21] drm/msm/dpu: Add RM support for allocating CWB Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-11-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=3088; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=g/6444LSdexGBzRzk11CQN1324zV0WLFsQMmtUfOVIo=; b=Qa5mh0lUVcJp28u038tCDiuOAdcwKXiDzOd+mD/BNZtb9SVYsjXLeb9KCmIWhMhU8ZgDfgY1v rT+5JAPrH8BDNbfujnArXG0gqXXQn4CEZitzd6k07GDDHWGitaMsht9 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HXh35JNhRJ_F_4RG5oBzYBQVCgbtzYzE X-Proofpoint-ORIG-GUID: HXh35JNhRJ_F_4RG5oBzYBQVCgbtzYzE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Add support for allocating the concurrent writeback mux as part of the WB allocation Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 30 +++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index c17d2d356f7a..c43cb55fe1d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #ifndef _DPU_HW_MDSS_H @@ -352,6 +354,7 @@ struct dpu_mdss_color { #define DPU_DBG_MASK_DSPP (1 << 10) #define DPU_DBG_MASK_DSC (1 << 11) #define DPU_DBG_MASK_CDM (1 << 12) +#define DPU_DBG_MASK_CWB (1 << 13) /** * struct dpu_hw_tear_check - Struct contains parameters to configure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index bc99b04eae3a..738e9a081b10 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include "msm_drv.h" #define pr_fmt(fmt) "[drm:%s] " fmt, __func__ #include "dpu_kms.h" @@ -34,6 +35,7 @@ int dpu_rm_init(struct drm_device *dev, void __iomem *mmio) { int rc, i; + struct dpu_hw_blk_reg_map *cwb_reg_map; if (!rm || !cat || !mmio) { DPU_ERROR("invalid kms\n"); @@ -100,11 +102,35 @@ int dpu_rm_init(struct drm_device *dev, rm->hw_intf[intf->id - INTF_0] = hw; } + if (cat->cwb_count > 0) { + cwb_reg_map = drmm_kzalloc(dev, + sizeof(*cwb_reg_map) * cat->cwb_count, + GFP_KERNEL); + + if (!cwb_reg_map) { + DPU_ERROR("failed cwb object creation\n"); + return -ENOMEM; + } + } + + + for (i = 0; i < cat->cwb_count; i++) { + struct dpu_hw_blk_reg_map *cwb = &cwb_reg_map[i]; + + cwb->blk_addr = mmio + cat->cwb[i].base; + cwb->log_mask = DPU_DBG_MASK_CWB; + } + for (i = 0; i < cat->wb_count; i++) { struct dpu_hw_wb *hw; const struct dpu_wb_cfg *wb = &cat->wb[i]; - hw = dpu_hw_wb_init(dev, wb, mmio, cat->mdss_ver); + if (cat->cwb) + hw = dpu_hw_wb_init_with_cwb(dev, wb, mmio, + cat->mdss_ver, cwb_reg_map); + else + hw = dpu_hw_wb_init(dev, wb, mmio, cat->mdss_ver); + if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed wb object creation: err %d\n", rc); From patchwork Thu Aug 29 20:48:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823587 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E24C18B49B; Thu, 29 Aug 2024 20:49:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964556; cv=none; b=HvbFVOENmFp9kwv+Towa9mUOV8jCiVHoSXIlzEApJs9fiHAjaQBNLMIAdWGGDgqiESWc8Q1Auf5h9EzBuxJcbTJ5F9xInDuT7y+w3AWV3SC1rA2gb450XHBvkjRd2VK9h9MkEj3uLuMKaYnPMiVpiKylez4R5c65eFy5zEwNSWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964556; c=relaxed/simple; bh=Rbya/mrjMowdiYUE1WAOYhHd71m3omgRIHg88wluB/U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=oaRO6ANQCZFLza98K45i35+oDIpXNbnmfjiHpOpRO8G1uFGlxKiLrNvWISeWI2Vij+5GF6YrRqlPt9sEw/JerBMeA0OwxFPxV9uNsB5yqyPeCX0mu59WtpRQZ8Q1H3E5gSsjwsO1hHaf75EaGPjeIFu5V7N1GsBk0WRXEvHmSww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ZPkVKfD+; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZPkVKfD+" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47THCKM5018470; Thu, 29 Aug 2024 20:49:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2033E19ReffnKLA3txTIrglhZ5hjuKJ9RBVBBiQeY0M=; b=ZPkVKfD+4mxOGec9 exHI7t5SgZryya4t0p//ancYJ9t04rdeY0aduBu8z2V34Rg8+GQ7rLsGrLPNFTN2 d0SAb6i+8oiBfiP0YMSnwwxh+x2ZM2+LO6sOu/kpDIA7Am82e50Vm9TkFMmzc7Jh Ro65RR3qzx99uiC0QhEPydVSIZ3AVDKF4ftEtwtazEGYZPCSsjL3nC15FdWZTZ0O 83CvEg9mazBfP5WnakGLNQhTnTTRaVmfQe08TPjmvYBeBpGGVkNZ7Q1c1/TfoAuA oIRWuraLw8hmH1lIuPiEQoK7gifk7kVLoqDvd7rk1vhwgLG76vVxeNdGSRB32pqg oXJkLw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419putpnc4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn24B021005 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:02 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:33 -0700 Subject: [PATCH 12/21] drm/msm/dpu: Add CWB to msm_display_topology Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-12-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=2912; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=Rbya/mrjMowdiYUE1WAOYhHd71m3omgRIHg88wluB/U=; b=pG21aIK8mNIhSlqJXefB0XOSribXUBg+c93Q0rmJ2ofH+ugxsVwTrYu4etDnn/W4OMCY3vVne ItWgNJBu82gCf2Fkb9jtvLg4QyHPjrqWmQ2BKNqlYGUR7EfvYLWjxeg X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JgeTZ9PkjJkVJNGBn3rzB1mvrMirMXYn X-Proofpoint-ORIG-GUID: JgeTZ9PkjJkVJNGBn3rzB1mvrMirMXYn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Add the cwb_enabled flag to msm_display topology and adjust the toplogy to account for concurrent writeback Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 11 +++++++++-- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index bebae365c036..1b0cc899e8c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1176,6 +1176,8 @@ static struct msm_display_topology dpu_crtc_get_topology( dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, &crtc_state->adjusted_mode); + topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); + /* * Datapath topology selection * @@ -1189,9 +1191,9 @@ static struct msm_display_topology dpu_crtc_get_topology( * Add dspps to the reservation requirements if ctm is requested */ - if (topology.num_intf == 2) + if (topology.num_intf == 2 && !topology.cwb_enabled) topology.num_lm = 2; - else if (topology.num_dsc == 2) + else if (topology.num_dsc == 2 && !topology.cwb_enabled) topology.num_lm = 2; else if (dpu_kms->catalog->caps->has_3d_merge) topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 738e9a081b10..13f84375e15d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -384,8 +384,15 @@ static int _dpu_rm_reserve_ctls( int i = 0, j, num_ctls; bool needs_split_display; - /* each hw_intf needs its own hw_ctrl to program its control path */ - num_ctls = top->num_intf; + /* + * For non-CWB mode, each hw_intf needs its own hw_ctl to program its + * control path. Since only one CWB session can run at a time, hardcode + * num_ctls to 1 if CWB is enabled + */ + if (top->cwb_enabled) + num_ctls = 1; + else + num_ctls = top->num_intf; needs_split_display = _dpu_rm_needs_split_display(top); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index be016d7b4ef1..315895937832 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -88,6 +89,7 @@ struct msm_display_topology { u32 num_dspp; u32 num_dsc; bool needs_cdm; + bool cwb_enabled; }; /* Commit/Event thread specific structure */ From patchwork Thu Aug 29 20:48:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824067 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E72A71BAEE1; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964560; cv=none; b=hPjAmEtVMz/gwAt8kv++u5amGflk93/IWd22V1A7duplfOa1DHwcQZsTEeodhBIHVKQF0UwRBh9diTLw3AGuknyFF8fCiiy4AQJMxwyrL8WohQ1CzLMTv4cPP/FVv5Gu/Rici8z7Vunb9bM3UkL3bACH7CTFdL7jLKjT8sUJr1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964560; c=relaxed/simple; bh=ntWNPM9zed0TrpAd8XQwx6V/he1U41+q9IIsFiS/rS8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=KsigNokWIv09D/yfuFPXUgkY33Cxb2eBNm9wYzghnncY2SAsUlvTV/dx3x/aGbJBP+9EsuJrdPGvjGDuOTiLWapCdzrZGk/iydoAuRv357pSsHcbgxK1dMN0SjQNh1zJeOXyoQc53fP1jeOIXCQa8865dcrQLzESBHODLsSRbKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=g5V1+kLK; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="g5V1+kLK" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGJhVk011674; Thu, 29 Aug 2024 20:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= E7gtwkNLn7VJUCrVd+0zRRUvRDiACAhmYTbXL324Y6g=; b=g5V1+kLKalgeU1qF qe3RjfjlgaxjRsY7MRvMGSq4f7GsWF1MLsaBfAGwVpwAN5oNY7hpoeTi1V3Go9d2 POFXM2uUphTaGsgJvfv+PkDHBhwhV9F59njiHJ11/IB1g7gswIR9RTO53xneXtkB /JtAWNZwPOdVFK3egrH/mgb2uvktKNVnKihe/Slapn95AnqZjnkuVo3d6S3klXMb 58p7fGf39JYVmpeL31kgQVdym1czvWSCjRsjSIpp2U7inEqU+mno90xIYKbDz+LB 1/10Rs+1fuMK/I15k4bfETk7NHffPE3e2J2ydY4ue5UuGiTL6awLiQ+SyLTxcuXK xZsOBg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419pv0pq96-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn2N4025055 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:02 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:02 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:34 -0700 Subject: [PATCH 13/21] drm/msm/dpu: Require modeset if clone mode status changes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-13-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=1349; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=ntWNPM9zed0TrpAd8XQwx6V/he1U41+q9IIsFiS/rS8=; b=VtfwJZY0OA8Jg/mqwkYAu4txG55/DICgCjxqJC4HgisA1y03G+ACkD0eB5SzjzC8KXi0EgyTX dPubGECOff3C11eT9/G4xAMug+lr0cBqfA6yEa/afMhRwIKpI580Qe3 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VwdSpyyoZhWTb7cz3WCvKd39GesnoTWC X-Proofpoint-ORIG-GUID: VwdSpyyoZhWTb7cz3WCvKd39GesnoTWC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 If the clone mode enabled status is changing, a modeset needs to happen so that the resources can be reassigned Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 1b0cc899e8c1..99eaaca405a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1306,6 +1306,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, int rc = 0; bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); + bool clone_mode_requested = drm_crtc_in_clone_mode(crtc->state); + bool clone_mode_enabled = drm_crtc_in_clone_mode(crtc_state); /* there might be cases where encoder needs a modeset too */ drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) { @@ -1313,6 +1315,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc_state->mode_changed = true; } + if ((clone_mode_requested && !clone_mode_enabled) || + (!clone_mode_requested && clone_mode_enabled)) + crtc_state->mode_changed = true; + if (drm_atomic_crtc_needs_modeset(crtc_state)) { rc = dpu_crtc_assign_resources(crtc, crtc_state); if (rc < 0) From patchwork Thu Aug 29 20:48:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824068 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EE721BA286; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964559; cv=none; b=TJ5a42vj9jI0qP3z0BPlrTV+Fkf25rttvU1W0LyKlZc2oeLyVRAIAL6rK67U2nyJ4mfR2h9orLf9v24uyjqvt3l4hnTp/Z4QTcF5K7QG/AhJHh7Ffc6ks74Bof0/RRxK+EpmKGOgwVtkqQRlB5YHjssG2azKdlSBrvOP25/EFX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964559; c=relaxed/simple; bh=KXLjepDBneJjSHty/aXZSXhstveeaM7nUatiLHjqo48=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=p1rr8GGvhBSnBQyyZDkcT8yIEWceHL7R0R+kzgd31YKUeRK1ECi7vqYBKUP3IZWCMd+1uKHgQZjz8eq5HFemnHSP5jBYPXEh+GU6FvcjZ1tiWl0G6Mkn1sxtLXRYJEl1ucrYxMuEcKOBp/v3/c8t5iUhTSBlohae0gR6E8hHQPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NCJiajVc; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NCJiajVc" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47THEpXM019321; Thu, 29 Aug 2024 20:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4GAK/z9YiqfLV1y4jyEzvDZoUYIJTuKn1mU2EbXrCHI=; b=NCJiajVcJdLdmSdl BUOl6I99yzbT845ACkTabkr2OIHcjz8nZjwNoAarwa5fc6XVnWNO5+oUZ/PocqCp 2xgCw/f7b3l2EMu5a8Gww7jTpWo4GXio3RhfmfdqDQQYhjn6UWo5HjmeywwyYo+/ 66oWpQ1srCWphDUqUlvX4aJ6vnoxrZ0r4kgZubthWVfDomAXx0HVK4T/OTbfbjR+ zPcYIeUsH1VrykJ9BFKcs2lSCPsnsAT8gW+wMA7B47HOF+niuYwrqrcrlK9BwzVL bGZuyxiqjWR4gUXtZBMIJHiLsvrY6M6ogRN5WmPxg/fX7A4T67DXkTdF5Rmx7TbU O2yBJQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419putpnc5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn369003416 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:02 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:35 -0700 Subject: [PATCH 14/21] drm/msm/dpu: Reserve resources for CWB Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-14-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=5847; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=KXLjepDBneJjSHty/aXZSXhstveeaM7nUatiLHjqo48=; b=BO5r5FtR0LOmIolXR5pVT52HfZSloODTzv9XcB6f/AyPlNH3LVGGuviIZJzd90Qznk58djJCO JoDFjYtZQe6CArnO13KEpzbbY/i5KwPQ/MnECX0Ku+u49caNcSmmY2A X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZIE72Bm0DEE-IhELrYbNtj3NA3t5h30U X-Proofpoint-ORIG-GUID: ZIE72Bm0DEE-IhELrYbNtj3NA3t5h30U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Reserve dedicated pingpong blocks for CWB Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 ++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 65 +++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 36b677cf9c7a..f1bd14d1f89e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2013 Red Hat * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Author: Rob Clark */ @@ -1054,6 +1054,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; int num_pp, num_dsc; + bool is_cwb_encoder; unsigned int dsc_mask = 0; int i; @@ -1067,6 +1068,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); + is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) && + dpu_enc->disp_info.intf_type == INTF_WB; global_state = dpu_kms_get_existing_global_state(dpu_kms); if (IS_ERR_OR_NULL(global_state)) { @@ -1077,9 +1080,15 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, trace_dpu_enc_mode_set(DRMID(drm_enc)); /* Query resource that have been reserved in atomic check step. */ - num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, - ARRAY_SIZE(hw_pp)); + if (is_cwb_encoder) + num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->crtc, DPU_HW_BLK_DCWB_PINGPONG, hw_pp, + ARRAY_SIZE(hw_pp)); + else + num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, + ARRAY_SIZE(hw_pp)); + dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index c43cb55fe1d2..c87790a1b940 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -77,6 +77,7 @@ enum dpu_hw_blk_type { DPU_HW_BLK_LM, DPU_HW_BLK_CTL, DPU_HW_BLK_PINGPONG, + DPU_HW_BLK_DCWB_PINGPONG, DPU_HW_BLK_INTF, DPU_HW_BLK_WB, DPU_HW_BLK_DSPP, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 13f84375e15d..afad26556cd5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -236,6 +236,48 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) return -EINVAL; } +static int _dpu_rm_reserve_cwb_pingpong(struct dpu_rm *rm, + struct dpu_global_state *global_state, uint32_t crtc_id, + struct msm_display_topology *topology) +{ + int num_cwb_pp = topology->num_lm, cwb_pp_count = 0; + int cwb_pp_idx[MAX_BLOCKS]; + + /* + * Reserve additional dedicated CWB pingpong blocks for each mixer + * + * TODO: add support for reserving non-dedicated CWB pingpong blocks + */ + for (int i = 0; i < ARRAY_SIZE(rm->mixer_blks) && + cwb_pp_count < num_cwb_pp; i++) { + for (int j = PINGPONG_CWB_0 - PINGPONG_0; + j < ARRAY_SIZE(rm->pingpong_blks); j++) { + /* + * Odd LMs must be assigned to odd pingpongs and even + * LMs with even pingpongs + */ + if (reserved_by_other(global_state->pingpong_to_crtc_id, + j, crtc_id) || + i % 2 != j % 2) + continue; + + cwb_pp_idx[cwb_pp_count] = j; + cwb_pp_count++; + break; + } + } + + if (cwb_pp_count != num_cwb_pp) { + DPU_ERROR("Unable to reserve all cwb pingpongs\n"); + return -ENAVAIL; + } + + for (int i = 0; i < cwb_pp_count; i++) + global_state->pingpong_to_crtc_id[cwb_pp_idx[i]] = crtc_id; + + return 0; +} + /** * _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets * proposed use case requirements, incl. hardwired dependent blocks like @@ -617,6 +659,14 @@ static int _dpu_rm_make_reservation( return ret; } + if (topology->cwb_enabled) { + ret = _dpu_rm_reserve_cwb_pingpong(rm, global_state, + crtc_id, topology); + if (ret) { + DPU_ERROR("unable to find appropriate dcwb pingpongs\n"); + return ret; + } + } ret = _dpu_rm_reserve_ctls(rm, global_state, crtc_id, topology); @@ -706,6 +756,7 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, switch (type) { case DPU_HW_BLK_PINGPONG: + case DPU_HW_BLK_DCWB_PINGPONG: hw_blks = rm->pingpong_blks; hw_to_crtc_id = global_state->pingpong_to_crtc_id; max_blks = ARRAY_SIZE(rm->pingpong_blks); @@ -745,6 +796,20 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, if (hw_to_crtc_id[i] != crtc_id) continue; + if (type == DPU_HW_BLK_PINGPONG) { + struct dpu_hw_pingpong *pp = to_dpu_hw_pingpong(hw_blks[i]); + + if (pp->idx >= PINGPONG_CWB_0) + continue; + } + + if (type == DPU_HW_BLK_DCWB_PINGPONG) { + struct dpu_hw_pingpong *pp = to_dpu_hw_pingpong(hw_blks[i]); + + if (pp->idx < PINGPONG_CWB_0) + continue; + } + if (num_blks == blks_size) { DPU_ERROR("More than %d resources assigned to crtc %d\n", blks_size, crtc_id); From patchwork Thu Aug 29 20:48:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823578 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 864CA1BBBC7; Thu, 29 Aug 2024 20:49:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; cv=none; b=CHyxmYeSEoCJwsJzBYiZSH0PQ1dRI6KOtFY2lw6rC5BAofIg8SI0ihatjZ6SYU1eqC+c9vW6kNuSalFGbR3ZPCHHdPTB26eFaXufb5ury0Mo05TD8VaUGNcXg3UVM9HTd2bh8xSLEzbUSdO3OntCyOWSefRPXgHSe92yzafkQgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; c=relaxed/simple; bh=Ig2dAomey3G6s4V4jnd4i3M6aLIJuteSLsPKXtBejrI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ZkhjPhsX/wJa9mD7MzMiHHWRoGC8sEYarnOb0NXv77q4sPAtz7ePoQJnvyyQVUAYJojECokDjSqN2A5pG79mNQDTVYxf1GPaPIGT1v8TqfV7si+Y1zWY3C4ax1fy3NXfKtNjXrwoTjovm6x9TyM1JNnMRJQ4UbnszYc9lN1sWWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=mLFkgvqr; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="mLFkgvqr" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47THVEd9029336; Thu, 29 Aug 2024 20:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Aa6lH7sPEGG7HqGc3eIoP4ElKkQXZh63Yi660WPiEck=; b=mLFkgvqr7m9knRPM siDbcNhenRbNq3BR/DMFjhxmm2SZo9TVMkXCES8l/YUq3jeEqassJNA8b4cHcB0O Na/fKhar6zJgA1YJ8uC4wE07/kDNeAFgbKjZ7GtJMKoF/ouzeORiuVmxF7XZPvI3 y5RtNi1+RaJlAqihbe+WzSxd/8AvUI6G93DnUu1IkZ4c2XAJYat2ked9rZHTooPx /PGQcOfHKZK4qWZJcMhOjiUq1eoYuYkf2/H05L4pQZusj1oTeTVd/c4iVJoad4LW h1Hvz1c5zhrxtY/q+xxNNydSEwwYJsoyZvTpqbPMCOVwJS4botAp7/Ecg0wD+zfn 3sBxBA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419puuehx6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn3BB003473 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:03 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:36 -0700 Subject: [PATCH 15/21] drm/msm/dpu: Configure CWB in writeback encoder Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-15-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=9855; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=Ig2dAomey3G6s4V4jnd4i3M6aLIJuteSLsPKXtBejrI=; b=z2PUYpbsZSrguh/9tjKnp3t89OKbCp3ICRtD9j//AO9ytLz5E//vIsS7xqIxjzjgHThy7qk50 FgmBfsJ4MZXDN5D23rqU69eRczg6pJ14VMtNwAwvAmL88X1J3F5qFRI X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7sXBfK8wyAS__NvfSxyaEwxrjagJt5_W X-Proofpoint-ORIG-GUID: 7sXBfK8wyAS__NvfSxyaEwxrjagJt5_W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Cache the CWB block mask in the DPU virtual encoder and configure CWB according to the CWB block mask within the writeback phys encoder Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 29 +++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 43 ++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 9 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 18 ++++++++- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 43 +++++++++++++++++++++- 5 files changed, 139 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 99eaaca405a4..c8ef59af444c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1236,6 +1236,33 @@ static bool dpu_crtc_has_valid_clones(struct drm_crtc *crtc, return true; } +static void dpu_crtc_set_encoder_cwb_mask(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + struct drm_encoder *drm_enc; + struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); + int cwb_idx = 0; + u32 cwb_mask = 0; + + /* + * Since there can only be one CWB session at a time, if the CRTC LM + * starts with an even index we start with CWB_0. If the LM index is + * odd, we start with CWB_1 + */ + if (cstate->mixers[0].hw_lm) + cwb_idx = (cstate->mixers[0].hw_lm->idx - LM_0) % 2; + + if (drm_crtc_in_clone_mode(crtc_state)) { + for (int i = 0; i < cstate->num_mixers; i++) { + cwb_mask |= (1 << cwb_idx); + cwb_idx++; + } + } + + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) + dpu_encoder_set_cwb_mask(drm_enc, cwb_mask); +} + static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; @@ -1329,6 +1356,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, !dpu_crtc_has_valid_clones(crtc, crtc_state)) return -EINVAL; + dpu_crtc_set_encoder_cwb_mask(crtc, crtc_state); + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f1bd14d1f89e..0f8f6c0182d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -162,6 +162,7 @@ enum dpu_enc_rc_states { * clks and resources after IDLE_TIMEOUT time. * @topology: topology of the display * @idle_timeout: idle timeout duration in milliseconds + * @cwb_mask: current encoder is in clone mode * @wide_bus_en: wide bus is enabled on this interface * @dsc: drm_dsc_config pointer, for DSC-enabled encoders */ @@ -202,6 +203,7 @@ struct dpu_encoder_virt { struct msm_display_topology topology; u32 idle_timeout; + u32 cwb_mask; bool wide_bus_en; @@ -638,6 +640,33 @@ bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_st return false; } +void dpu_encoder_set_cwb_mask(struct drm_encoder *enc, u32 cwb_mask) +{ + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(enc); + + dpu_enc->cwb_mask = cwb_mask; +} + +u32 dpu_encoder_get_cwb_mask(struct drm_encoder *enc) +{ + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(enc); + + if (!dpu_enc) + return 0; + + return dpu_enc->cwb_mask; +} + +bool dpu_encoder_in_clone_mode(struct drm_encoder *enc) +{ + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(enc); + + if (!dpu_enc) + return 0; + + return dpu_enc->cwb_mask != 0; +} + struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) { struct msm_drm_private *priv = drm_enc->dev->dev_private; @@ -2019,6 +2048,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; struct dpu_hw_intf_cfg intf_cfg = { 0 }; int i; + enum dpu_cwb cwb_idx; struct dpu_encoder_virt *dpu_enc; dpu_enc = to_dpu_encoder_virt(phys_enc->parent); @@ -2040,6 +2070,19 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) /* mark WB flush as pending */ if (phys_enc->hw_ctl->ops.update_pending_flush_wb) phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); + + if (dpu_enc->cwb_mask) { + for (i = 0; i < hweight32(dpu_enc->cwb_mask); i++) { + if (!(dpu_enc->cwb_mask & (1 << i))) + continue; + + cwb_idx = i + CWB_0; + + if (phys_enc->hw_wb->ops.setup_input_ctrl) + phys_enc->hw_wb->ops.setup_input_ctrl(phys_enc->hw_wb, + cwb_idx, PINGPONG_NONE); + } + } } else { for (i = 0; i < dpu_enc->num_phys_encs; i++) { if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 0d27e50384f0..131bb8b2c0ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -188,6 +188,13 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc, */ bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state); +/** + * dpu_encoder_set_cwb_mask - set the CWB blocks mask for the encoder + * @drm_enc: Pointer to previously created drm encoder structure + * @cwb_mask: CWB blocks mask to set for the encoder + */ +void dpu_encoder_set_cwb_mask(struct drm_encoder *drm_enc, u32 cwb_mask); + /** * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. * @drm_enc: Pointer to previously created drm encoder structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index e77ebe3a68da..f0e5c5b073e5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. */ @@ -339,6 +339,22 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( */ unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +/** + * dpu_encoder_get_cwb_mask - get CWB blocks mask for DPU encoder + * This helper function is used by physical encoders to get the CWB blocks + * mask used for this encoder. + * @enc: Pointer to DRM encoder structure + */ +u32 dpu_encoder_get_cwb_mask(struct drm_encoder *enc); + +/** + * dpu_encoder_in_clone_mode - determine if DPU encoder is in clone mode + * This helper is used by physical encoders to determine if the encoder is in + * clone mode. + * @enc: Pointer to DRM encoder structure + */ +bool dpu_encoder_in_clone_mode(struct drm_encoder *enc); + /** * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder * This helper function is used by physical encoder to get DSC config diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 882c717859ce..e1ec64ffc742 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ @@ -264,6 +264,45 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc) } } +static void dpu_encoder_phys_wb_setup_cwb(struct dpu_encoder_phys *phys_enc) +{ + struct dpu_hw_wb *hw_wb; + struct dpu_hw_ctl *hw_ctl; + struct dpu_hw_pingpong *hw_pp; + u32 cwb_mask, cwb_idx; + + if (!phys_enc) + return; + + hw_wb = phys_enc->hw_wb; + hw_ctl = phys_enc->hw_ctl; + hw_pp = phys_enc->hw_pp; + + if (!hw_wb || !hw_ctl || !hw_pp) { + DPU_DEBUG("[wb:%d] no ctl or pp assigned\n", hw_wb->idx - WB_0); + return; + } + + cwb_mask = dpu_encoder_get_cwb_mask(phys_enc->parent); + + for (int i = 0; i < hweight32(cwb_mask); i++) { + if (!(cwb_mask & (1 << i))) + continue; + + cwb_idx = i + CWB_0; + + if (hw_wb->ops.setup_input_ctrl) + hw_wb->ops.setup_input_ctrl(hw_wb, cwb_idx, hw_pp->idx + i); + + /* + * The CWB mux supports using LM or DSPP as tap points. For now, + * always use DSPP tap point + */ + if (hw_wb->ops.setup_input_mode) + hw_wb->ops.setup_input_mode(hw_wb, cwb_idx, INPUT_MODE_DSPP_OUT); + } +} + /** * _dpu_encoder_phys_wb_update_flush - flush hardware update * @phys_enc: Pointer to physical encoder @@ -342,6 +381,8 @@ static void dpu_encoder_phys_wb_setup( dpu_encoder_helper_phys_setup_cdm(phys_enc, dpu_fmt, CDM_CDWN_OUTPUT_WB); + dpu_encoder_phys_wb_setup_cwb(phys_enc); + dpu_encoder_phys_wb_setup_ctl(phys_enc); } From patchwork Thu Aug 29 20:48:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824062 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE8151BBBD9; Thu, 29 Aug 2024 20:49:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964563; cv=none; b=uLXuctF77s3uksxOiWK7KKxwU+Wmpl1RJ3jkW95/ih24iC5xIoJzwT/t/kk+c+UrbP+dAU19l02lZYxQeD36SmSHqWaPJEbmbp6Kw0Re99+Ez/2E6IVjSxjt7+/OzJGMedbCffZzgmwXnhPKEsF8diV2ZfXUfGykt6/KB96AHEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964563; c=relaxed/simple; bh=TvS7kqWVhkk04g2QK4/rFaLgMhi7+1NbU6nSMKHgF9o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ohs0Qikt2zcYNFG+dCSlVsEIgJ2PzH1j2VwKpp0Z4tH07Jg2W1EU6cqH7Ywt9m3YVN6YudP9RPwKBcCY3aoQ5c3qKzRZWJFbtNmw9zRYHZVTOxhEz/yGypB4/U0goWz1WN19hp2XoE3JX11wSbyUUEBUIUGzvU46OL6sNCDkJ98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Y/hRNcyt; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Y/hRNcyt" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGK98e024486; Thu, 29 Aug 2024 20:49:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= SmxPX7cEtCu+YKrM4/VjO7Xh4HTNFTAXD9bnzsqPX/U=; b=Y/hRNcytnTFnYONH aoTzgBJGwkr1ERIJ6v6KG+5pdz0M2yTvC/U6LSsxXrzj20HM4suvTvhu85SaOoH/ lDhPX4ANz4Ayfq001+xX0dw3pztydtCkhV8RCVKDP9B7g4ioBIHy+vM9LPdsvgzS fIXlX5HoyGE4iqLl5yktMxGLYMb8JtYxTtT9rw+dEIl4zXmnndCA4IcRDe6Gcr9r JASB8UEkzdThcOSK6XDLObIgghM6XcrqhXoeZlPrJhjD80wRFVs80MGbwD7xE3jO LZ6TauSIVopKnzrYzlpCSPFJSyOrttSEQ6dvZxfqxlJhzaQugnxlR+C1Z0G2E16z fLK+EQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419puvem38-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn3F9003476 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:03 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:37 -0700 Subject: [PATCH 16/21] drm/msm/dpu: Program hw_ctl to support CWB Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-16-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=10226; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=TvS7kqWVhkk04g2QK4/rFaLgMhi7+1NbU6nSMKHgF9o=; b=JmD4WVUvq8v06acHbuhd64BMEhjwMxrcovX8fBGm3vCy04/bHiShlC8Yy7REBZAeFULb4foMR P4OgiiUoERkB/hnmfsKZaCTtiVyiJsogFh5L8PH/NQtQd7GO0hOM8el X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KMjWvFU9BkxvcFtDxjNqN3neonQZ94Gl X-Proofpoint-GUID: KMjWvFU9BkxvcFtDxjNqN3neonQZ94Gl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Add support for configuring the CWB pending flush and active bits Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 +++++- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 13 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 30 +++++++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 14 +++++++++- 4 files changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 0f8f6c0182d5..bde385318018 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2081,6 +2081,10 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) if (phys_enc->hw_wb->ops.setup_input_ctrl) phys_enc->hw_wb->ops.setup_input_ctrl(phys_enc->hw_wb, cwb_idx, PINGPONG_NONE); + + /* mark CWB flush as pending */ + if (phys_enc->hw_ctl->ops.update_pending_flush_cwb) + phys_enc->hw_ctl->ops.update_pending_flush_cwb(ctl, cwb_idx); } } } else { @@ -2126,8 +2130,10 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) if (phys_enc->hw_intf) intf_cfg.intf = phys_enc->hw_intf->idx; - if (phys_enc->hw_wb) + if (phys_enc->hw_wb) { intf_cfg.wb = phys_enc->hw_wb->idx; + intf_cfg.cwb = dpu_enc->cwb_mask; + } if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index e1ec64ffc742..6d93e6ae442d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -236,6 +236,7 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc) intf_cfg.intf = DPU_NONE; intf_cfg.wb = hw_wb->idx; + intf_cfg.cwb = dpu_encoder_get_cwb_mask(phys_enc->parent); if (mode_3d && hw_pp && hw_pp->merge_3d) intf_cfg.merge_3d = hw_pp->merge_3d->idx; @@ -314,6 +315,7 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc) struct dpu_hw_pingpong *hw_pp; struct dpu_hw_cdm *hw_cdm; u32 pending_flush = 0; + u32 cwb_mask, cwb_idx; if (!phys_enc) return; @@ -322,6 +324,7 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc) hw_pp = phys_enc->hw_pp; hw_ctl = phys_enc->hw_ctl; hw_cdm = phys_enc->hw_cdm; + cwb_mask = dpu_encoder_get_cwb_mask(phys_enc->parent); DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); @@ -340,6 +343,16 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc) if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm) hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx); + for (int i = 0; i < hweight32(cwb_mask); i++) { + if (!(cwb_mask & (1 << i))) + continue; + + cwb_idx = i + CWB_0; + + if (hw_ctl->ops.update_pending_flush_cwb) + hw_ctl->ops.update_pending_flush_cwb(hw_ctl, cwb_idx); + } + if (hw_ctl->ops.get_pending_flush) pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2e50049f2f85..792687b010ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -31,12 +31,14 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_DSC_ACTIVE 0x0E8 #define CTL_WB_ACTIVE 0x0EC +#define CTL_CWB_ACTIVE 0x0F0 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_CDM_ACTIVE 0x0F8 #define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MERGE_3D_FLUSH 0x100 #define CTL_DSC_FLUSH 0x104 #define CTL_WB_FLUSH 0x108 +#define CTL_CWB_FLUSH 0x10C #define CTL_INTF_FLUSH 0x110 #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 @@ -53,6 +55,7 @@ #define PERIPH_IDX 30 #define INTF_IDX 31 #define WB_IDX 16 +#define CWB_IDX 28 #define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ #define CTL_INVALID_BIT 0xffff #define CTL_DEFAULT_GROUP_ID 0xf @@ -110,6 +113,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) ctx->pending_flush_mask = 0x0; ctx->pending_intf_flush_mask = 0; ctx->pending_wb_flush_mask = 0; + ctx->pending_cwb_flush_mask = 0; ctx->pending_merge_3d_flush_mask = 0; ctx->pending_dsc_flush_mask = 0; ctx->pending_cdm_flush_mask = 0; @@ -144,6 +148,9 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) if (ctx->pending_flush_mask & BIT(WB_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, ctx->pending_wb_flush_mask); + if (ctx->pending_flush_mask & BIT(CWB_IDX)) + DPU_REG_WRITE(&ctx->hw, CTL_CWB_FLUSH, + ctx->pending_cwb_flush_mask); if (ctx->pending_flush_mask & BIT(DSPP_IDX)) for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { @@ -310,6 +317,13 @@ static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx, ctx->pending_flush_mask |= BIT(WB_IDX); } +static void dpu_hw_ctl_update_pending_flush_cwb_v1(struct dpu_hw_ctl *ctx, + enum dpu_cwb cwb) +{ + ctx->pending_cwb_flush_mask |= BIT(cwb - CWB_0); + ctx->pending_flush_mask |= BIT(CWB_IDX); +} + static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, enum dpu_intf intf) { @@ -547,6 +561,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 dsc_active = 0; u32 wb_active = 0; + u32 cwb_active = 0; u32 mode_sel = 0; /* CTL_TOP[31:28] carries group_id to collate CTL paths @@ -561,6 +576,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); + cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE); dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); if (cfg->intf) @@ -569,12 +585,16 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->wb) wb_active |= BIT(cfg->wb - WB_0); + if (cfg->cwb) + cwb_active |= cfg->cwb; + if (cfg->dsc) dsc_active |= cfg->dsc; DPU_REG_WRITE(c, CTL_TOP, mode_sel); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); + DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active); DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); if (cfg->merge_3d) @@ -624,6 +644,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, struct dpu_hw_blk_reg_map *c = &ctx->hw; u32 intf_active = 0; u32 wb_active = 0; + u32 cwb_active = 0; u32 merge3d_active = 0; u32 dsc_active; u32 cdm_active; @@ -651,6 +672,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); } + if (cfg->cwb) { + cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE); + cwb_active &= ~cfg->cwb; + DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active); + } + if (cfg->wb) { wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); wb_active &= ~BIT(cfg->wb - WB_0); @@ -703,6 +730,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->update_pending_flush_merge_3d = dpu_hw_ctl_update_pending_flush_merge_3d_v1; ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1; + ops->update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1; ops->update_pending_flush_dsc = dpu_hw_ctl_update_pending_flush_dsc_v1; ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 4401fdc0f3e4..6972fc86d986 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DPU_HW_CTL_H @@ -51,6 +51,7 @@ struct dpu_hw_intf_cfg { enum dpu_ctl_mode_sel intf_mode_sel; enum dpu_cdm cdm; int stream_sel; + unsigned int cwb; unsigned int dsc; }; @@ -114,6 +115,15 @@ struct dpu_hw_ctl_ops { void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, enum dpu_wb blk); + /** + * OR in the given flushbits to the cached pending_(cwb_)flush_mask + * No effect on hardware + * @ctx : ctl path ctx pointer + * @blk : concurrent writeback block index + */ + void (*update_pending_flush_cwb)(struct dpu_hw_ctl *ctx, + enum dpu_cwb blk); + /** * OR in the given flushbits to the cached pending_(intf_)flush_mask * No effect on hardware @@ -258,6 +268,7 @@ struct dpu_hw_ctl_ops { * @pending_flush_mask: storage for pending ctl_flush managed via ops * @pending_intf_flush_mask: pending INTF flush * @pending_wb_flush_mask: pending WB flush + * @pending_cwb_flush_mask: pending CWB flush * @pending_dsc_flush_mask: pending DSC flush * @pending_cdm_flush_mask: pending CDM flush * @ops: operation list @@ -274,6 +285,7 @@ struct dpu_hw_ctl { u32 pending_flush_mask; u32 pending_intf_flush_mask; u32 pending_wb_flush_mask; + u32 pending_cwb_flush_mask; u32 pending_periph_flush_mask; u32 pending_merge_3d_flush_mask; u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; From patchwork Thu Aug 29 20:48:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823580 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8D811BB693; Thu, 29 Aug 2024 20:49:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; cv=none; b=H2F3AvPhnkGsHsFQXHkXbyCuAEBNUCQ/QwrOOiGViwVb1xVall1FV127dc3GPZDnivHzbFjlmuFivKiH7RHyjKoMB5DO281yjUtkqXqBwwX6DCDEvEtSQickSetPwSe3BtaIbJeIhEJKRaODJor3oZEuMP0ZMumGmih2sg9MWpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; c=relaxed/simple; bh=qr9zbrHz1IfgR0v5QAhtiuUxHXiifq2zI0rFpka/gLo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=lsfc21nxp5TVhvFoFtcRe3/e8CtFTlJbSVllJiZNKolm5oXHqV/vfmm5A2ME62j4i8kclN2jqVIMOxCGZil9jO2g5F/33aiKKWRwamB4p52ECnjLK4M8kVmLvgK9hf96wwcOO1pXt41pq7W5OEANdWPUfo1q37IL1ZpE9WlGf8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kp286JNq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kp286JNq" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TH1DSC001841; Thu, 29 Aug 2024 20:49:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= s6VOKBChpeKp8g++K4CVxALxydL3fMjjIA8D0S+g7dw=; b=kp286JNqzh5f4vXx JMG3JGOS9poez6GamkxPf1EMRB1nEdxZv6+1kAIgKoaI4MMYwS9dQuvjXyPf3JQw LpIY/xVS0gf78Sy9eE65F3jumthA9NacSGSkrSuQpRsqJpU34RYXgiKO5DCASX9e P6pzcPuWOffMimgqjdo3XxXjusgfpL7i4J36qo6YGhIgUEUDO0bUgfRV7wiP0Knd 00jGO4dMe68W9Fht2ENvNawUEcwDEi/ezJ4m+npPuLf/uwI3TVu9Wyyj9X7/Tpke RLuZip+41zNuRxemH6S5ETwA4heP5XMIVX5mCjcIMy5sBkdkuJS+LaSUBVGtbz1U f0rI+Q== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419puw6mx0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:05 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn3N3016075 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:03 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:03 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:38 -0700 Subject: [PATCH 17/21] drm/msm/dpu: Adjust writeback phys encoder setup for CWB Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-17-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=2503; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=qr9zbrHz1IfgR0v5QAhtiuUxHXiifq2zI0rFpka/gLo=; b=JDaKXJosEII1rf4Mtx5VXd4wix5aXSVEXrWrNde/oHJF2f1SgQ7dJzefJ5yy0ZZLMxMedVcgZ iCsd8qQVCv2Aw7byUciPwFvlykOTVp/mJAmN40blbes3v9ZS7biZV8w X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JzPOj3BFV3qHEQqE4Af6ZrnH0IVOYtf0 X-Proofpoint-GUID: JzPOj3BFV3qHEQqE4Af6ZrnH0IVOYtf0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Adjust QoS remapper, OT limit, and CDP parameters to account for concurrent writeback Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 6d93e6ae442d..56b5e44132da 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -68,7 +68,7 @@ static void dpu_encoder_phys_wb_set_ot_limit( ot_params.num = hw_wb->idx - WB_0; ot_params.width = phys_enc->cached_mode.hdisplay; ot_params.height = phys_enc->cached_mode.vdisplay; - ot_params.is_wfd = true; + ot_params.is_wfd = !dpu_encoder_in_clone_mode(phys_enc->parent); ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); ot_params.vbif_idx = hw_wb->caps->vbif_idx; ot_params.rd = false; @@ -111,7 +111,7 @@ static void dpu_encoder_phys_wb_set_qos_remap( qos_params.vbif_idx = hw_wb->caps->vbif_idx; qos_params.xin_id = hw_wb->caps->xin_id; qos_params.num = hw_wb->idx - WB_0; - qos_params.is_rt = false; + qos_params.is_rt = dpu_encoder_in_clone_mode(phys_enc->parent); DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n", qos_params.num, @@ -174,6 +174,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); struct dpu_hw_wb *hw_wb; struct dpu_hw_wb_cfg *wb_cfg; + u32 cdp_usage; if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { DPU_ERROR("invalid encoder\n"); @@ -182,6 +183,10 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, hw_wb = phys_enc->hw_wb; wb_cfg = &wb_enc->wb_cfg; + if (dpu_encoder_in_clone_mode(phys_enc->parent)) + cdp_usage = DPU_PERF_CDP_USAGE_RT; + else + cdp_usage = DPU_PERF_CDP_USAGE_NRT; wb_cfg->intf_mode = phys_enc->intf_mode; wb_cfg->roi.x1 = 0; @@ -199,7 +204,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf; hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format, - perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable); + perf->cdp_cfg[cdp_usage].wr_enable); } if (hw_wb->ops.setup_outaddress) From patchwork Thu Aug 29 20:48:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823584 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77D2718C329; Thu, 29 Aug 2024 20:49:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964558; cv=none; b=DciFZkYl5u6TjmrYQd0n6Lc1M80hBT/lfoNnKbUJYEI0JOCfaipvxEFycZh3r8yrl9ASFvSMETEbu94qZefmNSn/lbUSf9WK0ap/TxBCT17Dd+U04r/h14Wc8KigNtKI1U7XW7MnDPBodNHWrKek3gOMPrJmucWxn/qoaAnCSrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964558; c=relaxed/simple; bh=cfL8Euw5CQ5ocfSsUbpcXQrDGMxfXGdNhk8hzSy7o00=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Hv3lMyz48qekM1U4ko+4pXtxR+IUwY4RXPs3rjtkERXy4jZ/lceSoN+zA40F0CATIZ+r+CHO4RZS/i5Q7zWRd4x5MjJRCzDz1OU7BlvJ5fDVvAN/aLfnJYRW5tX1+jHsafax7y3UxYauZQHx0CPw09viWeRVyyK5iR4OVIG1w/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=leWIs5qV; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="leWIs5qV" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TIFXkH013558; Thu, 29 Aug 2024 20:49:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= cLRCZ6v/RUbsyfmenr87SnfueJvcAidRqgQTZ1+GbrU=; b=leWIs5qV358nyN76 gOESLjHPzcDD8GaiZswKHwGFZsKuDDRceJhk3aAeB/qryBOavy47TZ3U58z5Gtm2 dhzcDEYy2DbLNUcDrjmckqMyCrbuwxckmTB2kRyIJZyFHElbNX43ByaIXz0MBmHU s/LjYaQOdb6PWYDqWggpMTAKmNkRG4H+ELfQN+rDZQU3yHs/V0Y5S6BCzDd0VLk/ gSJIw3UD6wCXUOEH4n6lodCf/dwOQMuPKde2QMAHXRX1Ahw6eAC5JswDJ8+WpCoB lxZivqLCdLyGTa0+vpgRi+ctqWPEhaMEDFsuHGZQPc6OImFQpFPOUds7XyXSw0iR ksU2Vw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419px5pgwg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn4ma015152 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:03 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:39 -0700 Subject: [PATCH 18/21] drm/msm/dpu: Start frame done timer after encoder kickoff Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-18-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=3077; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=cfL8Euw5CQ5ocfSsUbpcXQrDGMxfXGdNhk8hzSy7o00=; b=4bdfesOXhC54fzDlSTWkE3HRCOC67wQvuP2cAVOx/OxDRBXsMsJnw94e0/Ymk7rCc3uAvDzLj ZHKNckfWzoDAR/taSGbb+KwfkKUTEOD4e2VK/Absn89z6GOnKYKKApr X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: QIvjX0DQKzi105XaD20MBItXilBJOmOl X-Proofpoint-GUID: QIvjX0DQKzi105XaD20MBItXilBJOmOl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Create a separate API for starting the encoder frame done timer and call it after the encoder kickoff is finished Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 21 ++++++++++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 1 + 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index c8ef59af444c..daf5f751f584 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -970,8 +970,10 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) dpu_vbif_clear_errors(dpu_kms); - drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { dpu_encoder_kickoff(encoder); + dpu_encoder_start_frame_done_timer(encoder); + } reinit_completion(&dpu_crtc->frame_done_comp); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index bde385318018..9d495a186eb8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1945,18 +1945,12 @@ bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) return true; } -void dpu_encoder_kickoff(struct drm_encoder *drm_enc) +void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; - struct dpu_encoder_phys *phys; unsigned long timeout_ms; - unsigned int i; - DPU_ATRACE_BEGIN("encoder_kickoff"); dpu_enc = to_dpu_encoder_virt(drm_enc); - - trace_dpu_enc_kickoff(DRMID(drm_enc)); - timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); @@ -1964,6 +1958,19 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc) mod_timer(&dpu_enc->frame_done_timer, jiffies + msecs_to_jiffies(timeout_ms)); +} + +void dpu_encoder_kickoff(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + struct dpu_encoder_phys *phys; + unsigned int i; + + DPU_ATRACE_BEGIN("encoder_kickoff"); + dpu_enc = to_dpu_encoder_virt(drm_enc); + + trace_dpu_enc_kickoff(DRMID(drm_enc)); + /* All phys encs are ready to go, trigger the kickoff */ _dpu_encoder_kickoff_phys(dpu_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 131bb8b2c0ee..7ab5f9380bf5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -216,5 +216,6 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, * @drm_enc: Pointer to drm encoder structure */ bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc); +void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc); #endif /* __DPU_ENCODER_H__ */ From patchwork Thu Aug 29 20:48:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823579 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE3A18C00A; Thu, 29 Aug 2024 20:49:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; cv=none; b=OIExCgowO51POdz7HHI1pSwWn0dX6QkK1Zg4Tz5U4EKalHjZnJfx8JbEK1b+YYOhm9HxdMyoCI/Jjr+cuXBBgCjifmeiMp5e+9lIPyvDHDfTAnPfjxhe2EGGlKtp+kQdoz2BxzUwChnb+LQxy1KVxi+yApVUNH5D52VUcRQ2Qjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; c=relaxed/simple; bh=EsK89cuQd4E/Olk9CLDiqKxnZJMyBEVg2nofQkF5Db4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qrp8Po6Ucvne8gXPbhF0siF8sFEUmKkNdqbNEVe48lKpYlcQWuJO0+h2QAGdouHk9Z68fmO6t28cNd3gJ2eyRnWVaHmIdMSnlKikX2142JArGpIRYWCj75EsonlzXCscboTh3HrJEP0McaQff7DuOwrGfrUk7rC3zHTa/IOsbW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Cj9+ES1I; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Cj9+ES1I" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TIGteV028780; Thu, 29 Aug 2024 20:49:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= B9xmPE3LcEFtsnje+NXk1JzGDpi3cJIN0kHrvQdUo6k=; b=Cj9+ES1IF8B1d7bM 2fGu/M4hBYlCrBSHG6PR8sD03n3Nj8een8PpQRbvPn187Xam6ByNw2TwCorRayCU Ds6RZgxZ2D4pSkA4wdrcvAA5j09gVqghQPB+IAf83Tw2AuxlmZ9hYKAcBjtYagG9 cU5izANXOluqt12m/+enveu2qGAi3XeJyLJPHkQPYv0C3hql6136H+KpFYdfanPS s4lXkN5pDck9YabDJan0lCtsxz9EMZgyeZTbj5FJB7ed/sMIuiwuJiln07R6ZrqT i4TiIl2P/LrSpMaXJW9emvgcN/y4MeZijaggZaod2ISrr6VCIuVdJIPFGYoWLkhq pEiekQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41ax4mgarj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn4e6021042 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:04 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:40 -0700 Subject: [PATCH 19/21] drm/msm/dpu: Skip trigger flush and start for CWB Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-19-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=2215; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=EsK89cuQd4E/Olk9CLDiqKxnZJMyBEVg2nofQkF5Db4=; b=vf1u1k7QGkMcp4X/2ZSFaPDSoGEvv711r3qSuI77cuEA3X5IkALKfZnXKD9NZK5OtTDU/NVH4 XdAnr+Hill7Bs+2QN/xI4OwIyHa+F72sFU409z9BZwkcsTcouSmJHu+ X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0va5OZCIrb031jAv5k4UiguokciDdLPc X-Proofpoint-ORIG-GUID: 0va5OZCIrb031jAv5k4UiguokciDdLPc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 For concurrent writeback, the real time encoder is responsible for trigger flush and trigger start. Return early for trigger start and trigger flush for the concurrent writeback encoders. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 9d495a186eb8..47b5a5994234 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1493,6 +1493,7 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) { struct dpu_hw_ctl *ctl; + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); int pending_kickoff_cnt; u32 ret = UINT_MAX; @@ -1509,6 +1510,15 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); + /* Return early if encoder is writeback and in clone mode */ + if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL && + dpu_enc->cwb_mask) { + DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n", + DRMID(drm_enc)); + return; + } + + if (extra_flush_bits && ctl->ops.update_pending_flush) ctl->ops.update_pending_flush(ctl, extra_flush_bits); @@ -1531,6 +1541,8 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, */ static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) { + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys->parent); + if (!phys) { DPU_ERROR("invalid argument(s)\n"); return; @@ -1541,6 +1553,13 @@ static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) return; } + if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL && + dpu_enc->cwb_mask) { + DPU_DEBUG("encoder %d CWB enabled, skipping\n", + DRMID(phys->parent)); + return; + } + if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) phys->ops.trigger_start(phys); } From patchwork Thu Aug 29 20:48:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 824064 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09D731BB6A4; Thu, 29 Aug 2024 20:49:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; cv=none; b=YoTmc0pUl5sZJ2vLJmMU17Ui7TEwzFtSm4YuCRKz+U8yv8nF5L5hypC8ZLQSKZd4BIhJb9ePk7xdRDhkR932FmxaQchVLD1EcApqQgf8V7Wh8VvjSqDyHU6BaedDTOHq4B5oNmNmo/H3xt6ebNM0BCv//C9RPhVvgrh1kn8+93w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964562; c=relaxed/simple; bh=kc9ilhLKig4c8W84vSwwdKMW7sbavFZ1geGDgPxzzLc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tCsvoutSIvD27xjm/a9m4ZM23oduNcGvGrdAufSKDdSJGcW7qZmla6hRHsxFXgocS2HzfTPjFQdJ0MWv++FT4ikgJle/QH30ZdDdt3YAXsyMWCay8NBr9ANyvqc9rl699fCbCtgTk2WmSf9BRLXC21djoAcL2e/d3+u9XAws/VA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=U0FGEC+B; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="U0FGEC+B" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGd0Eo030353; Thu, 29 Aug 2024 20:49:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= fiRTKU3HBUesysXCPLeksdxnC+pkFe03YYBbXF/AbDE=; b=U0FGEC+BRpJ6Bbvh xOgZpKuDUQC8bKUeAljDW3MS/1dcTIeFdTliA9MWwGBgKhhP+j14901nu9qRWYfq rLp0PQHphvxTO+fRG/jJH+qIIQD700fshWoZh07uFdnTVjwX0ztI8Tz8UorUlZEd IafJ/fHXUHk/Y2090p/uiozIWX43MAzv5Q2/mwqQmTIGWdP4PRreEiD3VNVE7ixL qxVhXxSyKgvMJu3eKLIa9lgUeuipEw/At+5Yanp2r0FVG4A3YmY5PqO+bb6k/UMH 7X0jlY5x+743XpONmlaenTNtpEn+LWJGrG87wIvjBFaiJMB+p8I6zhS2gOqWh8Wu OWPwrg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419puuehx8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:05 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn42H003484 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:04 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:41 -0700 Subject: [PATCH 20/21] drm/msm/dpu: Reorder encoder kickoff for CWB Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-20-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=4105; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=kc9ilhLKig4c8W84vSwwdKMW7sbavFZ1geGDgPxzzLc=; b=zdk/fKu4UB+fzzNT6YmVkSQZIBSX+6Pv3hd9EM3NTJfsj2ovtzdzAX98vriC56kpJJRAt/aFw Z7BktN1SOt2D6YiI+7z9AAhpES1VDRrNXH/dtZOzkbv2Q1+Waz8VfN1 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2xbuLdlb6U_aD80XW9SR909H_eaI6-u0 X-Proofpoint-ORIG-GUID: 2xbuLdlb6U_aD80XW9SR909H_eaI6-u0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Add a helper that will handle the correct order of the encoder kickoffs for concurrent writeback. For concurrent writeback, the realtime encoder must always kickoff last as it will call the trigger flush and start. This avoids the following scenario where the writeback encoder increments the pending kickoff count after the WB_DONE interrupt is fired: If the realtime encoder is kicked off first, the encoder kickoff will flush/start the encoder and increment the pending kickoff count. The WB_DONE interrupt then fires (before the writeback encoder is kicked off). When the writeback encoder enters its kickoff, it will skip the flush/start (due to CWB being enabled) and hit a frame done timeout as the frame was kicked off (and the WB_DONE interrupt fired) without the pending kickoff count being incremented. In addition, the writeback timer should only start after the realtime encoder is kicked off to ensure that we don't get timeouts when the system has a heavy load (ex. when debug logs are enabled) Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 67 ++++++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index daf5f751f584..d2f91e89eba7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -928,6 +928,42 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) return rc; } +static int dpu_crtc_kickoff_clone_mode(struct drm_crtc *crtc) +{ + struct drm_encoder *encoder; + struct drm_encoder *rt_encoder = NULL, *wb_encoder; + + /* Find encoder for real time display */ + drm_for_each_encoder_mask(encoder, crtc->dev, + crtc->state->encoder_mask) { + if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) + wb_encoder = encoder; + else + rt_encoder = encoder; + } + + if (!rt_encoder || !wb_encoder) { + DRM_DEBUG_ATOMIC("real time or wb encoder not found\n"); + return -EINVAL; + } + + dpu_encoder_prepare_for_kickoff(wb_encoder); + dpu_encoder_prepare_for_kickoff(rt_encoder); + + /* + * Kickoff real time encoder last as it's the encoder that + * will do the flush + */ + dpu_encoder_kickoff(wb_encoder); + dpu_encoder_kickoff(rt_encoder); + + /* Don't start frame done timers until the kickoffs have finished */ + dpu_encoder_start_frame_done_timer(wb_encoder); + dpu_encoder_start_frame_done_timer(rt_encoder); + + return 0; +} + void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) { struct drm_encoder *encoder; @@ -952,13 +988,25 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) goto end; } } - /* - * Encoder will flush/start now, unless it has a tx pending. If so, it - * may delay and flush at an irq event (e.g. ppdone) - */ - drm_for_each_encoder_mask(encoder, crtc->dev, - crtc->state->encoder_mask) - dpu_encoder_prepare_for_kickoff(encoder); + + if (drm_crtc_in_clone_mode(crtc->state)) { + if (dpu_crtc_kickoff_clone_mode(crtc)) + goto end; + } else { + /* + * Encoder will flush/start now, unless it has a tx pending. + * If so, it may delay and flush at an irq event (e.g. ppdone) + */ + drm_for_each_encoder_mask(encoder, crtc->dev, + crtc->state->encoder_mask) + dpu_encoder_prepare_for_kickoff(encoder); + + drm_for_each_encoder_mask(encoder, crtc->dev, + crtc->state->encoder_mask) { + dpu_encoder_kickoff(encoder); + dpu_encoder_start_frame_done_timer(encoder); + } + } if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { /* acquire bandwidth and other resources */ @@ -970,11 +1018,6 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) dpu_vbif_clear_errors(dpu_kms); - drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { - dpu_encoder_kickoff(encoder); - dpu_encoder_start_frame_done_timer(encoder); - } - reinit_completion(&dpu_crtc->frame_done_comp); end: From patchwork Thu Aug 29 20:48:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 823581 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 277611BAEF1; Thu, 29 Aug 2024 20:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; cv=none; b=dkqYSza+OeAZVKI0Eo5KhgdxJ1g7ooRejZAktDXtWoMJKmH1SyfMfpdBg9PyFjsQc9lvNCAFvnoCz7RYip7ftHo8Rrdy6gfPinpNLWdxDHGJ05nXdTgRfu7lnoPyextDYrhhHjKXxmgCizFl7FXpJ6s7lLXbGqT5yArTRzNlOE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724964561; c=relaxed/simple; bh=Zkfb0x1UhHELZyP7wkQbLW0HhqrMn1zVAR+JC51dopI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tZWF8Z3meir/XKT2TBvdUMfwHkA+xWScndJ/nMTCJ0VmNJSx2uK+RliIdVm29NiXKOq+0UuDvhQ0er2KdsYss3NTopuef2niZjNlduEWIzZjMMY75r96MnAwO1eWjQCBZth0BnW/mgxLcwZi0ednABVGVRE28DryuxL2i0nRZ8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=DszwjYma; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DszwjYma" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47TGePBg006365; Thu, 29 Aug 2024 20:49:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pLL17NErFn0beDKFMT994aik7V3gYXWvBuhXwiSVTHQ=; b=DszwjYmaXO8qPCQE Qyn3xEmDKx52rY0zkVdQuayDKhYPQDGRilwtNujHxVoNdjBhlYzEMjnRScswu3AM bKUavylYqUCqNwX4zSbqYQ6aohx6TvylU648viwGzFsUuw3t4sL3PyBDrMwQ5pKq LKB/5BIz3xgnaf0M+2FANDxD0oyv4PqL57WT/+htwUHIJjXLex9D1I/kwSAbNGnL PUJB/k5doBk29dZDIdg+aGC5wGT152HI2o/hNtJhMo2iDbwpt/b04RzwUh7Oom8q 0K0/HZRJWNS7naWVGLCLZg8M5HU1KioXf8wSsNxaNZ32k/9FJ/QRLDo+96+wupAJ 1KcAiw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 419putxpbu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:05 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47TKn4KQ021054 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 20:49:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 13:49:04 -0700 From: Jessica Zhang Date: Thu, 29 Aug 2024 13:48:42 -0700 Subject: [PATCH 21/21] drm/msm/dpu: Set possible clones for all encoders Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240829-concurrent-wb-v1-21-502b16ae2ebb@quicinc.com> References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> In-Reply-To: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1724964539; l=3416; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=Zkfb0x1UhHELZyP7wkQbLW0HhqrMn1zVAR+JC51dopI=; b=LKMEdAVhhzG5AzVK2wzQBejPgyRawIrGfiCXQVn4QZZOtA2zQGMjuBZv9BkUeInhh0SParZ79 07HPjlnfqf8DRjZnC21lcSeeZCLX9E3MzOI0G41XY9g+ZmNoy4IN0DB X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: eQwKgQ5f36EI-sTq3enKJDvMoVLglevw X-Proofpoint-GUID: eQwKgQ5f36EI-sTq3enKJDvMoVLglevw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290147 Set writeback encoders as possible clones for non-writeback encoders and vice versa. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 7 +++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +++++-- 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 47b5a5994234..aad659e6d35b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2352,6 +2352,33 @@ static int dpu_encoder_virt_add_phys_encs( return 0; } +uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc) +{ + struct drm_encoder *curr; + int type = drm_enc->encoder_type; + uint32_t clone_mask = drm_encoder_mask(drm_enc); + + /* + * Set writeback as possible clones of real-time encoders and real-time + * encoders as clones of writeback. + * + * Writeback encoders can't be clones of each other and real-time + * encoders can't be clones of each other. + */ + drm_for_each_encoder(curr, drm_enc->dev) { + if (type == DRM_MODE_ENCODER_VIRTUAL && + curr->encoder_type == DRM_MODE_ENCODER_VIRTUAL) + continue; + if (type != DRM_MODE_ENCODER_VIRTUAL && + curr->encoder_type != DRM_MODE_ENCODER_VIRTUAL) + continue; + + clone_mask |= drm_encoder_mask(curr); + } + + return clone_mask; +} + static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, struct msm_display_info *disp_info) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 7ab5f9380bf5..70eda127488a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -98,6 +98,13 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder); */ void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder); +/** + * dpu_encoder_get_clones - set possible_clones for DPU encoder + * @drm_enc: DRM encoder pointer + * Returns: possible_clones mask + */ +uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc); + /** * dpu_encoder_init - initialize virtual encoder object * @dev: Pointer to drm device structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 87526d3c224a..1a82aa61d217 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2013 Red Hat * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Author: Rob Clark */ @@ -793,8 +793,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) return ret; num_encoders = 0; - drm_for_each_encoder(encoder, dev) + drm_for_each_encoder(encoder, dev) { num_encoders++; + if (catalog->cwb_count > 0) + encoder->possible_clones = dpu_encoder_get_clones(encoder); + } max_crtc_count = min(catalog->mixer_count, num_encoders);