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Thu, 29 Aug 2024 22:15:58 +0000 Received: from NALASPPMTA02.qualcomm.com (NALASPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47TMFwSi024644; Thu, 29 Aug 2024 22:15:58 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-uchalich-lv.qualcomm.com [10.81.89.1]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTPS id 47TMFv1t024642 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 22:15:57 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4184210) id D6579639; Thu, 29 Aug 2024 15:15:57 -0700 (PDT) From: Unnathi Chalicheemala To: Bjorn Andersson , Konrad Dybcio Cc: Unnathi Chalicheemala , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com Subject: [PATCH v2 1/2] firmware: qcom_scm: Add API to get waitqueue IRQ info Date: Thu, 29 Aug 2024 15:15:54 -0700 Message-Id: <9acc746885d6b06c2333f0493413c44b85fa7f02.1724968351.git.quic_uchalich@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: lV10gWogBYpM0TzvNX0_SMQI13ZQVAxa X-Proofpoint-GUID: lV10gWogBYpM0TzvNX0_SMQI13ZQVAxa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290158 Bootloader and firmware for SM8650 and older chipsets expect node name as "qcom_scm". However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware irq number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware irq number is converted to a linux irq number using newly defined fill_irq_fwspec_params(). This linux irq number is then supplied to the threaded_irq call. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 59 +++++++++++++++++++++++++++++++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 00c379a3cceb..ed51fbb1c065 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -32,6 +32,14 @@ #include "qcom_scm.h" #include "qcom_tzmem.h" +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 987 // 1019 - 32 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 1024 // 5120 - 4096 + +#define GIC_IRQ_TYPE_SPI 0 +#define GIC_IRQ_TYPE_ESPI 2 + static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); module_param(download_mode, bool, 0); @@ -1819,6 +1827,55 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 virq) +{ + if (WARN(virq < GIC_SPI_BASE, "Unexpected virq: %d\n", virq)) { + return -ENXIO; + } else if (virq <= (GIC_SPI_BASE + GIC_MAX_SPI)) { + fwspec->param_count = 3; + fwspec->param[0] = GIC_IRQ_TYPE_SPI; + fwspec->param[1] = virq - GIC_SPI_BASE; + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; + } else if (WARN(virq < GIC_ESPI_BASE, "Unexpected virq: %d\n", virq)) { + return -ENXIO; + } else if (virq < (GIC_ESPI_BASE + GIC_MAX_ESPI)) { + fwspec->param_count = 3; + fwspec->param[0] = GIC_IRQ_TYPE_ESPI; + fwspec->param[1] = virq - GIC_ESPI_BASE; + fwspec->param[2] = IRQ_TYPE_EDGE_RISING; + } else { + WARN(1, "Unexpected virq: %d\n", virq); + return -ENXIO; + } + return 0; +} + +static int qcom_scm_get_waitq_irq(void) +{ + int ret; + u32 hwirq; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_WAITQ, + .cmd = QCOM_SCM_WAITQ_GET_INFO, + .owner = ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + struct irq_fwspec fwspec; + + ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + + fwspec.fwnode = of_node_to_fwnode(__scm->dev->of_node); + hwirq = res.result[1] & 0xffff; + ret = qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + ret = irq_create_fwspec_mapping(&fwspec); + + return ret; +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -1936,7 +1993,7 @@ static int qcom_scm_probe(struct platform_device *pdev) /* Let all above stores be available after this */ smp_store_release(&__scm, scm); - irq = platform_get_irq_optional(pdev, 0); + irq = qcom_scm_get_waitq_irq(); if (irq < 0) { if (irq != -ENXIO) return irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 685b8f59e7a6..ab0f88f5f777 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -143,6 +143,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 From patchwork Thu Aug 29 22:15:55 2024 Content-Type: text/plain; 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Thu, 29 Aug 2024 22:15:58 +0000 Received: from NALASPPMTA01.qualcomm.com (NALASPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47TMFwZX019815; Thu, 29 Aug 2024 22:15:58 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-uchalich-lv.qualcomm.com [10.81.89.1]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 47TMFwNh019814 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 22:15:58 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4184210) id 6AE79639; Thu, 29 Aug 2024 15:15:58 -0700 (PDT) From: Unnathi Chalicheemala To: Bjorn Andersson , Konrad Dybcio Cc: Unnathi Chalicheemala , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com Subject: [PATCH v2 2/2] firmware: qcom_scm: Support multiple waitq contexts Date: Thu, 29 Aug 2024 15:15:55 -0700 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: U8-6b9goVcWdrSS0y890Oh0dgzmejkmI X-Proofpoint-GUID: U8-6b9goVcWdrSS0y890Oh0dgzmejkmI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290158 Currently, only a single waitqueue context exists, with waitqueue id zero. Multi-waitqueue mechanism is added in firmware to support the case when multiple VMs make SMC calls or single VM making multiple calls on same CPU. When VMs make SMC call, firmware will allocate waitqueue context assuming the SMC call to be a blocking call. SMC calls that cannot acquire resources are returned to sleep in the calling VM. When resource is available, VM will be notified to wake sleeping thread and resume SMC call. SM8650 firmware can allocate two such waitq contexts so create these two waitqueue contexts. Unique waitqueue contexts are supported by a dynamically sized array where each unique wq_ctx is associated with a struct completion variable for easy lookup. To get the number of waitqueue contexts directly from firmware, qcom_scm_query_waitq_cnt() is introduced. On older targets which support only a single waitqueue, wq_cnt is set to 1 as SCM call for query_waitq_cnt() is not implemented for single waitqueue case. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 82 +++++++++++++++++++++++--------- 1 file changed, 60 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index ed51fbb1c065..b2c5505de681 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -44,12 +44,13 @@ static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); module_param(download_mode, bool, 0); struct qcom_scm { + int wq_cnt; struct device *dev; struct clk *core_clk; struct clk *iface_clk; struct clk *bus_clk; struct icc_path *path; - struct completion waitq_comp; + struct completion *waitq; struct reset_controller_dev reset; /* control access to the interconnect path */ @@ -1850,6 +1851,31 @@ static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 virq) return 0; } +static int qcom_scm_query_waitq_count(void) +{ + bool avail; + int count; + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_WAITQ, + .cmd = QCOM_SCM_WAITQ_GET_INFO, + .owner = ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + + avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_INFO); + if (!avail) { + count = 1; + return count; + } + + ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + count = res.result[0] & 0xff; + return count; +} + static int qcom_scm_get_waitq_irq(void) { int ret; @@ -1876,42 +1902,40 @@ static int qcom_scm_get_waitq_irq(void) return ret; } -static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) +static struct completion *qcom_scm_get_completion(u32 wq_ctx) { - /* FW currently only supports a single wq_ctx (zero). - * TODO: Update this logic to include dynamic allocation and lookup of - * completion structs when FW supports more wq_ctx values. - */ - if (wq_ctx != 0) { - dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); - return -EINVAL; - } + struct completion *wq; - return 0; + if (wq_ctx >= __scm->wq_cnt) + return ERR_PTR(-EINVAL); + + wq = &__scm->waitq[wq_ctx]; + + return wq; } int qcom_scm_wait_for_wq_completion(u32 wq_ctx) { - int ret; + struct completion *wq; - ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq = qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); - wait_for_completion(&__scm->waitq_comp); + wait_for_completion(wq); return 0; } static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { - int ret; + struct completion *wq; - ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq = qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); - complete(&__scm->waitq_comp); + complete(wq); return 0; } @@ -1948,6 +1972,7 @@ static int qcom_scm_probe(struct platform_device *pdev) struct qcom_tzmem_pool_config pool_config; struct qcom_scm *scm; int irq, ret; + int i; scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); if (!scm) @@ -1958,7 +1983,6 @@ static int qcom_scm_probe(struct platform_device *pdev) if (ret < 0) return ret; - init_completion(&scm->waitq_comp); mutex_init(&scm->scm_bw_lock); scm->path = devm_of_icc_get(&pdev->dev, NULL); @@ -1993,6 +2017,20 @@ static int qcom_scm_probe(struct platform_device *pdev) /* Let all above stores be available after this */ smp_store_release(&__scm, scm); + platform_set_drvdata(pdev, scm); + ret = qcom_scm_query_waitq_count(); + if (ret < 0) + return ret; + + scm->wq_cnt = ret; + + scm->waitq = devm_kcalloc(&pdev->dev, scm->wq_cnt, sizeof(*scm->waitq), GFP_KERNEL); + if (!scm->waitq) + return -ENOMEM; + + for (i = 0; i < scm->wq_cnt; i++) + init_completion(&scm->waitq[i]); + irq = qcom_scm_get_waitq_irq(); if (irq < 0) { if (irq != -ENXIO)