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Signed-off-by: Nikunj Kela --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 8332f8d82f96..16f00ecdcc09 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -257,6 +257,7 @@ #define QCOM_ID_QRB2210 524 #define QCOM_ID_SM8475 530 #define QCOM_ID_SM8475P 531 +#define QCOM_ID_SA8255P 532 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_SM8475_2 540 From patchwork Wed Aug 28 20:37:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824465 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5647F1AC889; Wed, 28 Aug 2024 20:38:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nikunj Kela --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 24c3971f2ef1..5c3bd59eaa69 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -424,6 +424,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRB2210) }, { qcom_board_id(SM8475) }, { qcom_board_id(SM8475P) }, + { qcom_board_id(SA8255P) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, { qcom_board_id(SM8475_2) }, From patchwork Wed Aug 28 20:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824466 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24B681B0129; Wed, 28 Aug 2024 20:38:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nikunj Kela --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c0529486810f..d8d12ad073ba 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -50,6 +50,7 @@ description: | qrb4210 qru1000 sa8155p + sa8255p sa8540p sa8775p sc7180 @@ -900,6 +901,11 @@ properties: - qcom,sa8155p-adp - const: qcom,sa8155p + - items: + - enum: + - qcom,sa8255p-ride + - const: qcom,sa8255p + - items: - enum: - qcom,sa8295p-adp From patchwork Wed Aug 28 20:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823228 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3CBA1AED3A; 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Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 2cc83771d8e7..65057f5c8972 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -43,6 +43,7 @@ properties: - qcom,scm-msm8998 - qcom,scm-qcm2290 - qcom,scm-qdu1000 + - qcom,scm-sa8255p - qcom,scm-sa8775p - qcom,scm-sc7180 - qcom,scm-sc7280 @@ -204,6 +205,7 @@ allOf: compatible: contains: enum: + - qcom,scm-sa8255p - qcom,scm-sa8775p then: properties: From patchwork Wed Aug 28 20:37:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823229 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 497611B1415; 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Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index 05e4e1d51713..bc108b8db9f4 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - qcom,qdu1000-ipcc + - qcom,sa8255p-ipcc - qcom,sa8775p-ipcc - qcom,sc7280-ipcc - qcom,sc8280xp-ipcc From patchwork Wed Aug 28 20:37:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824470 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 853CE1AC8B2; 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Signed-off-by: Nikunj Kela --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 47587971fb0b..932393f8c649 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -26,6 +26,7 @@ properties: - qcom,apss-wdt-msm8994 - qcom,apss-wdt-qcm2290 - qcom,apss-wdt-qcs404 + - qcom,apss-wdt-sa8255p - qcom,apss-wdt-sa8775p - qcom,apss-wdt-sc7180 - qcom,apss-wdt-sc7280 From patchwork Wed Aug 28 20:37:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824464 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4994F1B1416; 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Signed-off-by: Nikunj Kela --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 89c88004b41b..048b769a73c0 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -17,6 +17,7 @@ properties: - qcom,prng-ee # 8996 and later using EE - items: - enum: + - qcom,sa8255p-trng - qcom,sa8775p-trng - qcom,sc7280-trng - qcom,sm8450-trng From patchwork Wed Aug 28 20:37:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823235 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36B3C1AC8AF; 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Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 985fa10abb99..b1ea08a41bb0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -27,6 +27,7 @@ properties: items: - enum: - qcom,qdu1000-pdc + - qcom,sa8255p-pdc - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc From patchwork Wed Aug 28 20:37:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823234 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E80D1AD3F6; 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Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index 7afdb60edb22..bd873e7e4ae5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -26,6 +26,7 @@ properties: items: - enum: - qcom,qdu1000-aoss-qmp + - qcom,sa8255p-aoss-qmp - qcom,sa8775p-aoss-qmp - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp From patchwork Wed Aug 28 20:37:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824461 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21311B78E9; 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Wed, 28 Aug 2024 20:38:08 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47SKc7Hh025856 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Aug 2024 20:38:07 GMT Received: from hu-nkela-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 28 Aug 2024 13:38:03 -0700 From: Nikunj Kela To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Nikunj Kela Subject: [PATCH 10/22] dt-bindings: pinctrl: document support for SA8255p Date: Wed, 28 Aug 2024 13:37:09 -0700 Message-ID: <20240828203721.2751904-11-quic_nkela@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828203721.2751904-1-quic_nkela@quicinc.com> References: <20240828203721.2751904-1-quic_nkela@quicinc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pJXZs3ggEU0Rq8p2NWHSt2-rJSrrnBBS X-Proofpoint-GUID: pJXZs3ggEU0Rq8p2NWHSt2-rJSrrnBBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-28_08,2024-08-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408280149 Add compatible for pincontrol representing support on SA8255p. SA8255p uses the same TLMM block as SA8775p however the ownership of pins are split between Firmware VM and Linux VM on SA8255p. For example, pins used by UART are owned and configured by Firmware VM while pins used by ethernet are owned and configured by Linux VM. Therefore, adding a sa8255p specific compatible to mark the difference. Signed-off-by: Nikunj Kela --- .../devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml index e9abbf2c0689..0d712153f9d7 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -17,7 +17,9 @@ allOf: properties: compatible: - const: qcom,sa8775p-tlmm + enum: + - qcom,sa8255p-tlmm + - qcom,sa8775p-tlmm reg: maxItems: 1 From patchwork Wed Aug 28 20:37:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823233 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0E9F1AD9C2; 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Signed-off-by: Nikunj Kela --- drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 5459c0c681a2..9a48abdf9b71 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -1519,6 +1519,7 @@ static int sa8775p_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id sa8775p_pinctrl_of_match[] = { + { .compatible = "qcom,sa8255p-tlmm", }, { .compatible = "qcom,sa8775p-tlmm", }, { }, }; From patchwork Wed Aug 28 20:37:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824469 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C521AD41A; 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Signed-off-by: Nikunj Kela --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 1e9797f96410..71f6168f6d48 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -34,6 +34,7 @@ properties: items: - enum: - qcom,qdu1000-cpufreq-epss + - qcom,sa8255p-cpufreq-epss - qcom,sa8775p-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sc8280xp-cpufreq-epss From patchwork Wed Aug 28 20:37:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823232 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 957031AE842; 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Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 72048c5a0412..d45690d6a465 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -51,6 +51,7 @@ properties: - qcom,msm8996-tsens - qcom,msm8998-tsens - qcom,qcm2290-tsens + - qcom,sa8255p-tsens - qcom,sa8775p-tsens - qcom,sc7180-tsens - qcom,sc7280-tsens From patchwork Wed Aug 28 20:37:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824468 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD9261AD9FD; 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Signed-off-by: Nikunj Kela --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 280b4e49f219..3353c2d37841 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -37,6 +37,7 @@ properties: - enum: - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 + - qcom,sa8255p-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc7280-smmu-500 @@ -84,6 +85,7 @@ properties: items: - enum: - qcom,qcm2290-smmu-500 + - qcom,sa8255p-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 @@ -553,6 +555,7 @@ allOf: - marvell,ap806-smmu-500 - nvidia,smmu-500 - qcom,qdu1000-smmu-500 + - qcom,sa8255p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sdm670-smmu-500 - qcom,sdm845-smmu-500 From patchwork Wed Aug 28 20:37:14 2024 Content-Type: text/plain; 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Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index c6bd14ec5aa0..88f804bd7581 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -21,6 +21,7 @@ properties: - qcom,msm8998-tcsr - qcom,qcm2290-tcsr - qcom,qcs404-tcsr + - qcom,sa8255p-tcsr - qcom,sc7180-tcsr - qcom,sc7280-tcsr - qcom,sc8280xp-tcsr From patchwork Wed Aug 28 20:37:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 823231 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 937E41AC8A4; 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Clocks are being managed by the firmware VM and not required on SA8255p Linux VM hence removing it from required list. CC: Praveen Talari Signed-off-by: Nikunj Kela --- .../bindings/soc/qcom/qcom,geni-se.yaml | 47 +++++++++++++++++-- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 7b031ef09669..40e3a3e045da 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -22,17 +22,16 @@ properties: enum: - qcom,geni-se-qup - qcom,geni-se-i2c-master-hub + - qcom,sa8255p-geni-se-qup reg: description: QUP wrapper common register address and length. maxItems: 1 clock-names: - minItems: 1 maxItems: 2 clocks: - minItems: 1 maxItems: 2 "#address-cells": @@ -57,8 +56,6 @@ properties: required: - compatible - reg - - clock-names - - clocks - "#address-cells" - "#size-cells" - ranges @@ -83,6 +80,17 @@ patternProperties: $ref: /schemas/serial/qcom,serial-geni-qcom.yaml# allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sa8255p-geni-se-qup + then: + required: + - clocks + - clock-names + - if: properties: compatible: @@ -162,4 +170,35 @@ examples: }; }; + - | + + soc { + #address-cells = <2>; + #size-cells = <2>; + + geniqup@9c0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0 0x9c0000 0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c1: i2c@984000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0 0x984000 0 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi9_pd 1>; + }; + + uart4: serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0 0x990000 0 0x4000>; + interrupts = ; + power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>; + power-domain-names = "power", "perf"; + }; + }; + }; ... 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Clocks and interconnects are being configured in the firmware VM on SA8255p platform, therefore making them optional. CC: Praveen Talari Signed-off-by: Nikunj Kela --- .../serial/qcom,serial-geni-qcom.yaml | 58 ++++++++++++++++--- 1 file changed, 51 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml index dd33794b3534..dcd43e1353ec 100644 --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml @@ -13,11 +13,42 @@ maintainers: allOf: - $ref: /schemas/serial/serial.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + then: + required: + - power-domains + - power-domain-names + properties: + power-domains: + minItems: 2 + maxItems: 2 + else: + required: + - clocks + - clock-names + properties: + power-domains: + maxItems: 1 + interconnects: + maxItems: 2 + interconnect-names: + items: + - const: qup-core + - const: qup-config + properties: compatible: enum: - qcom,geni-uart - qcom,geni-debug-uart + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart clocks: maxItems: 1 @@ -26,12 +57,10 @@ properties: const: se interconnects: - maxItems: 2 + description: phandles of interconnect bw provider interconnect-names: - items: - - const: qup-core - - const: qup-config + description: names of interconnects interrupts: minItems: 1 @@ -51,15 +80,19 @@ properties: - const: sleep power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf reg: maxItems: 1 required: - compatible - - clocks - - clock-names - interrupts - reg @@ -83,4 +116,15 @@ examples: <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; }; + + - | + #include + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x990000 0x4000>; + interrupts = ; + power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>; + power-domain-names = "power", "perf"; + }; ... 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Clocks and interconnects are being configured in firmware VM on SA8255p platform, therefore making them optional. CC: Praveen Talari Signed-off-by: Nikunj Kela --- .../bindings/spi/qcom,spi-geni-qcom.yaml | 64 +++++++++++++++---- 1 file changed, 53 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..74ea7c4f2451 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -25,10 +25,41 @@ description: allOf: - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: qcom,sa8255p-geni-spi + then: + required: + - power-domains + - power-domain-names + properties: + power-domains: + minItems: 2 + maxItems: 2 + else: + required: + - clocks + - clock-names + properties: + power-domains: + maxItems: 1 + interconnects: + minItems: 2 + maxItems: 3 + interconnect-names: + minItems: 2 + items: + - const: qup-core + - const: qup-config + - const: qup-memory properties: compatible: - const: qcom,geni-spi + enum: + - qcom,geni-spi + - qcom,sa8255p-geni-spi clocks: maxItems: 1 @@ -45,15 +76,10 @@ properties: - const: rx interconnects: - minItems: 2 - maxItems: 3 + description: phandles of interconnect bw provider interconnect-names: - minItems: 2 - items: - - const: qup-core - - const: qup-config - - const: qup-memory + description: names of interconnects interrupts: maxItems: 1 @@ -61,15 +87,18 @@ properties: operating-points-v2: true power-domains: - maxItems: 1 + $ref: "/schemas/power/power-domain.yaml#/properties/power-domains" + + power-domain-names: + items: + - const: power + - const: perf reg: maxItems: 1 required: - compatible - - clocks - - clock-names - interrupts - reg @@ -116,3 +145,16 @@ examples: #address-cells = <1>; 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Clocks and interconnects are being configured in Firmware VM on SA8255p, therefore making them optional. CC: Praveen Talari Signed-off-by: Nikunj Kela --- .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 56 ++++++++++++------- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 9f66a3bb1f80..88f513fc5b08 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -15,14 +15,13 @@ properties: enum: - qcom,geni-i2c - qcom,geni-i2c-master-hub + - qcom,sa8255p-geni-i2c clocks: - minItems: 1 - maxItems: 2 + description: phandles for the clock providers clock-names: - minItems: 1 - maxItems: 2 + description: names for the clocks clock-frequency: default: 100000 @@ -36,12 +35,13 @@ properties: - const: rx interconnects: - minItems: 2 - maxItems: 3 + description: phandles of interconnect bw provider interconnect-names: - minItems: 2 - maxItems: 3 + items: + - const: qup-core + - const: qup-config + - const: qup-memory interrupts: maxItems: 1 @@ -69,8 +69,6 @@ properties: required: - compatible - interrupts - - clocks - - clock-names - reg allOf: @@ -100,22 +98,28 @@ allOf: items: - const: qup-core - const: qup-config + - if: + properties: + compatible: + contains: + const: qcom,sa8255p-geni-i2c + then: + required: + - power-domains else: properties: clocks: - maxItems: 1 - + minItems: 1 + maxItems: 2 clock-names: - const: se - + minItems: 1 + maxItems: 2 interconnects: - minItems: 3 - + minItems: 2 + maxItems: 3 interconnect-names: - items: - - const: qup-core - - const: qup-config - - const: qup-memory + minItems: 2 + maxItems: 3 unevaluatedProperties: false @@ -143,4 +147,16 @@ examples: power-domains = <&rpmhpd SC7180_CX>; required-opps = <&rpmhpd_opp_low_svs>; }; + + - | + #include + + i2c@a90000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi9_pd 11>; + }; ... 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Signed-off-by: Nikunj Kela --- Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 211f5254adf2..a168be6dd30c 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -24,7 +24,7 @@ description: | properties: $nodename: - const: scmi + pattern: '^scmi\.*' compatible: oneOf: From patchwork Wed Aug 28 20:37:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj Kela X-Patchwork-Id: 824462 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43E0C1B29D3; Wed, 28 Aug 2024 20:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells. Signed-off-by: Nikunj Kela --- include/dt-bindings/interrupt-controller/arm-gic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index 35b6f69b7db6..9c06248446b7 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -12,6 +12,7 @@ #define GIC_SPI 0 #define GIC_PPI 1 +#define GIC_ESPI 2 /* * Interrupt specifier cell 2. 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This platform abstracts resources such as clocks, regulators etc. in the firmware VM. The device drivers request resources operations over SCMI using power, performance, reset and sensor protocols. Multiple virtual SCMI instances are being employed for greater parallelism. These instances are tied to devices such that devices can have dedicated SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and can process requests from agents in parallel. Qualcomm smc transport is used for communication between SCMI agent and platform. Let's add the reduced functional support for SA8255p Ride board. Subsequently, the support for PCIe, USB, UFS, Ethernet will be added. Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 149 ++ arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2312 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2405 +++++++++++++++++++ 5 files changed, 4947 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 197ab325c0b9..a4ae24e55c48 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8255p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi new file mode 100644 index 000000000000..fb268d13b997 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + thermal-zones { + pmm8654au_0_thermal: pm8255-0-thermal { + polling-delay-passive = <100>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8255-1-thermal { + polling-delay-passive = <100>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8255-2-thermal { + polling-delay-passive = <100>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8255-3-thermal { + polling-delay-passive = <100>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts new file mode 100644 index 000000000000..1dc03051ad92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include + +#include "sa8255p.dtsi" +#include "sa8255p-pmics.dtsi" +#include "sa8255p-scmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8255P Ride"; + compatible = "qcom,sa8255p-ride", "qcom,sa8255p"; + + aliases { + i2c11 = &i2c11; + i2c18 = &i2c18; + serial0 = &uart10; + serial1 = &uart4; + spi16 = &spi16; + scmichannels = &scmichannels; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adreno_smmu { + power-domains = <&scmi15_pd 0>; + + status = "okay"; +}; + +&gpll0_board_clk { + clock-frequency = <300000000>; +}; + +&i2c11 { + clock-frequency = <400000>; + power-domains = <&scmi9_pd 11>; + + status = "okay"; +}; + +&i2c18 { + clock-frequency = <400000>; + power-domains = <&scmi9_pd 18>; + + status = "okay"; +}; + +&pmm8654au_0_thermal { + thermal-sensors = <&scmi23_sensor 0>; +}; + +&pmm8654au_1_thermal { + thermal-sensors = <&scmi23_sensor 1>; +}; + +&pmm8654au_2_thermal { + thermal-sensors = <&scmi23_sensor 2>; +}; + +&pmm8654au_3_thermal { + thermal-sensors = <&scmi23_sensor 3>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&scmi9 { + status = "okay"; +}; + +&scmi10 { + status = "okay"; +}; + +&scmi11 { + status = "okay"; +}; + +&scmi15 { + status = "okay"; +}; + +&scmi23 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&spi16 { + power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>; + power-domain-names = "power", "perf"; + + status = "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; +}; + +&uart4 { + power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>; + power-domain-names = "power", "perf"; + + status = "okay"; +}; + +&uart10 { + power-domains = <&scmi11_pd 10>, <&scmi11_dvfs 10>; + power-domain-names = "power", "perf"; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi new file mode 100644 index 000000000000..1e2db91711c6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi @@ -0,0 +1,2312 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&firmware { + scmi0: scmi0 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem0>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi0_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi0_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi0_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi1 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem1>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi1_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi1_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi1_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi2: scmi2 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem2>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi2_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi2_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi2_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi3: scmi3 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem3>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi3_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi3_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi3_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi4: scmi4 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem4>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi4_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi4_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi4_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi5: scmi5 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem5>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi5_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi5_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi5_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi6: scmi6 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem6>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi6_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi6_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi6_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi7: scmi7 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem7>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi7_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi7_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi7_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi8: scmi8 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem8>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi8_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi8_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi8_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi9: scmi9 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem9>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi9_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi9_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi9_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi10: scmi10 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem10>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi10_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi10_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi10_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi11: scmi11 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem11>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi11_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi11_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi11_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi12: scmi12 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem12>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi12_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi12_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi12_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi13: scmi13 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem13>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi13_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi13_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi13_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi14: scmi14 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem14>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi14_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi14_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi14_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi15: scmi15 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem15>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi15_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi15_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi15_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi16: scmi16 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem16>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi16_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi16_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi16_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi17: scmi17 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem17>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi17_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi17_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi17_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi18: scmi18 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem18>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi18_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi18_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi18_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi19: scmi19 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem19>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi19_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi19_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi19_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi20: scmi20 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem20>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi20_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi20_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi20_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi21: scmi21 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem21>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi21_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi21_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi21_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi22: scmi22 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem22>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi22_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi22_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi22_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi23: scmi23 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem23>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi23_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + + scmi24: scmi24 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem24>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi24_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi24_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi24_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi25: scmi25 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem25>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi25_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi25_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi25_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi26: scmi26 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem26>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi26_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi26_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi26_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi27: scmi27 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem27>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi27_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi27_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi27_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi28: scmi28 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem28>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi28_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi28_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi28_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi29: scmi29 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem29>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi29_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi29_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi29_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi30: scmi30 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem30>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi30_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi30_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi30_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi31: scmi31 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem31>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi31_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi31_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi31_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi32: scmi32 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem32>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi32_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi32_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi32_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi33: scmi33 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem33>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi33_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi33_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi33_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi34: scmi34 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem34>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi34_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi34_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi34_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi35: scmi35 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem35>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi35_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi35_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi35_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi36: scmi36 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem36>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi36_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi36_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi36_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi37: scmi37 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem37>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi37_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi37_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi37_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi38: scmi38 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem38>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi38_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi38_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi38_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi39: scmi39 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem39>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi39_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi39_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi39_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi40: scmi40 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem40>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi40_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi40_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi40_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi41: scmi41 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem41>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi41_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi41_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi41_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi42: scmi42 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem42>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi42_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi42_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi42_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi43: scmi43 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem43>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi43_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi43_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi43_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi44: scmi44 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem44>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi44_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi44_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi44_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi45: scmi45 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem45>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi45_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi45_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi45_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi46: scmi46 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem46>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi46_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi46_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi46_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi47: scmi47 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem47>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi47_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi47_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi47_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi48: scmi48 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem48>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi48_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi48_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi48_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi49: scmi49 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem49>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi49_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi49_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi49_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi50: scmi50 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem50>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi50_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi50_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi50_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi51: scmi51 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem51>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi51_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi51_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi51_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi52: scmi52 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem52>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi52_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi52_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi52_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi53: scmi53 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem53>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi53_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi53_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi53_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi54: scmi54 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem54>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi54_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi54_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi54_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi55: scmi55 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem55>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi55_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi55_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi55_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi56: scmi56 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem56>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi56_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi56_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi56_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi57: scmi57 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem57>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi57_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi57_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi57_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi58: scmi58 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem58>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi58_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi58_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi58_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi59: scmi59 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem59>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi59_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi59_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi59_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi60: scmi60 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem60>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi60_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi60_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi60_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi61: scmi61 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem61>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi61_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi61_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi61_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi62: scmi62 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem62>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi62_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi62_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi62_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi63: scmi63 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem63>; + + interrupts = ; + interrupt-names = "a2p"; + + max-rx-timeout-ms = <3000>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + scmi63_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi63_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi63_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; +}; + +&soc { + scmichannels: sram@d0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mmio-sram"; + reg = <0x0 0xd0000000 0x0 0x40000>; + ranges = <0x0 0x0 0x0 0xffffffff>; + + shmem0: scmi-sram@d0000000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0000000 0x1000>; + }; + + shmem1: scmi-sram@d0001000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0001000 0x1000>; + }; + + shmem2: scmi-sram@d0002000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0002000 0x1000>; + }; + + shmem3: scmi-sram@d0003000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0003000 0x1000>; + }; + + shmem4: scmi-sram@d0004000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0004000 0x1000>; + }; + + shmem5: scmi-sram@d0005000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0005000 0x1000>; + }; + + shmem6: scmi-sram@d0006000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0006000 0x1000>; + }; + + shmem7: scmi-sram@d0007000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0007000 0x1000>; + }; + + shmem8: scmi-sram@d0008000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0008000 0x1000>; + }; + + shmem9: scmi-sram@d0009000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0009000 0x1000>; + }; + + shmem10: scmi-sram@d000a000 { + compatible = "arm,scmi-shmem"; + reg = <0xd000a000 0x1000>; + }; + + shmem11: scmi-sram@d000b000 { + compatible = "arm,scmi-shmem"; + reg = <0xd000b000 0x1000>; + }; + + shmem12: scmi-sram@d000c000 { + compatible = "arm,scmi-shmem"; + reg = <0xd000c000 0x1000>; + }; + + shmem13: scmi-sram@d000d000 { + compatible = "arm,scmi-shmem"; + reg = <0xd000d000 0x1000>; + }; + + shmem14: scmi-sram@d000e000 { + compatible = "arm,scmi-shmem"; + reg = <0xd000e000 0x1000>; + }; + + shmem15: scmi-sram@d000f000 { + compatible = "arm,scmi-shmem"; + reg = <0xd000f000 0x1000>; + }; + + shmem16: scmi-sram@d0010000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0010000 0x1000>; + }; + + shmem17: scmi-sram@d0011000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0011000 0x1000>; + }; + + shmem18: scmi-sram@d0012000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0012000 0x1000>; + }; + + shmem19: scmi-sram@d0013000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0013000 0x1000>; + }; + + shmem20: scmi-sram@d0014000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0014000 0x1000>; + }; + + shmem21: scmi-sram@d0015000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0015000 0x1000>; + }; + + shmem22: scmi-sram@d0016000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0016000 0x1000>; + }; + + shmem23: scmi-sram@d0017000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0017000 0x1000>; + }; + + shmem24: scmi-sram@d0018000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0018000 0x1000>; + }; + + shmem25: scmi-sram@d0019000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0019000 0x1000>; + }; + + shmem26: scmi-sram@d001a000 { + compatible = "arm,scmi-shmem"; + reg = <0xd001a000 0x1000>; + }; + + shmem27: scmi-sram@d001b000 { + compatible = "arm,scmi-shmem"; + reg = <0xd001b000 0x1000>; + }; + + shmem28: scmi-sram@d001c000 { + compatible = "arm,scmi-shmem"; + reg = <0xd001c000 0x1000>; + }; + + shmem29: scmi-sram@d001d000 { + compatible = "arm,scmi-shmem"; + reg = <0xd001d000 0x1000>; + }; + + shmem30: scmi-sram@d001e000 { + compatible = "arm,scmi-shmem"; + reg = <0xd001e000 0x1000>; + }; + + shmem31: scmi-sram@d001f000 { + compatible = "arm,scmi-shmem"; + reg = <0xd001f000 0x1000>; + }; + + shmem32: scmi-sram@d0020000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0020000 0x1000>; + }; + + shmem33: scmi-sram@d0021000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0021000 0x1000>; + }; + + shmem34: scmi-sram@d0022000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0022000 0x1000>; + }; + + shmem35: scmi-sram@d0023000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0023000 0x1000>; + }; + + shmem36: scmi-sram@d0024000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0024000 0x1000>; + }; + + shmem37: scmi-sram@d0025000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0025000 0x1000>; + }; + + shmem38: scmi-sram@d0026000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0026000 0x1000>; + }; + + shmem39: scmi-sram@d0027000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0027000 0x1000>; + }; + + shmem40: scmi-sram@d0028000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0028000 0x1000>; + }; + + shmem41: scmi-sram@d0029000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0029000 0x1000>; + }; + + shmem42: scmi-sram@d002a000 { + compatible = "arm,scmi-shmem"; + reg = <0xd002a000 0x1000>; + }; + + shmem43: scmi-sram@d002b000 { + compatible = "arm,scmi-shmem"; + reg = <0xd002b000 0x1000>; + }; + + shmem44: scmi-sram@d002c000 { + compatible = "arm,scmi-shmem"; + reg = <0xd002c000 0x1000>; + }; + + shmem45: scmi-sram@d002d000 { + compatible = "arm,scmi-shmem"; + reg = <0xd002d000 0x1000>; + }; + + shmem46: scmi-sram@d002e000 { + compatible = "arm,scmi-shmem"; + reg = <0xd002e000 0x1000>; + }; + + shmem47: scmi-sram@d002f000 { + compatible = "arm,scmi-shmem"; + reg = <0xd002f000 0x1000>; + }; + + shmem48: scmi-sram@d0030000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0030000 0x1000>; + }; + + shmem49: scmi-sram@d0031000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0031000 0x1000>; + }; + + shmem50: scmi-sram@d0032000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0032000 0x1000>; + }; + + shmem51: scmi-sram@d0033000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0033000 0x1000>; + }; + + shmem52: scmi-sram@d0034000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0034000 0x1000>; + }; + + shmem53: scmi-sram@d0035000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0035000 0x1000>; + }; + + shmem54: scmi-sram@d0036000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0036000 0x1000>; + }; + + shmem55: scmi-sram@d0037000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0037000 0x1000>; + }; + + shmem56: scmi-sram@d0038000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0038000 0x1000>; + }; + + shmem57: scmi-sram@d0039000 { + compatible = "arm,scmi-shmem"; + reg = <0xd0039000 0x1000>; + }; + + shmem58: scmi-sram@d003a000 { + compatible = "arm,scmi-shmem"; + reg = <0xd003a000 0x1000>; + }; + + shmem59: scmi-sram@d003b000 { + compatible = "arm,scmi-shmem"; + reg = <0xd003b000 0x1000>; + }; + + shmem60: scmi-sram@d003c000 { + compatible = "arm,scmi-shmem"; + reg = <0xd003c000 0x1000>; + }; + + shmem61: scmi-sram@d003d000 { + compatible = "arm,scmi-shmem"; + reg = <0xd003d000 0x1000>; + }; + + shmem62: scmi-sram@d003e000 { + compatible = "arm,scmi-shmem"; + reg = <0xd003e000 0x1000>; + }; + + shmem63: scmi-sram@d003f000 { + compatible = "arm,scmi-shmem"; + reg = <0xd003f000 0x1000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qcom/sa8255p.dtsi new file mode 100644 index 000000000000..c354f76ffa5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi @@ -0,0 +1,2405 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + gpll0_board_clk: gpll0-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_board_clk>; + clock-mult = <1>; + clock-div = <2>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10000>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_1>; + L3_1: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + + }; + }; + + CPU5: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10100>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_1>; + }; + }; + + CPU6: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10200>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_1>; + }; + }; + + CPU7: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10300>; + enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware: firmware { + scm { + compatible = "qcom,scm-sa8255p", "qcom,scm"; + memory-region = <&tz_ffi_mem>; + qcom,dload-mode = <&tcsr 0x13000>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg = <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg = <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90600000 { + reg = <0x0 0x90600000 0x0 0x200000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg = <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg = <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + ddr_training_checksum: ddr-training-checksum@908c0000 { + reg = <0x0 0x908c0000 0x0 0x1000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg = <0x0 0x908f0000 0x0 0xe000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908fe000 { + reg = <0x0 0x908fe000 0x0 0x2000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible = "qcom,smem"; + reg = <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + + aoss_backup_mem: aoss-backup@91b00000 { + reg = <0x0 0x91b00000 0x0 0x40000>; + no-map; + }; + + cpucp_backup_mem: cpucp-backup@91b40000 { + reg = <0x0 0x91b40000 0x0 0x40000>; + no-map; + }; + + tz_config_backup_mem: tz-config-backup@91b80000 { + reg = <0x0 0x91b80000 0x0 0x10000>; + no-map; + }; + + ddr_training_data_mem: ddr-training-data@91b90000 { + reg = <0x0 0x91b90000 0x0 0x10000>; + no-map; + }; + + cdt_data_backup_mem: cdt-data-backup@91ba0000 { + reg = <0x0 0x91ba0000 0x0 0x1000>; + no-map; + }; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg = <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg = <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg = <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg = <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg = <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg = <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg = <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg = <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg = <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg = <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_mdf_mem: audio-mdf-region@ae000000 { + reg = <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg = <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg = <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + scmi_mem: scmi-region@d0000000 { + reg = <0x0 0xd0000000 0x0 0x40000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg = <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg = <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_reserved_mem: firmware-reserved@d0054000 { + reg = <0x0 0xd0054000 0x0 0x9c000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg = <0x0 0xd00f0000 0x0 0x10000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg = <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg = <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg = <0x0 0xd1800000 0x0 0x100000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg = <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg = <0x0 0xdb200000 0x0 0x100000>; + no-map; + }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + + ipcc0: mailbox@408000 { + compatible = "qcom,sa8255p-ipcc", "qcom,ipcc"; + reg = <0x0 0x00408000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc1: mailbox@488000 { + compatible = "qcom,sa8255p-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + status = "disabled"; + }; + + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + ranges; + iommus = <&apps_smmu 0x5a3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + i2c14: i2c@880000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart14: serial@880000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart15: serial@884000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x888000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi16: spi@888000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart16: serial@888000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c17: i2c@88c000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart17: serial@88c000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c18: i2c@890000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi18: spi@890000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart19: serial@894000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c20: i2c@898000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi20: spi@898000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart20: serial@898000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x403 0x0>; + status = "disabled"; + + i2c0: i2c@980000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart0: serial@980000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@984000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x984000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart2: serial@988000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x988000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart3: serial@98c000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x98c000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x990000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart5: serial@994000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x994000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; + + i2c7: i2c@a80000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi7: spi@a80000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart7: serial@a80000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c8: i2c@a84000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi8: spi@a84000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart8: serial@a84000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c9: i2c@a88000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi9: spi@a88000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart9: serial@a88000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0xa88000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi10: spi@a8c000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart10: serial@a8c000 { + compatible = "qcom,sa8255p-geni-debug-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c11: i2c@a90000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi11: spi@a90000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart11: serial@a90000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c12: i2c@a94000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi12: spi@a94000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart12: serial@a94000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + + i2c13: i2c@a98000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + }; + + qupv3_id_3: geniqup@bc0000 { + compatible = "qcom,sa8255p-geni-se-qup"; + reg = <0x0 0xbc0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x43 0x0>; + status = "disabled"; + + i2c21: i2c@b80000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + spi21: spi@b80000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + status = "disabled"; + }; + + uart21: serial@b80000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + status = "disabled"; + }; + }; + + rng: rng@10d2000 { + compatible = "qcom,sa8255p-trng", "qcom,trng"; + reg = <0x0 0x010d2000 0x0 0x1000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "qcom,sa8255p-tcsr", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sa8255p-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sa8255p-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens2: thermal-sensor@c251000 { + compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c251000 0x0 0x1ff>, + <0x0 0x0c224000 0x0 0x8>; + interrupts = , + ; + #qcom,sensors = <13>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c252000 { + compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c252000 0x0 0x1ff>, + <0x0 0x0c225000 0x0 0x8>; + interrupts = , + ; + #qcom,sensors = <13>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c263000 0x0 0x1ff>, + <0x0 0x0c222000 0x0 0x8>; + interrupts = , + ; + #qcom,sensors = <12>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c265000 0x0 0x1ff>, + <0x0 0x0c223000 0x0 0x8>; + interrupts = , + ; + #qcom,sensors = <12>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sa8255p-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + interrupts-extended = <&ipcc0 IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc0 IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells = <0>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8255p-tlmm"; + reg = <0x0 0x0f000000 0x0 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 149>; + wakeup-parent = <&pdc>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sa8255p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sa8255p", "qcom,kpss-wdt"; + reg = <0x0 0x17c10000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8255p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&bi_tcxo_div2>, <&gpll0_board_clk>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + }; + + thermal-zones { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + audio-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camss-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pcie-0-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camss-1-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pcie-1-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-0-2-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-1-2-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddrss-0-thermal { + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors = <&tsens2 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-0-2-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsp-1-2-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddrss-1-thermal { + thermal-sensors = <&tsens3 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors = <&tsens3 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};