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AJvYcCXR7RbABTBZ/FAoerJui94oQ8QAABhVgSP0Nozke+PqyPfB3ud6O8v09WaPW11etHeLjgvuzXDKaRCQmBwe@vger.kernel.org X-Gm-Message-State: AOJu0Yzj3wH4dgRhevQg+6zRtved6T7a7A2rAxRW2d6ZL3RQLXavY6cR bF9wXYg6z9VIDMVmYoRDb1B8PBleAlYDKLUQJgERtZ1MgMOfs7QcnEjXINPhLrE= X-Google-Smtp-Source: AGHT+IFjioJWqfHoLZSyZtpbC3hGCEXMM/p8fgRmV3Ro8hWJPu+jWJN6wQIPD2x7AwJXhGlaVxPS1g== X-Received: by 2002:a17:907:e2d8:b0:a86:80b7:471d with SMTP id a640c23a62f3a-a86a52de598mr403785866b.37.1724500743573; Sat, 24 Aug 2024 04:59:03 -0700 (PDT) Received: from sagittarius-a.ht.home ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f4f4a95sm390881166b.210.2024.08.24.04.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Aug 2024 04:59:03 -0700 (PDT) From: Bryan O'Donoghue To: mailingradian@gmail.com, vladimir.zapolskiy@linaro.org, loic.poulain@linaro.org, rfoss@kernel.org Cc: andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, todor.too@gmail.com, mchehab@kernel.org, andersson@kernel.org, konradybcio@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH] i2c: qcom-cci: Stop complaining about DT set clock rate Date: Sat, 24 Aug 2024 12:59:00 +0100 Message-ID: <20240824115900.40702-1-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 It is common practice in the downstream and upstream CCI dt to set CCI clock rates to 19.2 MHz. It appears to be fairly common for initial code to set the CCI clock rate to 37.5 MHz. Applying the widely used CCI clock rates from downstream ought not to cause warning messages in the upstream kernel where our general policy is to usually copy downstream hardware clock rates across the range of Qualcomm drivers. Drop the warning it is pervasive across CAMSS users but doesn't add any information or warrant any changes to the DT to align the DT clock rate to the bootloader clock rate. Signed-off-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy --- drivers/i2c/busses/i2c-qcom-cci.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 414882c57d7f4..99e4305a33733 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -602,14 +602,6 @@ static int cci_probe(struct platform_device *pdev) } } - if (cci_clk_rate != cci->data->cci_clk_rate) { - /* cci clock set by the bootloader or via assigned clock rate - * in DT. - */ - dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n", - cci_clk_rate, cci->data->cci_clk_rate); - } - ret = cci_enable_clocks(cci); if (ret < 0) return ret;