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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 01/11] i2c: riic: Use temporary variable for struct device Date: Tue, 20 Aug 2024 13:19:08 +0300 Message-Id: <20240820101918.2384635-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Use a temporary variable for the struct device pointers to avoid dereferencing. Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - collected tags Changes in v3: - dropped updates around &riic->adapter.dev introduced in v2; with this restored commit description from v1 Changes in v2: - updated commit description to reflect all the changes done drivers/i2c/busses/i2c-riic.c | 49 +++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index d6f585cdb7e5..bc33762a5d07 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -131,11 +131,12 @@ static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct riic_dev *riic = i2c_get_adapdata(adap); + struct device *dev = adap->dev.parent; unsigned long time_left; int i; u8 start_bit; - pm_runtime_get_sync(adap->dev.parent); + pm_runtime_get_sync(dev); if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) { riic->err = -EBUSY; @@ -168,7 +169,7 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) } out: - pm_runtime_put(adap->dev.parent); + pm_runtime_put(dev); return riic->err ?: num; } @@ -303,8 +304,9 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) int ret = 0; unsigned long rate; int total_ticks, cks, brl, brh; + struct device *dev = riic->adapter.dev.parent; - pm_runtime_get_sync(riic->adapter.dev.parent); + pm_runtime_get_sync(dev); if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { dev_err(&riic->adapter.dev, @@ -396,7 +398,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); out: - pm_runtime_put(riic->adapter.dev.parent); + pm_runtime_put(dev); return ret; } @@ -415,13 +417,14 @@ static void riic_reset_control_assert(void *data) static int riic_i2c_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct riic_dev *riic; struct i2c_adapter *adap; struct i2c_timings i2c_t; struct reset_control *rstc; int i, ret; - riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL); + riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); if (!riic) return -ENOMEM; @@ -429,22 +432,22 @@ static int riic_i2c_probe(struct platform_device *pdev) if (IS_ERR(riic->base)) return PTR_ERR(riic->base); - riic->clk = devm_clk_get(&pdev->dev, NULL); + riic->clk = devm_clk_get(dev, NULL); if (IS_ERR(riic->clk)) { - dev_err(&pdev->dev, "missing controller clock"); + dev_err(dev, "missing controller clock"); return PTR_ERR(riic->clk); } - rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + rstc = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(rstc)) - return dev_err_probe(&pdev->dev, PTR_ERR(rstc), + return dev_err_probe(dev, PTR_ERR(rstc), "Error: missing reset ctrl\n"); ret = reset_control_deassert(rstc); if (ret) return ret; - ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc); + ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc); if (ret) return ret; @@ -453,29 +456,29 @@ static int riic_i2c_probe(struct platform_device *pdev) if (ret < 0) return ret; - ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr, + ret = devm_request_irq(dev, ret, riic_irqs[i].isr, 0, riic_irqs[i].name, riic); if (ret) { - dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name); + dev_err(dev, "failed to request irq %s\n", riic_irqs[i].name); return ret; } } - riic->info = of_device_get_match_data(&pdev->dev); + riic->info = of_device_get_match_data(dev); adap = &riic->adapter; i2c_set_adapdata(adap, riic); strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); adap->owner = THIS_MODULE; adap->algo = &riic_algo; - adap->dev.parent = &pdev->dev; - adap->dev.of_node = pdev->dev.of_node; + adap->dev.parent = dev; + adap->dev.of_node = dev->of_node; init_completion(&riic->msg_done); - i2c_parse_fw_timings(&pdev->dev, &i2c_t, true); + i2c_parse_fw_timings(dev, &i2c_t, true); - pm_runtime_enable(&pdev->dev); + pm_runtime_enable(dev); ret = riic_init_hw(riic, &i2c_t); if (ret) @@ -487,24 +490,24 @@ static int riic_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, riic); - dev_info(&pdev->dev, "registered with %dHz bus speed\n", - i2c_t.bus_freq_hz); + dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz); return 0; out: - pm_runtime_disable(&pdev->dev); + pm_runtime_disable(dev); return ret; } static void riic_i2c_remove(struct platform_device *pdev) { struct riic_dev *riic = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; - pm_runtime_get_sync(&pdev->dev); + pm_runtime_get_sync(dev); riic_writeb(riic, 0, RIIC_ICIER); - pm_runtime_put(&pdev->dev); + pm_runtime_put(dev); i2c_del_adapter(&riic->adapter); - pm_runtime_disable(&pdev->dev); + pm_runtime_disable(dev); } static const struct riic_of_data riic_rz_a_info = { From patchwork Tue Aug 20 10:19:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 820757 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4B5D18D636 for ; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:31 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 02/11] i2c: riic: Call pm_runtime_get_sync() when need to access registers Date: Tue, 20 Aug 2024 13:19:09 +0300 Message-Id: <20240820101918.2384635-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea There is no need to runtime resume the device as long as the IP registers are not accessed. Calling pm_runtime_get_sync() at the register access time leads to a simpler error path. Reviewed-by: Andi Shyti Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - collected tags Changes in v3: - collected tags Changes in v2: - none drivers/i2c/busses/i2c-riic.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index bc33762a5d07..2e119024c2d7 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -301,19 +301,15 @@ static const struct i2c_algorithm riic_algo = { static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) { - int ret = 0; unsigned long rate; int total_ticks, cks, brl, brh; struct device *dev = riic->adapter.dev.parent; - pm_runtime_get_sync(dev); - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { dev_err(&riic->adapter.dev, "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); - ret = -EINVAL; - goto out; + return -EINVAL; } rate = clk_get_rate(riic->clk); @@ -351,8 +347,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) if (brl > (0x1F + 3)) { dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n", (unsigned long)t->bus_freq_hz); - ret = -EINVAL; - goto out; + return -EINVAL; } brh = total_ticks - brl; @@ -384,6 +379,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) t->scl_fall_ns / (1000000000 / rate), t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); + pm_runtime_get_sync(dev); + /* Changing the order of accessing IICRST and ICE may break things! */ riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); @@ -397,9 +394,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); -out: pm_runtime_put(dev); - return ret; + return 0; } static struct riic_irq_desc riic_irqs[] = { From patchwork Tue Aug 20 10:19:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 821891 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1373118DF9B for ; Tue, 20 Aug 2024 10:19:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149177; cv=none; b=lO3/ZY8UUmfOAYOy6ASxtfAVc33l0A76VnFteirnw9bZpsc7s4m6YlNKPPOUYHTvluJzQaxT9+5MDn0GEhuJyhlp+G79xWLaVhppBZ2IM+lBahWa7Xaz94F5M4RrPKjkqeED6U5IUiFGKmNALieORt/33zgHGJ0q0vxWZls1WUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149177; c=relaxed/simple; bh=cNNjQttiLgf1necaxo77Jw1cc9uDH5GA16TvXwtf6wk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cchjpYKqrmLKY8YPhILHObSXJsTwkUC3BlwOlrjI1kyThGq8lm/yF8w4eXktjmcK6JD8bLFs/AC0PBQ9tmRNKWhew129gLUw4uAAyhlUKrGlpAPk1Oy5tXTxRUiVblXwZ4GmCjYG3cx4gjRmGmWXj4tVaVywUwFQutNmgEdjhvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=lr9EK1Hs; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="lr9EK1Hs" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-52efd8807aaso6990800e87.3 for ; Tue, 20 Aug 2024 03:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724149174; x=1724753974; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NPXFJc6gcMMk+4vX3cXQqxjNWYT/VTeUT7RD3vBSt14=; b=lr9EK1Hs6ZMVTnM7apxUdDwm037Sb59KsILdYpDTeccmcRqjVwXjqYihN8x3bocwvC 6CRKvrIPKbVKcdFtmYcbq7FEWngi5zd2dYOWEvmrGNk2nSmfpiLfCWUjlC5ZvjkSyMNV 2ckofCeUc/w0aHKa/pFyqgpoYmoD4DzFsQQSeEfihGm4sqsxwpklyI1ErILfwrVwqS/V Hq3TkIaE0/222F5vwxP4T7ioxhrowYu6taZGGiBShGpn7355RUOfuNqmq7ZU81sOarNK /eXjCZ4uUlg4Oj5aaMjSWPF9kElQbNIfSIXWvdZk+isjewM9udaRTyovp3MlBnTYMkbf skwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724149174; x=1724753974; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NPXFJc6gcMMk+4vX3cXQqxjNWYT/VTeUT7RD3vBSt14=; b=KDaILRtaGJl396LzVj3K/blD6wikE0V97BU9YS0sXNhS9QaiqOK2HcPGENbNL/DElH Sdk2u58bN/xc+z3hKMLan6lt9Qhgr+uVOCTZmfDZc0pQwwJkeSBOGJun4QGqlaOBR2w+ 0TsVUxYDl+aKCfcJ600uyJsAMHX/KZ3Shu7oN7KdEZcp0rYjvBpL9WSWVKfvFwkJAuWO BiCe7nKTMATGeM/sKc69Oh+bR4//uKmVhBlBRu9vbXnWMMdED8dwgiVyzzDCAMtlpAaA ZwZiH6saVWwR+H4G8E0O4AWbIrbVeEgW/DShYOPQOKxXGrjCaHVYoDiPJWWApULHO9R5 kCWQ== X-Forwarded-Encrypted: i=1; AJvYcCXZ4TMr7TLsPVSHX04xTtfYKo2zv3Iw0BLQ8R+9Lfsl/QazHo/H1UC6f3tnaXpqXK4jZiU0X6KRyJs=@vger.kernel.org X-Gm-Message-State: AOJu0Yyqp7UecxGR36S5UprNqRzreJaci379iRjkG6O3Y6UzgFAjmZtz m6H7MAcqbS15/U02NI05porEuC6wtcPgj8nWweo1afh1Vcu94ca+gYX5mHKT3Qo= X-Google-Smtp-Source: AGHT+IEWKnix5ITqvENAXxypC3bZpawDtQsVVhD1tV5/rTPnlQTkYQAFRPzt6jP6cYqsKGikHAplJw== X-Received: by 2002:a05:6512:4020:b0:52e:9fe0:bee4 with SMTP id 2adb3069b0e04-533407870f1mr1226654e87.9.1724149173472; Tue, 20 Aug 2024 03:19:33 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:33 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 03/11] i2c: riic: Use pm_runtime_resume_and_get() Date: Tue, 20 Aug 2024 13:19:10 +0300 Message-Id: <20240820101918.2384635-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea pm_runtime_get_sync() may return with error. In case it returns with error dev->power.usage_count needs to be decremented. pm_runtime_resume_and_get() takes care of this. Thus use it. Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - collected tags Changes in v3: - dropped error message on pm_runtime_resume_and_get() failures - restored initial place of i2c_del_adapter() in riic_i2c_remove() Changes in v2: - delete i2c adapter all the time in remove drivers/i2c/busses/i2c-riic.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 2e119024c2d7..6fc41bde2ec2 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -133,10 +133,12 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) struct riic_dev *riic = i2c_get_adapdata(adap); struct device *dev = adap->dev.parent; unsigned long time_left; - int i; + int i, ret; u8 start_bit; - pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) { riic->err = -EBUSY; @@ -301,6 +303,7 @@ static const struct i2c_algorithm riic_algo = { static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) { + int ret; unsigned long rate; int total_ticks, cks, brl, brh; struct device *dev = riic->adapter.dev.parent; @@ -379,7 +382,9 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) t->scl_fall_ns / (1000000000 / rate), t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); - pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; /* Changing the order of accessing IICRST and ICE may break things! */ riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); @@ -498,10 +503,13 @@ static void riic_i2c_remove(struct platform_device *pdev) { struct riic_dev *riic = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; + int ret; - pm_runtime_get_sync(dev); - riic_writeb(riic, 0, RIIC_ICIER); - pm_runtime_put(dev); + ret = pm_runtime_resume_and_get(dev); + if (!ret) { + riic_writeb(riic, 0, RIIC_ICIER); + pm_runtime_put(dev); + } i2c_del_adapter(&riic->adapter); pm_runtime_disable(dev); } From patchwork Tue Aug 20 10:19:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 820756 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2687918E038 for ; Tue, 20 Aug 2024 10:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149178; cv=none; b=N/+i75FK5yjkc16LXacAM+rqr6K7+2aolGx77dbiAR4TVugL63izLQgwYB5YtDt2yny2ntKgagwHYriIsbRNY5jwyZMyRjIzbcQB+hsUfLoC78Q1jvKcpCjaGY4duMIvxO9kxzASakpXwZB9ecwHNPi2RwOP8/4l6DfLuRx9fbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149178; c=relaxed/simple; bh=vem8p96L0oMWQEyldLlJtpVhQ994QqnmR0ohREVf2Pc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HMsTubwNGvA8u7+lvkMBGpl5vlGPba/RRzCv54pebl1UB8d1e1mrNZia3RZnOHubBPZ6RBSEBZewv5nWceEylPFr81pzly/xJkL9FF+JQrFqBCQlR/lARQY8bSR/aNrZKYTx6dF5eyVH6U2ZbovIa5VTIwf7a85z+t2SF1z78BQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=VMS5VtPj; arc=none smtp.client-ip=209.85.208.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="VMS5VtPj" Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-2f029e9c9cfso25625531fa.2 for ; Tue, 20 Aug 2024 03:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724149175; x=1724753975; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ks+2YRAyKgKRE43sjfM9QF4KPwZ0caq5YtrlIAthty4=; b=VMS5VtPjE70UurK+Dk/MxfZbykcsfzo5d+1YEodewel6ocBpfJa3ZqDJyNObe/v6hC r23YYCCNJXkBOTibds8f3Wab+0WaiGLEZtfzmoJvSv95JuB/H981G7YGH0wknim8xzje hO/0V5oG5OcKUlBfovnEeb2KJ6/i8LoSlMNTKNVm3ptj+F/NJ14w4cEAKtVsEsnr5xRM dhkOhj9nOpCsuGc8GxvFDJSbGSKJCk9ldyW5MRs3oSE6McF7X5BLKpBD3VW9mT1kZfqF ELlalWaFL/kySMQPGx9HFi0ZaF6NOttMxhEfKhLyYbr+CPC7tUeBuExGWu7nq2vNpj3a xsbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724149175; x=1724753975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ks+2YRAyKgKRE43sjfM9QF4KPwZ0caq5YtrlIAthty4=; b=iTuA3JOiSF+j+upyEHV25pXdFjWJAuSw2S+L42YsGCfbBlsyDEmhpApOLwLYZieaZq 6fsxDYKa0fKdoh7QIBJWYOcKyMxhuaOHu3gT2EvIq2nFk8cyPyZNrRR43kqjZL/RvcNo bPrPxcMKtJyjGPiKVgR+ozNGT5Mkd7pG89ybzDIjYa+53BLm5RvxPzDfCc0tbM6gMwDk awFTMEAMScPiZ/HBC8gFC9iPLWt/IeTARFI1sigcdIYeGYQzUl/JMhbHFHdEiCUurDLc oJR1b9egO+l2DgDxEdb37UXLO98oErdXgprLI9qaWdJaFMhfxqu6DjkKxDW9PeNt5Z+S MFnQ== X-Forwarded-Encrypted: i=1; AJvYcCXtCBIilNg8uFxpFf7aiUA8e3TbOWp2CVMBDl2NgZ/DbEq6l01RheOC1jt68oNgPcOLu3iaLDX15rc=@vger.kernel.org X-Gm-Message-State: AOJu0Yzf6H9EaPQCVxOYDF/9dro+ZKKI3D5HP+DJhhKPbOr9Tmxhytr7 58Xuz90elGOvs0WeKb81VVj3hXP13mUWILnnJMXJiV37pouvTdkGIEgpxQP+ABg= X-Google-Smtp-Source: AGHT+IFlb9J3A3Mxm0nx13hYdwklVJKspWeIpZSmdrnA+oVIdgB3VI1lpHABkqDCTT2rIQJsnXm5jw== X-Received: by 2002:a05:651c:54f:b0:2f3:f256:aeec with SMTP id 38308e7fff4ca-2f3f2573d65mr4517381fa.19.1724149175056; Tue, 20 Aug 2024 03:19:35 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 04/11] i2c: riic: Enable runtime PM autosuspend support Date: Tue, 20 Aug 2024 13:19:11 +0300 Message-Id: <20240820101918.2384635-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable runtime PM autosuspend support for the RIIC driver. With this, in case there are consecutive xfer requests the device wouldn't be runtime enabled/disabled after each consecutive xfer but after the the delay configured by user. With this, we can avoid touching hardware registers involved in runtime PM suspend/resume saving in this way some cycles. The default chosen autosuspend delay is zero to keep the previous driver behavior. Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - collected tags - added a comment on top of pm_runtime_set_autosuspend_delay() Changes in v3: - none Changes in v2: - none drivers/i2c/busses/i2c-riic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 6fc41bde2ec2..ec854a525a0b 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -171,7 +171,8 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) } out: - pm_runtime_put(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return riic->err ?: num; } @@ -399,7 +400,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); - pm_runtime_put(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return 0; } @@ -479,6 +481,9 @@ static int riic_i2c_probe(struct platform_device *pdev) i2c_parse_fw_timings(dev, &i2c_t, true); + /* Default 0 to save power. Can be overridden via sysfs for lower latency. */ + pm_runtime_set_autosuspend_delay(dev, 0); + pm_runtime_use_autosuspend(dev); pm_runtime_enable(dev); ret = riic_init_hw(riic, &i2c_t); @@ -496,6 +501,7 @@ static int riic_i2c_probe(struct platform_device *pdev) out: pm_runtime_disable(dev); + pm_runtime_dont_use_autosuspend(dev); return ret; } @@ -512,6 +518,7 @@ static void riic_i2c_remove(struct platform_device *pdev) } i2c_del_adapter(&riic->adapter); pm_runtime_disable(dev); + pm_runtime_dont_use_autosuspend(dev); } static const struct riic_of_data riic_rz_a_info = { From patchwork Tue Aug 20 10:19:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 821890 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA3FA18E744 for ; Tue, 20 Aug 2024 10:19:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149180; cv=none; b=rs+cHFd0Q/8jUaRN+e+DZpNu4Cu3aW553k1z/Eggh6bW0rdgwMqn6R/75bUkNiP1RJz1ET/1sAxGE8Tq37gmMKreu2jt83hevoVSulwJB8aUS/yIXLLcH3KL4g6Gp/Gnv8m+bVXnujx8KAV57/G7CZrKaz/MHZWZTbDtsCI3RKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149180; c=relaxed/simple; bh=Wr5nznH60aPy5RZ1toMDvv67f/JbqCseJWfH2M7+ODU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qo7xuyD1Hy+qnjMxf6vO2gOtwIm3oV0052Q68Zsq/8OBLgRa2gdF1lqxrs/HJELpVWlJAIfrXjl7tF3S9uO1auxGZV0tNZ2D7fLVFRccQacFy3hCJT2qGZwDrJWHRXnojohEwWFeA6sGTIFeBCQRi9K6IOF4cQ4gSgVUAEAqizc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ZiXKEQOx; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ZiXKEQOx" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a7a9e25008aso664782066b.0 for ; Tue, 20 Aug 2024 03:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724149177; x=1724753977; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kP0OsNI0P+8dZfKavF7RqDgnlmT2Fdk1y9BAkCcY/5s=; b=ZiXKEQOxks/3QSN40RzMzs01z5ZIk6B3u860TULvW3IC1NTUNWgeULD5wCZOmn9E44 meA0FeApB0/y6u6MHjyj0Ay9BUU3MQFOBxDIgXr5fs442GrQqI+wW2auUZxHiIiwUbRc TU0HEfK3XTptrcjpZ+VRp6fRxJGTJj2wMUkVbAJ/brknMkXR5GjotHHC4i66dTI880zK rQcdkXckFELgdSYzQzA9jadjL35JtuYFksBeL4e1jDjloqM0IuGts+KO0RYTUCjJWXzE uHu28Vo3nnpLAghqUwMPVRTvhPP45egNyLq1jPo07TXnRpNWNVGjlRuovlrdQxgendip qJvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724149177; x=1724753977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kP0OsNI0P+8dZfKavF7RqDgnlmT2Fdk1y9BAkCcY/5s=; b=V1IhtsCKsV0HZUA8omXB7L3D+gpRh3eW51U+r3/o+6pberp/5ZP2oY79SUJExVHCpx NxBj4udnX5Al5MLEVBULZBtSfLaLbhUdcOWbDz3rLpv+laVZ9g19zyfJewRnRzGw9oH0 YCNMKXMlA2hZmKm11EtssMwTt0xDWAdnxYZimfW3jpVYb24QzxCBi4oiqTiCHMe4URNc aFR+ly3PRe593B43An/EEQYIsr8q9wCmbS/uGeVzuhQ4SKVkWxVJ20binmTbbtr4T6AX lnvvKEIYecE38/7K7/1rWO3pBjoX0Q6oEcmAaEz88RkrweJ/sW00BMJSC4nI33ySEZeQ 2tlw== X-Forwarded-Encrypted: i=1; AJvYcCUqgw6S6+v0UY35dUKv1S5G1+B4L9Kb6ChkRcw7mVEejv1srFbt7I04xxhZC9g6QVEGx3VydsjEkfY=@vger.kernel.org X-Gm-Message-State: AOJu0YwPCk2eYnDiNm7BOtiEZqcKmjPDr0H3TfPd0iBM68oG26v5vbNZ nk9m6kwATvuwdZcewo5izFKHEY/1Ukg23omHQwznC8tayuFvR3CUJ8eWRsjy2Ug= X-Google-Smtp-Source: AGHT+IEer6zUIkK9BunJKsfiVnr14g7TQUujSD8dQthJ3M69JW4ySk89ZCjoBOJfAU6drUiQDI6ECw== X-Received: by 2002:a17:907:e2e8:b0:a7a:b620:aa3a with SMTP id a640c23a62f3a-a8392a2231fmr1007954466b.52.1724149176584; Tue, 20 Aug 2024 03:19:36 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 05/11] i2c: riic: Add suspend/resume support Date: Tue, 20 Aug 2024 13:19:12 +0300 Message-Id: <20240820101918.2384635-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add suspend/resume support for the RIIC driver. This is necessary for the Renesas RZ/G3S SoC which support suspend to deep sleep state where power to most of the SoC components is turned off. As a result the I2C controller needs to be reconfigured after suspend/resume. For this, the reset line was stored in the driver private data structure as well as i2c timings. The reset line and I2C timings are necessary to re-initialize the controller after resume. Reviewed-by: Andi Shyti Signed-off-by: Claudiu Beznea --- Changes in v5: - collected tags - added a comment on riic_i2c_resume() to explain why the reset signal is asserted on failure path Changes in v4: - rebased on top of latest next Changes in v3: - none Changes in v2: - deassert the reset line in resume if riic_init_hw() fails as if that happens there is no way to recover the controller drivers/i2c/busses/i2c-riic.c | 73 +++++++++++++++++++++++++++++------ 1 file changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index ec854a525a0b..eb741d4b1005 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -105,6 +105,8 @@ struct riic_dev { struct completion msg_done; struct i2c_adapter adapter; struct clk *clk; + struct reset_control *rstc; + struct i2c_timings i2c_t; }; struct riic_irq_desc { @@ -302,11 +304,12 @@ static const struct i2c_algorithm riic_algo = { .functionality = riic_func, }; -static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) +static int riic_init_hw(struct riic_dev *riic) { int ret; unsigned long rate; int total_ticks, cks, brl, brh; + struct i2c_timings *t = &riic->i2c_t; struct device *dev = riic->adapter.dev.parent; if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { @@ -423,8 +426,6 @@ static int riic_i2c_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct riic_dev *riic; struct i2c_adapter *adap; - struct i2c_timings i2c_t; - struct reset_control *rstc; int i, ret; riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); @@ -441,16 +442,16 @@ static int riic_i2c_probe(struct platform_device *pdev) return PTR_ERR(riic->clk); } - rstc = devm_reset_control_get_optional_exclusive(dev, NULL); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), + riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(riic->rstc)) + return dev_err_probe(dev, PTR_ERR(riic->rstc), "Error: missing reset ctrl\n"); - ret = reset_control_deassert(rstc); + ret = reset_control_deassert(riic->rstc); if (ret) return ret; - ret = devm_add_action_or_reset(dev, riic_reset_control_assert, rstc); + ret = devm_add_action_or_reset(dev, riic_reset_control_assert, riic->rstc); if (ret) return ret; @@ -479,14 +480,14 @@ static int riic_i2c_probe(struct platform_device *pdev) init_completion(&riic->msg_done); - i2c_parse_fw_timings(dev, &i2c_t, true); + i2c_parse_fw_timings(dev, &riic->i2c_t, true); /* Default 0 to save power. Can be overridden via sysfs for lower latency. */ pm_runtime_set_autosuspend_delay(dev, 0); pm_runtime_use_autosuspend(dev); pm_runtime_enable(dev); - ret = riic_init_hw(riic, &i2c_t); + ret = riic_init_hw(riic); if (ret) goto out; @@ -496,7 +497,7 @@ static int riic_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, riic); - dev_info(dev, "registered with %dHz bus speed\n", i2c_t.bus_freq_hz); + dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz); return 0; out: @@ -553,6 +554,55 @@ static const struct riic_of_data riic_rz_v2h_info = { }, }; +static int riic_i2c_suspend(struct device *dev) +{ + struct riic_dev *riic = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + i2c_mark_adapter_suspended(&riic->adapter); + + /* Disable output on SDA, SCL pins. */ + riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_sync(dev); + + return reset_control_assert(riic->rstc); +} + +static int riic_i2c_resume(struct device *dev) +{ + struct riic_dev *riic = dev_get_drvdata(dev); + int ret; + + ret = reset_control_deassert(riic->rstc); + if (ret) + return ret; + + ret = riic_init_hw(riic); + if (ret) { + /* + * In case this happens there is no way to recover from this + * state. The driver will remain loaded. We want to avoid + * keeping the reset line de-asserted for no reason. + */ + reset_control_assert(riic->rstc); + return ret; + } + + i2c_mark_adapter_resumed(&riic->adapter); + + return 0; +} + +static const struct dev_pm_ops riic_i2c_pm_ops = { + SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume) +}; + static const struct of_device_id riic_i2c_dt_ids[] = { { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info }, { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info }, @@ -565,6 +615,7 @@ static struct platform_driver riic_i2c_driver = { .driver = { .name = "i2c-riic", .of_match_table = riic_i2c_dt_ids, + .pm = pm_ptr(&riic_i2c_pm_ops), }, }; From patchwork Tue Aug 20 10:19:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 820755 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 173F318E75E for ; Tue, 20 Aug 2024 10:19:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149181; cv=none; b=B52PtZ8tRmcz16BFdVCgJyPkbrgTuxELHBwpnLX+BMMp8eLHaD40yNqTMV432qAsCT8XaFPHy5zGw4K4WRjAPwDIOXDucSFAT4MbDmNoDBZxoeTEmUwxWItW0p9iQIl8n3zBw9rvhZDg/XMju2gHUKkhkhLKYz7QjFRmA9fSe4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149181; c=relaxed/simple; bh=tUI85jO7Cpl1pB/o0KZqowvldcpXZzdz+AXIa2Z6P24=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PGVD8YZKz9KGymX6ZenDVhxTCskpAnP1Q5WEbFpNGjCbZTB10sMNmbgKM3O0cCQFsQWvStNEVvERPJgezbL0fFquEBfMWJcqIKff2I/7SKYN4EgyKcg1hPFLF6+2stz08Gn1ISbpaDDyIU+AYAj5qphyirLDSh+KDoy74my30aQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=A+I9+1fO; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="A+I9+1fO" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a83869373b6so545903466b.2 for ; Tue, 20 Aug 2024 03:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724149178; x=1724753978; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/HlaFt2mfcDs3v7cVtqEFaICLthaNdqu1VtbRc8xTWA=; b=A+I9+1fO/JS9or3QqSTjIp8NUTmibDQvAVUO04hAwqeilduu65xNzsQyUTVSL7MoGF FvR1n2xL+GZJc0FoKvl6bSpnYPPKHyN+6nV5WBERkeIPth0Jfz+9C+4BD+jSSGtMtVFS Cz26GurRKdKaiOdas2oLyoodPGnW9/YjaPEkqWY2jB/imvRNc0aykfPP6dnIQDw2h6gP QOwMGY8cCyvgnCjGWstM8u0/Eq8NJ/LH7hvL/siPOFMvTfJEG/qH50b8zBMrhrDKtWDg KNb4td8tO8SV71uCBihjvl7z62tK7nyjcxHqw0zrFlA/S/q7LK6LEJkC3HPd3P6Oeaxx uyPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724149178; x=1724753978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/HlaFt2mfcDs3v7cVtqEFaICLthaNdqu1VtbRc8xTWA=; b=VOPEiAADwEOAnAPVuMIY0Zn2MAB0gLuw8sdfD6D56R+GdQVvBJW8ylX4vfGnPeVh2x 6Fw3t+6uSFLwSOabQGFc4wpkrsjgJNXgY2YX6EBN/3Kone2TNpQRI7Wzi3/MqyG1TiIY rNQJfvHLlSb1UiKvTWVphNW2qO0s5dtKZJoNQnpRpW5KfZT/ouNim+1txBsXCNnsfGMS hqvNltO2350V/2nxLlzBAawMbjwrG4i5nPk5nrfp9ekvxlTGSgnEpN9+rjujzDb6S6Re H2rFRrzobKe+uluxoyukWwQG9zBPpYOeSmQMKjxNtXyLSmxrGGpcozCxNIBiuvJjRSQE m5CQ== X-Forwarded-Encrypted: i=1; AJvYcCXUOJ9WudWj3bv1tMHEVYicPQRU/sDuA0IBRlXLnzcPzgC7ywbTngsmBvi3ulyyivi1k7eQSnl2UIOac93PfyNoKguYmt4FK5Uw X-Gm-Message-State: AOJu0YyHp238WUmD5tszZ8vIfPAS9mMjUUCOO56gowrg1nzrk4kBiTQ8 wCswRqMbeV7u0ffNprNb5rxRX5Cpq+a2vc1mOpe64pi6k3BEaDaZcaDiXwfZYBs= X-Google-Smtp-Source: AGHT+IHXhspWPuCSOnb/GLwsDgiKU0Bp/C97L8hMioAeuTeoW28g4CRpcwe1UoHbElZr1QVsv5vZtg== X-Received: by 2002:a17:907:e2c3:b0:a7a:b1a8:6a2e with SMTP id a640c23a62f3a-a839292ff2bmr915681866b.28.1724149178268; Tue, 20 Aug 2024 03:19:38 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 06/11] i2c: riic: Define individual arrays to describe the register offsets Date: Tue, 20 Aug 2024 13:19:13 +0300 Message-Id: <20240820101918.2384635-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Define individual arrays to describe the register offsets. In this way we can describe different IP variants that share the same register offsets but have differences in other characteristics. Commit prepares for the addition of fast mode plus. Reviewed-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - collected tags Changes in v3: - none Changes in v2: - none drivers/i2c/busses/i2c-riic.c | 58 +++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index eb741d4b1005..f7293bf4b585 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -91,7 +91,7 @@ enum riic_reg_list { }; struct riic_of_data { - u8 regs[RIIC_REG_END]; + const u8 *regs; }; struct riic_dev { @@ -522,36 +522,40 @@ static void riic_i2c_remove(struct platform_device *pdev) pm_runtime_dont_use_autosuspend(dev); } +static const u8 riic_rz_a_regs[RIIC_REG_END] = { + [RIIC_ICCR1] = 0x00, + [RIIC_ICCR2] = 0x04, + [RIIC_ICMR1] = 0x08, + [RIIC_ICMR3] = 0x10, + [RIIC_ICSER] = 0x18, + [RIIC_ICIER] = 0x1c, + [RIIC_ICSR2] = 0x24, + [RIIC_ICBRL] = 0x34, + [RIIC_ICBRH] = 0x38, + [RIIC_ICDRT] = 0x3c, + [RIIC_ICDRR] = 0x40, +}; + static const struct riic_of_data riic_rz_a_info = { - .regs = { - [RIIC_ICCR1] = 0x00, - [RIIC_ICCR2] = 0x04, - [RIIC_ICMR1] = 0x08, - [RIIC_ICMR3] = 0x10, - [RIIC_ICSER] = 0x18, - [RIIC_ICIER] = 0x1c, - [RIIC_ICSR2] = 0x24, - [RIIC_ICBRL] = 0x34, - [RIIC_ICBRH] = 0x38, - [RIIC_ICDRT] = 0x3c, - [RIIC_ICDRR] = 0x40, - }, + .regs = riic_rz_a_regs, +}; + +static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { + [RIIC_ICCR1] = 0x00, + [RIIC_ICCR2] = 0x01, + [RIIC_ICMR1] = 0x02, + [RIIC_ICMR3] = 0x04, + [RIIC_ICSER] = 0x06, + [RIIC_ICIER] = 0x07, + [RIIC_ICSR2] = 0x09, + [RIIC_ICBRL] = 0x10, + [RIIC_ICBRH] = 0x11, + [RIIC_ICDRT] = 0x12, + [RIIC_ICDRR] = 0x13, }; static const struct riic_of_data riic_rz_v2h_info = { - .regs = { - [RIIC_ICCR1] = 0x00, - [RIIC_ICCR2] = 0x01, - [RIIC_ICMR1] = 0x02, - [RIIC_ICMR3] = 0x04, - [RIIC_ICSER] = 0x06, - [RIIC_ICIER] = 0x07, - [RIIC_ICSR2] = 0x09, - [RIIC_ICBRL] = 0x10, - [RIIC_ICBRH] = 0x11, - [RIIC_ICDRT] = 0x12, - [RIIC_ICDRR] = 0x13, - }, + .regs = riic_rz_v2h_regs, }; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:39 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , Conor Dooley Subject: [PATCH v5 07/11] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support Date: Tue, 20 Aug 2024 13:19:14 +0300 Message-Id: <20240820101918.2384635-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with the version available on Renesas RZ/V2H (R9A09G075). Acked-by: Conor Dooley Signed-off-by: Claudiu Beznea --- Changes in v5: - added back Conor's tag Changes in v4: - added comment near the fallback for RZ/G3S; because of this dropped Conor's tag Changes in v3: - collected tags Changes in v2: - dropped the renesas,riic-no-fast-mode-plus - updated commit description Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 7993fe463c4c..505a8ec92266 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -25,6 +25,10 @@ properties: - renesas,riic-r9a07g054 # RZ/V2L - const: renesas,riic-rz # RZ/A or RZ/G2L + - items: + - const: renesas,riic-r9a08g045 # RZ/G3S + - const: renesas,riic-r9a09g057 # RZ/V2H(P) + - const: renesas,riic-r9a09g057 # RZ/V2H(P) reg: From patchwork Tue Aug 20 10:19:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 820754 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FEAB18EFEC for ; Tue, 20 Aug 2024 10:19:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149185; cv=none; b=KbU7+k2PwRRAn+4fYzKW/xFndEKeHEEWMZEIZw2wLqZXCpNYYQjRPYqLRqVme4dCxxZJf5Y/cJSIR5T8MMRDtO4vo0LWduqb8v03r6QNA5dFjsL3ECJlex6N9sgVz76JhXIwzjb6BTOpmJMXs/K4KtJhMnbAbWDFH32ffONgWhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149185; c=relaxed/simple; bh=KI03NXaMd1QC9VE9Z4VVaE0H506C/htfrmJvTUjjSHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OhiL2slvDLngIK33+FEFGsTXl0znGN/2XvaVvFdwnlGxdGU4iEq3I93DjrD6yU55fGIjT9c45Ir5tjrqmcrP9Ef1aAzPoaEgdIqY5e57jFIrz2fXv8wwbq40r5D7713uVQx48TXHRdX0UItDt/klP+1oOysgL94aiOLNw01Oies= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=SKRB8aFJ; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="SKRB8aFJ" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a83562f9be9so480247866b.0 for ; Tue, 20 Aug 2024 03:19:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724149182; x=1724753982; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=219c63JbxhJlvsmjhtmJRprxFDazu4TcqcxKlP/ynos=; b=SKRB8aFJF6prmhA9Cr4a1G8C3sFKKmxj5PMNxK/7LwKt7C4KKObSslMlQXp640xXbU 9GYO2eIza68gQcd0z/+CMVIv5caMYIwHyIFtuNVbbmlprKSVb64+scb3mLK4s5HOT0JJ qKEdq1uodP8vOVEns0FDq/eJ8fqPzcCOjGKW5Wgk7Ek5TrnuceTy4u7B4QReH22494RX Ig5XVv+sbcmAMfG5CvNoMVnLMI/O0G8R0OI91Zwb3fzsl7TPYku0PBMG1/E65IIR2D+W V3umbj5Ww5FMMKWF8wePwTVuZO5hzHyvgUcErHNwyLRiccayIQAbgBMDwRyoDOiYpGXq WjwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724149182; x=1724753982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=219c63JbxhJlvsmjhtmJRprxFDazu4TcqcxKlP/ynos=; b=mv3BkDMwwAtzw3oS0ATxmiMJx162haGkUVc441s/jclWfB8wt1IEgKRdvXiUG7NJRT tfb41keOySP0TgNSb4pnlfjdrubrAz8y12OQ6B1rBa45oLpsg6jJAIyAdyeT5KHjY8yI 3RLqg5B4eVihMouP/0dz3NNqcmxLiMzpuL3BQcgcsT7IkBpHpTAayLO7q2uTkfHPGg0Y bm50vdE0tuRRQQZFDHiwVbADi5MPI8KnN7KThRUoydUsxuawaiwstn8LKqRUmDFGcMUV UF+G0q8DqUntkfHrp1fUzhtOYqus1dLG9aL9/OtlJewfRIsw0DWgSQef26RS+Y8N84GA PaDA== X-Forwarded-Encrypted: i=1; AJvYcCUX4P++u2ADp/jm1qLhqLeDtdhFJLRKlb7ADYZKVjlslHi9YpfRH/YKFFhzLcaOMIzyNgk+qKkr4gTeVCRUZ46O/30pTv0yIRcV X-Gm-Message-State: AOJu0Yyoqnp+P2Y4zxfMdb9+Y9lRCUNfU/behPpJxSNgC9N+cVNoA7Q6 NW2Uvui8h69DKLZH6Oeo/EOB9l+qWuYKTtnWzmiT44nJVNzW7IrT4P9Z5JW32WU= X-Google-Smtp-Source: AGHT+IE7gA6ysW6bEpwxOFRB6xikUMRG6dFr1SONaXIuUFoRYhenFe3YI2z2jpTk6Y6jiWJph9+30Q== X-Received: by 2002:a17:907:e6a0:b0:a7a:9fe9:99e7 with SMTP id a640c23a62f3a-a8392955fdamr996588466b.41.1724149181778; Tue, 20 Aug 2024 03:19:41 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:41 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 08/11] i2c: riic: Add support for fast mode plus Date: Tue, 20 Aug 2024 13:19:15 +0300 Message-Id: <20240820101918.2384635-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Fast mode plus is available on most of the IP variants that RIIC driver is working with. The exception is (according to HW manuals of the SoCs where this IP is available) the Renesas RZ/A1H. For this, patch introduces the struct riic_of_data::fast_mode_plus. Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by instantiating the RIIC frequency to 1MHz and issuing i2c reads on the fast mode plus capable devices (and the i2c clock frequency was checked on RZ/G3S). Signed-off-by: Claudiu Beznea --- Changes in v5: - added local variable in riic_init_hw() to store the fast_mode_plus and used it all over the places - align arguments of the 1st dev_err() in riic_init_hw() as suggested on review Changes in v4: - in riic_init_hw() checked t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ before applying hardware settings Changes in v3: - enabled FM+ for all riic_rz_a_info based platforms except RZ/A1H as requested in review comments; with this, dropped the riic_rz_g2_info and RZ/G2 specific compatibles in riic_i2c_dt_ids[]; Note that it has been tested only on platforms mentioned in commit description (as I don't have all the other RZ/A platforms). Changes in v2: - dropped code that handles the renesas,riic-no-fast-mode-plus - updated commit description drivers/i2c/busses/i2c-riic.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index f7293bf4b585..a6996f3c1711 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -63,6 +63,8 @@ #define ICMR3_ACKWP 0x10 #define ICMR3_ACKBT 0x08 +#define ICFER_FMPE 0x80 + #define ICIER_TIE 0x80 #define ICIER_TEIE 0x40 #define ICIER_RIE 0x20 @@ -80,6 +82,7 @@ enum riic_reg_list { RIIC_ICCR2, RIIC_ICMR1, RIIC_ICMR3, + RIIC_ICFER, RIIC_ICSER, RIIC_ICIER, RIIC_ICSR2, @@ -92,6 +95,7 @@ enum riic_reg_list { struct riic_of_data { const u8 *regs; + bool fast_mode_plus; }; struct riic_dev { @@ -311,11 +315,15 @@ static int riic_init_hw(struct riic_dev *riic) int total_ticks, cks, brl, brh; struct i2c_timings *t = &riic->i2c_t; struct device *dev = riic->adapter.dev.parent; + bool fast_mode_plus = riic->info->fast_mode_plus; - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { + if ((!fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) || + (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)) { dev_err(&riic->adapter.dev, "unsupported bus speed (%dHz). %d max\n", - t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); + t->bus_freq_hz, + fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ : + I2C_MAX_FAST_MODE_FREQ); return -EINVAL; } @@ -401,6 +409,9 @@ static int riic_init_hw(struct riic_dev *riic) riic_writeb(riic, 0, RIIC_ICSER); riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3); + if (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) + riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER); + riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); pm_runtime_mark_last_busy(dev); @@ -527,6 +538,7 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { [RIIC_ICCR2] = 0x04, [RIIC_ICMR1] = 0x08, [RIIC_ICMR3] = 0x10, + [RIIC_ICFER] = 0x14, [RIIC_ICSER] = 0x18, [RIIC_ICIER] = 0x1c, [RIIC_ICSR2] = 0x24, @@ -538,6 +550,11 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_a_info = { .regs = riic_rz_a_regs, + .fast_mode_plus = true, +}; + +static const struct riic_of_data riic_rz_a1h_info = { + .regs = riic_rz_a_regs, }; static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { @@ -545,6 +562,7 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { [RIIC_ICCR2] = 0x01, [RIIC_ICMR1] = 0x02, [RIIC_ICMR3] = 0x04, + [RIIC_ICFER] = 0x05, [RIIC_ICSER] = 0x06, [RIIC_ICIER] = 0x07, [RIIC_ICSR2] = 0x09, @@ -556,6 +574,7 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_v2h_info = { .regs = riic_rz_v2h_regs, + .fast_mode_plus = true, }; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 09/11] arm64: dts: renesas: r9a08g045: Add I2C nodes Date: Tue, 20 Aug 2024 13:19:16 +0300 Message-Id: <20240820101918.2384635-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S has 4 I2C channels. Add DT nodes for it. Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - none Changes in v3: - none Changes in v2: - dropped renesas,riic-no-fast-mode-plus arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 37885cd24f16..e44e8949e22a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,94 @@ scif0: serial@1004b800 { status = "disabled"; }; + i2c0: i2c@10090000 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C0_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@10090400 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C1_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10090800 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C2_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@10090c00 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:44 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 10/11] arm64: dts: renesas: rzg3s-smarc: Enable i2c0 node Date: Tue, 20 Aug 2024 13:19:17 +0300 Message-Id: <20240820101918.2384635-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable i2c0 node. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v5: - none Changes in v4: - none Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index deb2ad37bb2e..7945d44e6ee1 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,7 @@ / { aliases { + i2c0 = &i2c0; serial0 = &scif0; mmc1 = &sdhi1; }; @@ -66,6 +67,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <1000000>; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; From patchwork Tue Aug 20 10:19:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 821887 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9207718FC88 for ; Tue, 20 Aug 2024 10:19:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149190; cv=none; b=X52QhczsvIwlCFd8H8k8KvvIhhQl3bNp0N4GA+CEX/7yFvhOC4Y7RIJMKA/HgRUe8P0KBc99fsa5cWRh1Pp1cCCK1Uv/zxiPhUySESRY/stW7tL26vW/cJXfn2K0jxRZoIkXbgrEc/s81cayME1bNjwDkgDZLIuD4VXONNgkWeo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149190; c=relaxed/simple; bh=/tKUzOHrRt266Tu45Ds7SUJPkjzc5fK4AjYP3mwcytU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lenGjjgV6igOTvNWzA9JXnY+Hv7Ju0S9iJgVcDGQawQIBLnXw23RAwwdfneUW+ukNDlqW2OT4vlB6heiXBFu73uMXV+aZ/kjXuinbUxyHzL+3Gdd0O9FQrMRN311u5wHITyw3+v/jwNRqsB9c/fIOAottBvem6JdM7XieOiTKg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=fpOt9+iM; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="fpOt9+iM" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3718eaf4046so3382364f8f.3 for ; Tue, 20 Aug 2024 03:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724149187; x=1724753987; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aBK2n6/pFj/ILXvmSt1CdVdmwT9MRszPiHjEVvASYLo=; b=fpOt9+iM184UDLNogONTc0yYH4D3mA3PvH0xS4GwinBQmIHiajeq1RH8+EAzVbE9cO zgb4UkoqeHrRwl0gIkMW+siHWmU4OEyTZ1LaY8xIytGySFooGUuJVwIyARnXnLACQFDV lNJ3aXuZkHTMEHTfV3GskoiPr0T5NlXCIX70AUESMlC45RqI7mD0Z6NK6UfFKuZo2UT8 NqKK7A9QghRDl5TVjkFk9YsJ5S8rgMSr0lmAqVtbDPH/n76i30la3sOWWXiH6FIco4Dg EFVzN6Q6PAZSKT45AiPxJyklaThYvL6PG9egdsKz6MbScB3Qhqm3QiouW2Pq8TUvLkkC lQ+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724149187; x=1724753987; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aBK2n6/pFj/ILXvmSt1CdVdmwT9MRszPiHjEVvASYLo=; b=Md+0BwCDt1XxsvZ93uhuoJBwfYE5Jyn67obD2RvWcMPlBceYi82a0M+Y7wDK4AXGLq EasngH5Lu+FojZWVk/nqHoUJXlOzVBh0UoXmaZyB6LRDdB/YmI+Mgd3/Ro4BQXrnqi73 Cjuz8SxkM/1XrgEabbBIa/loUBwlyanqm0guySzgeeJxw5OSwALNxIJDCDgNnOk0ekB+ l4fyf5FtQw0YZsGVznx1ZhEdUqEFWyN4LMvhzJeWta06huq6wpgT40yshS+UaRWgb2Ec Gb/gka5m5clgVYnUTxIXfW/9FHon4dFxq737KqW4lnlSxD5nauovdv0DCW8KC3TZ0KBy H66Q== X-Forwarded-Encrypted: i=1; AJvYcCUnrhU4MfuqSr7usK1Njt2J4cFLu/u0BUROCdlCpMItRyPQdCrdwl4yddos1y5+UrD6/83d9GW3xBM=@vger.kernel.org X-Gm-Message-State: AOJu0YyaFcKmUopkpjvB6qTupfZVX0BGTT+ijOcbOmY+UBj0e0PXrk2J x59V6SCJGLPq3SvKHkgrb8Rt/XGPnR2fx1mdmGIMmG1cMUmF46u12Jg+LPa17Mo= X-Google-Smtp-Source: AGHT+IGOhXXhbrXYtNIqlBM6EFLynq9Nkm50wQEMf0Wrby599QYliScoeHDmNCsdfFrFuBUGx/PJKg== X-Received: by 2002:a5d:43c7:0:b0:368:4c38:a668 with SMTP id ffacd0b85a97d-3719431566fmr11712818f8f.9.1724149186736; Tue, 20 Aug 2024 03:19:46 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83839464ebsm734550066b.155.2024.08.20.03.19.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 03:19:46 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v5 11/11] arm64: dts: renesas: rzg3s-smarc-som: Enable i2c1 node Date: Tue, 20 Aug 2024 13:19:18 +0300 Message-Id: <20240820101918.2384635-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> References: <20240820101918.2384635-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable i2c1 node. Signed-off-by: Claudiu Beznea --- Changes in v5: - none Changes in v4: - none Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 8a3d302f1535..21bfa4e03972 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -32,6 +32,7 @@ / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { + i2c1 = &i2c1; mmc0 = &sdhi0; #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; @@ -150,6 +151,10 @@ &extal_clk { clock-frequency = <24000000>; }; +&i2c1 { + status = "okay"; +}; + #if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 {