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Mon, 19 Aug 2024 12:34:23 -0700 (PDT) Received: from [192.168.0.113] ([2a02:8109:aa0d:be00::676e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8383964976sm667783666b.188.2024.08.19.12.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2024 12:34:22 -0700 (PDT) From: Caleb Connolly Date: Mon, 19 Aug 2024 21:34:17 +0200 Subject: [PATCH 1/4] clk/qcom: implement clk dump MIME-Version: 1.0 Message-Id: <20240819-b4-qcom-clk-dump-v1-1-182cf77c23a2@linaro.org> References: <20240819-b4-qcom-clk-dump-v1-0-182cf77c23a2@linaro.org> In-Reply-To: <20240819-b4-qcom-clk-dump-v1-0-182cf77c23a2@linaro.org> To: Lukasz Majewski , Sean Anderson , Neil Armstrong , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6493; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=nxK/d88itr3JtU0XB/+xiwMh0xK1wVyYi3ERrQRJ7+o=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmw548lE4+ZYQEf6s4J88uxTA5OLnejqK6CaDLW EeMosZOgyaJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZsOePAAKCRAFgzErGV9k tnQEEACY7XgKSOnyZNWYoAg0JgXGxmLNOSgNqbHEgmdVaA1Hv2N4mFvtsnnsAUbOw6IYQEWTenN d1dULvdBUQnPr8xQtAxIKhPyTOv3iiOLJCVCgPVY7Vnyrmm1Q2oq8ay7FasX7xX+ynEaRXXBzs1 DZtUwBcz4wX5XO+yLbFoBzZ/+jpJtN3FTHSg5ZbWQaPzrgGdOCqhQH4OX68hCUsn1ygSIZlS7Sv 1pGAeyxkh5rhYbR9kUPhu5RCTzFrx2Z9bKOUk9niZ/gJMXVz/1vNDKuk8K/Q+np/eU3lB2nnZs5 plpPPClTLKEcNn2HC4vidFfoiTVFzaG6Zggp5hm+Lc/QpHnx4tmF0JV2iXrxfL2nIS3YnAyQUyD 31VSrAeK7ZBqonqY0vyiJn/AkOjCUPKSCe38mDDhv5BgF1JkKNP09/LJXEJI0qW9gTqKibfKp0c 6/MvmXlqmkMQ/aclUmG6GIRdo/PYu1S3gcjojqlGMAAQyNSCmKx/9wVgLZlvteVJizk+as8IpY7 kmoXPFQ6dNZ59pLy1ZJ1rlkyRlKtZyPh6ixqtSwJDfGqYCx+HnIBWR+YASeMcJV2WjU7zseuPUy ZpAt/O1tmSAK0ELYkiwjVr3Jv8i+bq8bQ8TBRFAz4AMnYhMTedYer01Z7cUI25RDCdv3O0kll/K TR//k9SlrSFhaaw== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-.c. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ 2 files changed, 123 insertions(+) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 79c7606a2253..5727d055e95a 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -12,8 +12,9 @@ * Based on Little Kernel driver, simplified */ #include +#include #include #include #include #include @@ -214,11 +215,127 @@ static int msm_clk_enable(struct clk *clk) return 0; } +static void dump_gplls(struct udevice *dev, phys_addr_t base) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + u32 i; + bool locked; + u64 l, a, xo_rate = 19200000; + struct clk *clk = NULL; + struct udevice *xodev; + const phys_addr_t *gplls = data->dbg_pll_addrs; + + uclass_foreach_dev_probe(UCLASS_CLK, xodev) { + if (!strcmp(xodev->name, "xo-board") || !strcmp(xodev->name, "xo_board")) { + clk = dev_get_clk_ptr(xodev); + break; + } + } + + if (clk) { + xo_rate = clk_get_rate(clk); + + /* On SDM845 this needs to be divided by 2 for some reason */ + if (xo_rate && of_machine_is_compatible("qcom,sdm845")) + xo_rate /= 2; + } else { + printf("Can't find XO clock, XO_BOARD rate may be wrong\n"); + } + + printf("GPLL clocks:\n"); + printf("| GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA |\n"); + printf("+--------+--------+-----------+------------+----------------+\n"); + for (i = 0; i < data->num_plls; i++) { + locked = !!(readl(gplls[i]) & BIT(31)); + l = readl(gplls[i] + 4) & (BIT(16) - 1); + a = readq(gplls[i] + 40) & (BIT(16) - 1); + printf("| GPLL%-2d | %-6s | %9llu * (%#-9llx + %#-13llx * 2 ** -40 ) / 1000000\n", + i, locked ? "X" : "", xo_rate, l, a); + } +} + +static void dump_rcgs(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + int i; + u32 cmd; + u32 cfg; + u32 not_n_minus_m; + u32 src, m, n, div; + bool root_on, d_odd; + + printf("\nRCGs:\n"); + + /* + * Which GPLL SRC corresponds to depends on the parent map, see gcc-.c in Linux + * and find the parent map associated with the clock. Note that often there are multiple + * outputs from a single GPLL where one is actually half the rate of the other (_EVEN). + * intput_freq = associated GPLL output freq (potentially divided depending on SRC). + */ + printf("| NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] |\n"); + printf("+----------------------------------+----+-----+---------------------------------------+--------------+\n"); + for (i = 0; i < data->num_rcgs; i++) { + cmd = readl(data->dbg_rcg_addrs[i]); + cfg = readl(data->dbg_rcg_addrs[i] + 0x4); + m = readl(data->dbg_rcg_addrs[i] + 0x8); + n = 0; + not_n_minus_m = readl(data->dbg_rcg_addrs[i] + 0xc); + + root_on = !(cmd & BIT(31)); // ROOT_OFF + src = (cfg >> 8) & 7; + + if (not_n_minus_m) { + n = (~not_n_minus_m & 0xffff); + + /* A clumsy assumption that this is an 8-bit MND RCG */ + if ((n & 0xff00) == 0xff00) + n = n & 0xff; + + n += m; + } + + div = ((cfg & 0b11111) + 1) / 2; + d_odd = ((cfg & 0b11111) + 1) % 2 == 1; + printf("%-34s | %-2s | %3d | input_freq * (%4d/%5d) * (1/%1d%-2s) | [%#010x]\n", + data->dbg_rcg_names[i], root_on ? "X" : "", src, + m ?: 1, n ?: 1, div, d_odd ? ".5" : "", cmd); + } + + printf("\n"); +} + +static void msm_dump_clks(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + const struct gate_clk *sclk; + int val, i; + + if (!data->clks) { + printf("No clocks\n"); + return; + } + + printf("Gate Clocks:\n"); + for (i = 0; i < data->num_clks; i++) { + sclk = &data->clks[i]; + if (!sclk->name) + continue; + printf("%-32s: ", sclk->name); + val = readl(priv->base + sclk->reg) & sclk->en_val; + printf("%s\n", val ? "ON" : ""); + } + + dump_gplls(dev, priv->base); + dump_rcgs(dev); +} + static struct clk_ops msm_clk_ops = { .set_rate = msm_clk_set_rate, .enable = msm_clk_enable, + .dump = msm_dump_clks, }; U_BOOT_DRIVER(qcom_clk) = { .name = "qcom_clk", diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f6445c8f566f..040c0cf29943 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -75,8 +75,14 @@ struct msm_clk_data { unsigned long num_resets; const struct gate_clk *clks; unsigned long num_clks; + const phys_addr_t *dbg_pll_addrs; + unsigned long num_plls; + const phys_addr_t *dbg_rcg_addrs; + unsigned long num_rcgs; + const char * const *dbg_rcg_names; + int (*enable)(struct clk *clk); unsigned long (*set_rate)(struct clk *clk, unsigned long rate); }; From patchwork Mon Aug 19 19:34:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 820275 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c8:0:b0:367:895a:4699 with SMTP id m8csp1591370wrb; Mon, 19 Aug 2024 12:34:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV9XA2E4KnXaUHUWZt1Tyimqg/TIjB6yD/KXhtRcisF5ijm1aSQKbcXRLuYCqlo7LlANJNEBA==@linaro.org X-Google-Smtp-Source: AGHT+IE4Z7U/a2CtuzxlQ1j/o6dXustimMLbNV0eYtlySBpNQgrBk0gUiMZNz75VOYmpnVA/zDHR X-Received: by 2002:a05:6602:6404:b0:822:4344:5b6a with SMTP id ca18e2360f4ac-824f26ad901mr1820344539f.10.1724096090390; Mon, 19 Aug 2024 12:34:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1724096090; cv=none; d=google.com; s=arc-20160816; b=cUiIckBgqWuBcEtGDP9yulQKuCxAkb08nRMOb2sIASU01fGhQ99uXuiqJ1uGdhM6jS 79bNlygLpQXuXGACxQKE5Wz15j+K8q33VG3Ne1ljScK0r6gpWioJwonvrWG5o1Zr4TsF mcDgV6ZsU6GDk4NZAz7NzGKgVs4Ke72PZr2UDr4OBDsv+B9Caeg6YEs/LLde0/mYBO89 Hgd0vGb2hDGO0bbsxtBef4vlTNsG/U3oaa98HpB41t7H+9Gvd94DX+4TrZkTiOPPYLN/ ECkxV7HMYYGvOHpqNJ9Sps7TD9dbmuwSS9oZDPIrIYFVoE5i7FmgZuzxqFw8jTPHswbI 4cKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=GTr66mSU4Vru9Y1q5TaXUqjtPY4DyoBYunKN4yraEyo=; fh=HWWPvUNRhy4Qj892x6sRLy07CRoEFOVzrU6iUrpZvlI=; b=x/qRp/dwRjmg0swBwyDzAOAhLa5wqSIKDJZF7ibr6XLvXLPHhHWyCdHMQx7MuNPE2E xV3hbHrGvAAoxNk6FZxXlWjF+OvjJDXCIgf2p8KjVIgIM2HvC9g1y8Dv4LX7bFVUU3/4 M0oIALjpht0PhtqPkZoh8MzNt4YJkWWe/Do+AM1lr/rDMHMCmqAJiq0vJ7oabURnEr+c l5J8+vXFxjIrJG83PIQDDkv6Q1YT9+aJSlyxaRif/XVa1ZC2kY+nrAlADUqCe3pgk12J xvEPjsrB96nFT6OeY44j3ccCo7J5k24I17xiWYiyBs2S/mo+2YSApY8dLE6P8R9L6tph 7GpQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZutHQI3y; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Mon, 19 Aug 2024 12:34:23 -0700 (PDT) From: Caleb Connolly Date: Mon, 19 Aug 2024 21:34:18 +0200 Subject: [PATCH 2/4] clk/qcom: sdm845: add dump data MIME-Version: 1.0 Message-Id: <20240819-b4-qcom-clk-dump-v1-2-182cf77c23a2@linaro.org> References: <20240819-b4-qcom-clk-dump-v1-0-182cf77c23a2@linaro.org> In-Reply-To: <20240819-b4-qcom-clk-dump-v1-0-182cf77c23a2@linaro.org> To: Lukasz Majewski , Sean Anderson , Neil Armstrong , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3942; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=VBGTaoTLCP0hDeMcg8fJUKbNu/8Z9t1pUuSzLkeb4GE=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmw548wW0qEmi3kxpZXHKO6w85I3awGApojpGFE EV462BhEmqJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZsOePAAKCRAFgzErGV9k tuiSD/4k8uMJGFJdlnGJKkyxuTzIyNqfA4Z+/GXaYFTczVb7Cry/C4G+TT7nyQ3qnMSC5G4K63E hlUTqxM+JfNwK71Up5noteQVWxfLNNjDYXejQpL3dtThDx8nWtTcmDYgu+sXWrY1t2tsKBU+PBx hsP1hzaXO6PcnE5f0dY7MLQdrVnQf0KRbiFfuZojLp4P9L0h0pTulhfjwhaYdnewOKad98i7/ml fh+jgWwYyTLyXZyu2jVLRWMdNLTpgOYUp8xrmpnUrZSXP2eyT2txPqcCc20/3j26n5QaGU5v3cA hV1OVWs7PmGI0pYSUEQVU21Tj7HTlFiCn2Iqm0wIkqrMMdLBHRBC7vazp+4eeJwgl9Fgu2uh7pb TDfOl1B84Iv5LQvf9jIFi0LLyE1tdOfsUQloPme756kstsLXfmNyGANZQ/RrQpTwDQBlSt+ozOc OzjvQs8zXFZHwM9kuKZCA/i1A/RDJfz2qbhmEhynZa/FLkbkxYOM1E/3llIBZhrkUrpp8mkw8L2 Zhyi63PR1qosuUI/u0LF8WlMAFcNJnA6bSh3KYSjgIVUT8HmUE6FniBvUDy0R2W38yn23wnmgI5 yP8o6JPQc1QyDM0TQUXwkKLOtRdbhIIe+FU0RuiKbpbAruJbkcUA23PEH/NWy8bVYSOvt2gB/ae qyhnZudm5yOiFLA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add debug data to dump PLL and RCG clocks. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sdm845.c | 93 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index f41f8c9e8dee..adffb0cb2402 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -202,8 +202,96 @@ static const struct qcom_power_map sdm845_gdscs[] = { [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, }; +static const phys_addr_t sdm845_gpll_addrs[] = { + 0x00100000, // GCC_GPLL0_MODE + 0x00101000, // GCC_GPLL1_MODE + 0x00102000, // GCC_GPLL2_MODE + 0x00103000, // GCC_GPLL3_MODE + 0x00176000, // GCC_GPLL4_MODE + 0x00174000, // GCC_GPLL5_MODE + 0x00113000, // GCC_GPLL6_MODE +}; + +static const phys_addr_t sdm845_rcg_addrs[] = { + 0x0010f018, // GCC_USB30_PRIM_MASTER + 0x0010f030, // GCC_USB30_PRIM_MOCK_UTMI + 0x0010f05c, // GCC_USB3_PRIM_PHY_AUX + 0x00110018, // GCC_USB30_SEC_MASTER + 0x00110030, // GCC_USB30_SEC_MOCK_UTMI + 0x0011005c, // GCC_USB3_SEC_PHY_AUX + 0x0011400c, // GCC_SDCC2_APPS + 0x0011600c, // GCC_SDCC4_APPS + 0x00117018, // GCC_QUPV3_WRAP0_CORE_2X + 0x00117034, // GCC_QUPV3_WRAP0_S0 + 0x00117164, // GCC_QUPV3_WRAP0_S1 + 0x00117294, // GCC_QUPV3_WRAP0_S2 + 0x001173c4, // GCC_QUPV3_WRAP0_S3 + 0x001174f4, // GCC_QUPV3_WRAP0_S4 + 0x00117624, // GCC_QUPV3_WRAP0_S5 + 0x00117754, // GCC_QUPV3_WRAP0_S6 + 0x00117884, // GCC_QUPV3_WRAP0_S7 + 0x00118018, // GCC_QUPV3_WRAP1_S0 + 0x00118148, // GCC_QUPV3_WRAP1_S1 + 0x00118278, // GCC_QUPV3_WRAP1_S2 + 0x001183a8, // GCC_QUPV3_WRAP1_S3 + 0x001184d8, // GCC_QUPV3_WRAP1_S4 + 0x00118608, // GCC_QUPV3_WRAP1_S5 + 0x00118738, // GCC_QUPV3_WRAP1_S6 + 0x00118868, // GCC_QUPV3_WRAP1_S7 + 0x0016b028, // GCC_PCIE_0_AUX + 0x0018d028, // GCC_PCIE_1_AUX + 0x0016f014, // GCC_PCIE_PHY_REFGEN + 0x0017501c, // GCC_UFS_CARD_AXI + 0x0017505c, // GCC_UFS_CARD_ICE_CORE + 0x00175074, // GCC_UFS_CARD_UNIPRO_CORE + 0x00175090, // GCC_UFS_CARD_PHY_AUX + 0x0017701c, // GCC_UFS_PHY_AXI + 0x0017705c, // GCC_UFS_PHY_ICE_CORE + 0x00177074, // GCC_UFS_PHY_UNIPRO_CORE + 0x00177090, // GCC_UFS_PHY_PHY_AUX +}; + +static const char *const sdm845_rcg_names[] = { + "GCC_USB30_PRIM_MASTER", + "GCC_USB30_PRIM_MOCK_UTMI", + "GCC_USB3_PRIM_PHY_AUX", + "GCC_USB30_SEC_MASTER", + "GCC_USB30_SEC_MOCK_UTMI", + "GCC_USB3_SEC_PHY_AUX", + "GCC_SDCC2_APPS", + "GCC_SDCC4_APPS", + "GCC_QUPV3_WRAP0_CORE_2X", + "GCC_QUPV3_WRAP0_S0", + "GCC_QUPV3_WRAP0_S1", + "GCC_QUPV3_WRAP0_S2", + "GCC_QUPV3_WRAP0_S3", + "GCC_QUPV3_WRAP0_S4", + "GCC_QUPV3_WRAP0_S5", + "GCC_QUPV3_WRAP0_S6", + "GCC_QUPV3_WRAP0_S7", + "GCC_QUPV3_WRAP1_S0", + "GCC_QUPV3_WRAP1_S1", + "GCC_QUPV3_WRAP1_S2", + "GCC_QUPV3_WRAP1_S3", + "GCC_QUPV3_WRAP1_S4", + "GCC_QUPV3_WRAP1_S5", + "GCC_QUPV3_WRAP1_S6", + "GCC_QUPV3_WRAP1_S7", + "GCC_PCIE_0_AUX", + "GCC_PCIE_1_AUX", + "GCC_PCIE_PHY_REFGEN", + "GCC_UFS_CARD_AXI", + "GCC_UFS_CARD_ICE_CORE", + "GCC_UFS_CARD_UNIPRO_CORE", + "GCC_UFS_CARD_PHY_AUX", + "GCC_UFS_PHY_AXI", + "GCC_UFS_PHY_ICE_CORE", + "GCC_UFS_PHY_UNIPRO_CORE", + "GCC_UFS_PHY_PHY_AUX", +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, @@ -212,8 +300,13 @@ static struct msm_clk_data sdm845_clk_data = { .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, + .dbg_pll_addrs = sdm845_gpll_addrs, + .num_plls = ARRAY_SIZE(sdm845_gpll_addrs), + .dbg_rcg_addrs = sdm845_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sdm845_rcg_addrs), + .dbg_rcg_names = sdm845_rcg_names, }; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add "clk dump" support for SM6115. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sm6115.c | 63 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c index 8314a0deb348..9057dfe0bb18 100644 --- a/drivers/clk/qcom/clock-sm6115.c +++ b/drivers/clk/qcom/clock-sm6115.c @@ -169,8 +169,65 @@ static const struct qcom_reset_map sm6115_gcc_resets[] = { static const struct qcom_power_map sm6115_gdscs[] = { [GCC_USB30_PRIM_GDSC] = { 0x1a004 }, }; +static const phys_addr_t sm6115_gpll_addrs[] = { + 0x01400000, // GCC_GPLL0_MODE + 0x01401000, // GCC_GPLL1_MODE + 0x01402000, // GCC_GPLL2_MODE + 0x01403000, // GCC_GPLL3_MODE + 0x01404000, // GCC_GPLL4_MODE + 0x01405000, // GCC_GPLL5_MODE + 0x01406000, // GCC_GPLL6_MODE + 0x01407000, // GCC_GPLL7_MODE + 0x01408000, // GCC_GPLL8_MODE + 0x01409000, // GCC_GPLL9_MODE + 0x0140a000, // GCC_GPLL10_MODE + 0x0140b000, // GCC_GPLL11_MODE +}; + +static const phys_addr_t sm6115_rcg_addrs[] = { + 0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x01438028, // GCC_SDCC1_APPS_CMD_RCGR + 0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0141f018, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR + 0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x01428014, // GCC_SLEEP_CMD_RCGR + 0x0142802c, // GCC_XO_CMD_RCGR + 0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR +}; + +static const char *const sm6115_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_SDCC1_APPS_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_SLEEP_CMD_RCGR", + "GCC_XO_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", +}; + static struct msm_clk_data sm6115_gcc_data = { .resets = sm6115_gcc_resets, .num_resets = ARRAY_SIZE(sm6115_gcc_resets), .clks = sm6115_clks, @@ -179,8 +236,14 @@ static struct msm_clk_data sm6115_gcc_data = { .num_power_domains = ARRAY_SIZE(sm6115_gdscs), .enable = sm6115_enable, .set_rate = sm6115_set_rate, + + .dbg_pll_addrs = sm6115_gpll_addrs, + .num_plls = ARRAY_SIZE(sm6115_gpll_addrs), + .dbg_rcg_addrs = sm6115_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm6115_rcg_addrs), + .dbg_rcg_names = sm6115_rcg_names, }; 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Drop in the RCG and GPLL data for debugging these clocks. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-sm8250.c | 115 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c index af10fc116219..e322a923a5c0 100644 --- a/drivers/clk/qcom/clock-sm8250.c +++ b/drivers/clk/qcom/clock-sm8250.c @@ -252,8 +252,117 @@ static const struct qcom_power_map sm8250_gdscs[] = { [UFS_PHY_GDSC] = { 0x77004 }, [USB30_PRIM_GDSC] = { 0xf004 }, [USB30_SEC_GDSC] = { 0x10004 }, }; +static const phys_addr_t sm8250_gpll_addrs[] = { + 0x00100000, // GCC_GPLL0_MODE + 0x00101000, // GCC_GPLL1_MODE + 0x00102000, // GCC_GPLL2_MODE + 0x00103000, // GCC_GPLL3_MODE + 0x00176000, // GCC_GPLL4_MODE + 0x00174000, // GCC_GPLL5_MODE + 0x00113000, // GCC_GPLL6_MODE + 0x0011a000, // GCC_GPLL7_MODE + 0x0011b000, // GCC_GPLL8_MODE + 0x0011c000, // GCC_GPLL9_MODE + 0x0011d000, // GCC_GPLL10_MODE + 0x0014a000, // GCC_GPLL11_MODE +}; + +static const phys_addr_t sm8250_rcg_addrs[] = { + 0x0010f020, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0010f038, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0010f064, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x00110020, // GCC_USB30_SEC_MASTER_CMD_RCGR + 0x00110038, // GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR + 0x00110064, // GCC_USB3_SEC_PHY_AUX_CMD_RCGR + 0x0011400c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0011600c, // GCC_SDCC4_APPS_CMD_RCGR + 0x0012300c, // GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR + 0x00117010, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x00117140, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x00117270, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x001173a0, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x001174d0, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x00117600, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x00117730, // GCC_QUPV3_WRAP0_S6_CMD_RCGR + 0x00117860, // GCC_QUPV3_WRAP0_S7_CMD_RCGR + 0x00123144, // GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR + 0x00118010, // GCC_QUPV3_WRAP1_S0_CMD_RCGR + 0x00118140, // GCC_QUPV3_WRAP1_S1_CMD_RCGR + 0x00118270, // GCC_QUPV3_WRAP1_S2_CMD_RCGR + 0x001183a0, // GCC_QUPV3_WRAP1_S3_CMD_RCGR + 0x001184d0, // GCC_QUPV3_WRAP1_S4_CMD_RCGR + 0x00118600, // GCC_QUPV3_WRAP1_S5_CMD_RCGR + 0x0016b038, // GCC_PCIE_0_AUX_CMD_RCGR + 0x0018d038, // GCC_PCIE_1_AUX_CMD_RCGR + 0x0016f014, // GCC_PCIE_PHY_REFGEN_CMD_RCGR + 0x00175024, // GCC_UFS_CARD_AXI_CMD_RCGR + 0x0017506c, // GCC_UFS_CARD_ICE_CORE_CMD_RCGR + 0x00175084, // GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR + 0x001750a0, // GCC_UFS_CARD_PHY_AUX_CMD_RCGR + 0x00177024, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x0017706c, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x00177084, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x001770a0, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR + 0x0012327c, // GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR + 0x0011e010, // GCC_QUPV3_WRAP2_S0_CMD_RCGR + 0x0011e140, // GCC_QUPV3_WRAP2_S1_CMD_RCGR + 0x0011e270, // GCC_QUPV3_WRAP2_S2_CMD_RCGR + 0x0011e3a0, // GCC_QUPV3_WRAP2_S3_CMD_RCGR + 0x0011e4d0, // GCC_QUPV3_WRAP2_S4_CMD_RCGR + 0x0011e600, // GCC_QUPV3_WRAP2_S5_CMD_RCGR + 0x0010d00c, // GCC_RBCPR_MMCX_CMD_RCGR + 0x00106038, // GCC_PCIE_2_AUX_CMD_RCGR +}; + +static const char *const sm8250_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_USB30_SEC_MASTER_CMD_RCGR", + "GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_SEC_PHY_AUX_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_SDCC4_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_QUPV3_WRAP0_S6_CMD_RCGR", + "GCC_QUPV3_WRAP0_S7_CMD_RCGR", + "GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP1_S0_CMD_RCGR", + "GCC_QUPV3_WRAP1_S1_CMD_RCGR", + "GCC_QUPV3_WRAP1_S2_CMD_RCGR", + "GCC_QUPV3_WRAP1_S3_CMD_RCGR", + "GCC_QUPV3_WRAP1_S4_CMD_RCGR", + "GCC_QUPV3_WRAP1_S5_CMD_RCGR", + "GCC_PCIE_0_AUX_CMD_RCGR", + "GCC_PCIE_1_AUX_CMD_RCGR", + "GCC_PCIE_PHY_REFGEN_CMD_RCGR", + "GCC_UFS_CARD_AXI_CMD_RCGR", + "GCC_UFS_CARD_ICE_CORE_CMD_RCGR", + "GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_CARD_PHY_AUX_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", + "GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR", + "GCC_QUPV3_WRAP2_S0_CMD_RCGR", + "GCC_QUPV3_WRAP2_S1_CMD_RCGR", + "GCC_QUPV3_WRAP2_S2_CMD_RCGR", + "GCC_QUPV3_WRAP2_S3_CMD_RCGR", + "GCC_QUPV3_WRAP2_S4_CMD_RCGR", + "GCC_QUPV3_WRAP2_S5_CMD_RCGR", + "GCC_RBCPR_MMCX_CMD_RCGR", + "GCC_PCIE_2_AUX_CMD_RCGR", +}; + static struct msm_clk_data qcs404_gcc_data = { .resets = sm8250_gcc_resets, .num_resets = ARRAY_SIZE(sm8250_gcc_resets), .clks = sm8250_clks, @@ -262,8 +371,14 @@ static struct msm_clk_data qcs404_gcc_data = { .num_power_domains = ARRAY_SIZE(sm8250_gdscs), .enable = sm8250_enable, .set_rate = sm8250_set_rate, + + .dbg_pll_addrs = sm8250_gpll_addrs, + .num_plls = ARRAY_SIZE(sm8250_gpll_addrs), + .dbg_rcg_addrs = sm8250_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm8250_rcg_addrs), + .dbg_rcg_names = sm8250_rcg_names, }; static const struct udevice_id gcc_sm8250_of_match[] = { {