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Cc: qemu-stable@nongnu.org Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 113639083b..c803e8d1ba 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4521,7 +4521,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) TRANS(STF, ALL, do_st_fpr, a, MO_32) TRANS(STDF, ALL, do_st_fpr, a, MO_64) -TRANS(STQF, ALL, do_st_fpr, a, MO_128) +TRANS(STQF, 64, do_st_fpr, a, MO_128) TRANS(STFA, 64, do_st_fpr, a, MO_32) TRANS(STDFA, 64, do_st_fpr, a, MO_64) From patchwork Fri Aug 16 07:23:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 819730 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c8:0:b0:367:895a:4699 with SMTP id m8csp162088wrb; Fri, 16 Aug 2024 00:25:05 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWN1mFMEYKw47ISHKy37BDohpbMKizwpKqtaolm2mNtX7h0NloQn8fA6lBLw+r8SWFgiGAVmgB8bljD1dj8fdHu X-Google-Smtp-Source: AGHT+IHs2uG2HNuah0Uo1cwb//RbHdnP0yKRW/fs4lvUjufZcoHG1VG3QTaacX8nCpUrBEWr/+UK X-Received: by 2002:a05:6902:c0d:b0:e11:7246:9632 with SMTP id 3f1490d57ef6-e1180e84cdamr2795262276.4.1723793105494; Fri, 16 Aug 2024 00:25:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723793105; cv=none; d=google.com; s=arc-20160816; b=m357gwmTuRR55Duw424P/Wac6G8t8/YWYgdQwfqaduAVTHRNhMV2k2MVze9nw3elNv nYHTyI3DmsMU/Yy1dSICyZ2WUla2Fc4HhVtCGdrkKOL+/+RTYAKSqonhqvbkGo4v6D3Y HzNeTdAYtspKuAw1kPEy+EPkxM2OFSxtvBJkwHpZ6PGFgL8GYg8Q4g7xdRkOErNCW5Rz zevj9OPNET3VjZSDPWM+/8QEwlCH51wbCxfb+eaaUrONp0p7lTkJrEXK6TjlniVr4wQF hb9bxBmgpRClNzRaKjnCK2ScpYMZ1W6FGM4qSFicq1ypp6cYJejVjliiaFSFafUFbU0y leLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gpBjGkW6BU4v1nqztsjjBjF53uYRgoULCdoJY53mCgc=; fh=p/+L0Odm18RRMlFO3Np611soLgx+p9X23e419/JuZ6o=; b=eVbz0CdyZgl92s9SPzMHqKf75nEBNByMbPLwQVj78EXLjSMzYbLfPK9ne9iB+nPDSe l4VwyFgsc0imTVSKzOeKsbL145qge/e+XKYdzR3CpfRUQ/IMmbMvjQb0Eb+11zDZGviL /d8S2XYfagwiXuZjvzfAr/T1YjTWfi+w3JAZO+t/e9VgZ5NFUu39CGoUACRG8Y6KeIz8 5fBX86wcvLcijmEHoT6LvxXm0LXEoLDRQG20DcuhitbAXDS1kG52V0Wl/G2HMout+T8a 9ylELX8IuD081fCDyp/2MR9+yCY7lrHwOkzDv4Iss62kI28d33Yb6/xJdfzJ3F56CQ0t SE8A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hv7mQFCg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 2/6] target/sparc: Add FQ and FSR.QNE Date: Fri, 16 Aug 2024 17:23:07 +1000 Message-ID: <20240816072311.353234-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Carl Hauser Add support for, and migrate, a single-entry fp instruction queue for sparc32. Signed-off-by: Carl Hauser [rth: Split from a larger patch; adjust representation with union; add migration state] Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 22 ++++++++++++++++++++++ target/sparc/fop_helper.c | 4 ++++ target/sparc/machine.c | 25 +++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index dfd9512a21..9f2bc44722 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -184,6 +184,8 @@ enum { #define FSR_FTT_SEQ_ERROR (4ULL << 14) #define FSR_FTT_INVAL_FPR (6ULL << 14) +#define FSR_QNE (1ULL << 13) + #define FSR_FCC0_SHIFT 10 #define FSR_FCC1_SHIFT 32 #define FSR_FCC2_SHIFT 34 @@ -438,6 +440,26 @@ struct CPUArchState { uint32_t fsr_cexc_ftt; /* cexc, ftt */ uint32_t fcc[TARGET_FCCREGS]; /* fcc* */ +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + /* + * Single-element FPU fault queue, with address and insn, + * packaged into the double-word with which it is stored. + */ + uint32_t fsr_qne; /* qne */ + union { + uint64_t d; + struct { +#if HOST_BIG_ENDIAN + uint32_t addr; + uint32_t insn; +#else + uint32_t insn; + uint32_t addr; +#endif + } s; + } fq; +#endif + CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted from PSR) */ diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 0b30665b51..b6692382b3 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -545,6 +545,8 @@ target_ulong cpu_get_fsr(CPUSPARCState *env) fsr |= (uint64_t)env->fcc[1] << FSR_FCC1_SHIFT; fsr |= (uint64_t)env->fcc[2] << FSR_FCC2_SHIFT; fsr |= (uint64_t)env->fcc[3] << FSR_FCC3_SHIFT; +#elif !defined(CONFIG_USER_ONLY) + fsr |= env->fsr_qne; #endif /* VER is kept completely separate until re-assembly. */ @@ -591,6 +593,8 @@ void cpu_put_fsr(CPUSPARCState *env, target_ulong fsr) env->fcc[1] = extract64(fsr, FSR_FCC1_SHIFT, 2); env->fcc[2] = extract64(fsr, FSR_FCC2_SHIFT, 2); env->fcc[3] = extract64(fsr, FSR_FCC3_SHIFT, 2); +#elif !defined(CONFIG_USER_ONLY) + env->fsr_qne = fsr & FSR_QNE; #endif set_fsr_nonsplit(env, fsr); diff --git a/target/sparc/machine.c b/target/sparc/machine.c index 48e0cf22f3..222e5709c5 100644 --- a/target/sparc/machine.c +++ b/target/sparc/machine.c @@ -143,6 +143,24 @@ static const VMStateInfo vmstate_xcc = { .get = get_xcc, .put = put_xcc, }; +#else +static bool fq_needed(void *opaque) +{ + SPARCCPU *cpu = opaque; + return cpu->env.fsr_qne; +} + +static const VMStateDescription vmstate_fq = { + .name = "cpu/fq", + .version_id = 1, + .minimum_version_id = 1, + .needed = fq_needed, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(env.fq.s.addr, SPARCCPU), + VMSTATE_UINT32(env.fq.s.insn, SPARCCPU), + VMSTATE_END_OF_LIST() + }, +}; #endif static int cpu_pre_save(void *opaque) @@ -265,4 +283,11 @@ const VMStateDescription vmstate_sparc_cpu = { #endif VMSTATE_END_OF_LIST() }, +#ifndef TARGET_SPARC64 + .subsections = (const VMStateDescription * const []) { + &vmstate_fq, + NULL + }, +#endif + }; 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[2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 3/6] target/sparc: Populate sparc32 FQ when raising fp exception Date: Fri, 16 Aug 2024 17:23:08 +1000 Message-ID: <20240816072311.353234-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Carl Hauser Implement a single instruction floating point queue, populated while delivering an fp exception. Signed-off-by: Carl Hauser [rth: Split from a larger patch] Signed-off-by: Richard Henderson --- target/sparc/int32_helper.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 6b7d65b031..fb6f3799c8 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -21,10 +21,10 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "sysemu/runstate.h" - static const char * const excp_names[0x80] = { [TT_TFAULT] = "Instruction Access Fault", [TT_ILL_INSN] = "Illegal Instruction", @@ -116,22 +116,9 @@ void sparc_cpu_do_interrupt(CPUState *cs) qemu_log("%6d: %s (v=%02x)\n", count, name, intno); log_cpu_state(cs, 0); -#if 0 - { - int i; - uint8_t *ptr; - - qemu_log(" code="); - ptr = (uint8_t *)env->pc; - for (i = 0; i < 16; i++) { - qemu_log(" %02x", ldub(ptr + i)); - } - qemu_log("\n"); - } -#endif count++; } -#if !defined(CONFIG_USER_ONLY) +#ifndef CONFIG_USER_ONLY if (env->psret == 0) { if (cs->exception_index == 0x80 && env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { @@ -143,6 +130,21 @@ void sparc_cpu_do_interrupt(CPUState *cs) } return; } + if (intno == TT_FP_EXCP) { + env->fsr_qne = FSR_QNE; + env->fq.s.addr = env->pc; + env->fq.s.insn = cpu_ldl_code(env, env->pc); + /* + * The sparc32 fpu has three states related to exception handling. + * The FPop that signals an exception transitions from fp_execute + * to fp_exception_pending. A subsequent FPop transitions from + * fp_exception_pending to fp_exception, which forces the trap. + * We do not model the fp_exception_pending state, but we do need + * to advance pc/npc to mimic the delayed trap delivery. + */ + env->pc = env->npc; + env->npc = env->npc + 4; + } #endif env->psret = 0; cwp = cpu_cwp_dec(env, env->cwp - 1); From patchwork Fri Aug 16 07:23:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 819728 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c8:0:b0:367:895a:4699 with SMTP id m8csp161959wrb; Fri, 16 Aug 2024 00:24:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWjAuKy8pY08Nnh5PCY8K70hArYtK4D6ye37W8+1M/ZZPG+H8m7NW2xHH+gwlBE115bptcwQYs+K68v5kiWyXXw X-Google-Smtp-Source: AGHT+IFkCIZetQq47FosTZ/i/OsRSEzoEYAgpKAl7XmNGrv8epO1XwW4+oIDQUyA1XVjC6HOArDd X-Received: by 2002:a05:6102:94d:b0:492:9ca1:d35e with SMTP id ada2fe7eead31-4977989b901mr2570118137.5.1723793067923; Fri, 16 Aug 2024 00:24:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723793067; cv=none; d=google.com; s=arc-20160816; b=zTsu6gENRb3WWksuTvUWcl+AobiFpAXiMIaWFcaqfyo2lrForqpZKQkGOIQTe3bxvA QIJto6V1H1Tikckqm5ECXaiZrWAYXMKXZNe9yG6WQHDqaw29lwC+LcnYNp26DyAz2fh8 gxnnOxqHR8h1vU7XJXnOysqWGRZOkkIrmxQcQkKsKUgCywZrSGZYlRWqQvTvi3Tx3xsA dFwxeaTpc4qtEIyVarPFi0OjErvOiugTF4orO9x8JUPgGNqqihSrL7ByG43/F/rKSi6r VFmhIMmAIuIA2XvVXsgpM8fo0GquWfWa17KslRwLnj9ZsGL08muH1AI+Y26Qq3Yi3ZYl gRcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=K5QfoW0VwajlTQd3ELmUEuobbsHpYmua9JmMsJd9x1U=; fh=p/+L0Odm18RRMlFO3Np611soLgx+p9X23e419/JuZ6o=; b=gwa+Jaxd3k2OkpD2K6nI8LDEW/Y298lYluqC5L+aZlIMFe6JIXst3BGqDdtSLK8eoX wpLb2BpSvpeX0G3aecj4BqUkMxaPBip6CgLEH9HgGBhIOo9W1WZcZk880AdkVgVqLeMk qSrW8XZN9wlR4APQsNRW3DSw+w9EdXPTLluxC0DvPZQsHqTv4Zr8t7G1CPajs3APj4H5 Oj0t66/C1MtgEp4fNOZvvCUoltaRA2AIHq91pRU6G3ZF2MrryrZfoXjbJuLgMJ7mXpkr 4b5oqi6A9Bb2IYzX/FqM53WEAD81H9+YvrW7M9Q8jFuHM/PfsUMz6Fm6lnWay5VF3hj+ 152g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Z/C/VAkU"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 4/6] target/sparc: Add FSR_QNE to tb_flags Date: Fri, 16 Aug 2024 17:23:09 +1000 Message-ID: <20240816072311.353234-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 8 +++++++- target/sparc/translate.c | 10 +++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 9f2bc44722..f517e5a383 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -744,6 +744,7 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_AM_ENABLED (1 << 5) #define TB_FLAG_SUPER (1 << 6) #define TB_FLAG_HYPER (1 << 7) +#define TB_FLAG_FSR_QNE (1 << 8) #define TB_FLAG_ASI_SHIFT 24 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, @@ -775,7 +776,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, if (env->psref) { flags |= TB_FLAG_FPU_ENABLED; } -#endif +#ifndef CONFIG_USER_ONLY + if (env->fsr_qne) { + flags |= TB_FLAG_FSR_QNE; + } +#endif /* !CONFIG_USER_ONLY */ +#endif /* TARGET_SPARC64 */ *pflags = flags; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c803e8d1ba..eb0158a11d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -185,6 +185,8 @@ typedef struct DisasContext { bool supervisor; #ifdef TARGET_SPARC64 bool hypervisor; +#else + bool fsr_qne; #endif #endif @@ -5596,13 +5598,15 @@ static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags); #ifndef CONFIG_USER_ONLY dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0; +# ifdef TARGET_SPARC64 + dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0; +# else + dc->fsr_qne = (dc->base.tb->flags & TB_FLAG_FSR_QNE) != 0; +# endif #endif #ifdef TARGET_SPARC64 dc->fprs_dirty = 0; dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; -#ifndef CONFIG_USER_ONLY - dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0; -#endif #endif /* * if we reach a page boundary, we stop generation so that the From patchwork Fri Aug 16 07:23:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 819727 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c8:0:b0:367:895a:4699 with SMTP id m8csp161952wrb; Fri, 16 Aug 2024 00:24:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUGNxohIm3RzJNTN3nIT0tFlsis9QSNbf+Umx+DEuQa6Qioi4VASubEVmotLOa2jGCQ1Q0p0eWD9jDpMCNYLte4 X-Google-Smtp-Source: AGHT+IHi+Tjt39lUCr98XUGD2LZZKABQO9AgLFlxD/jBQIcBYQlGD0YF+ECCtDOm1lR9q0mM0ISg X-Received: by 2002:a05:6214:5905:b0:6bf:7be1:5f45 with SMTP id 6a1803df08f44-6bf7cdeff29mr27982096d6.26.1723793065827; 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[2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 5/6] target/sparc: Implement STDFQ Date: Fri, 16 Aug 2024 17:23:10 +1000 Message-ID: <20240816072311.353234-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Invalid encoding of addr should raise TT_ILL_INSN, so check before supervisor, which might raise TT_PRIV_INSN. Clear QNE after execution. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 24 +++++++++++++++++++++++- target/sparc/insns.decode | 4 ++-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index eb0158a11d..6d4c0e79c9 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4531,17 +4531,39 @@ TRANS(STQFA, 64, do_st_fpr, a, MO_128) static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) { + TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (!avail_32(dc)) { return false; } + if (addr == NULL) { + return false; + } if (!supervisor(dc)) { return raise_priv(dc); } +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) if (gen_trap_ifnofpu(dc)) { return true; } - gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + if (dc->fsr_qne) { + TCGv_i64 fq = tcg_temp_new_i64(); + + /* Store the single element from the queue. */ + tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d)); + tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4); + + /* Mark the queue empty, transitioning to fp_execute state. */ + tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, + offsetof(CPUSPARCState, fsr_qne)); + dc->fsr_qne = 0; + } else { + gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + } return true; +#else + qemu_build_not_reached(); +#endif } static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index fbcb4f7aef..923f348580 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -644,8 +644,8 @@ STF 11 ..... 100100 ..... . ............. @r_r_ri_na STFSR 11 00000 100101 ..... . ............. @n_r_ri STXFSR 11 00001 100101 ..... . ............. @n_r_ri { - STQF 11 ..... 100110 ..... . ............. @q_r_ri_na - STDFQ 11 ----- 100110 ----- - ------------- + STQF 11 ..... 100110 ..... . ............. @q_r_ri_na # v9 + STDFQ 11 ..... 100110 ..... . ............. @r_r_ri # v7,v8 } STDF 11 ..... 100111 ..... . ............. @d_r_ri_na From patchwork Fri Aug 16 07:23:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 819726 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c8:0:b0:367:895a:4699 with SMTP id m8csp161897wrb; Fri, 16 Aug 2024 00:24:12 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWZVfl4VFTY5/A6jLKx8nCNNJ5iN/K/2PXa6x3vR6IAhovXQlkP2dqG1PiOjR++HSTererwsVIlipg60669MRr7 X-Google-Smtp-Source: AGHT+IGTA5X/Vk/pzVkZN6K3aH74NGOieODKlFa8whxiXkZHZ0oNk7L2g8gxIigKkXO4uMxuVAen X-Received: by 2002:a05:622a:2588:b0:453:5f63:747 with SMTP id d75a77b69052e-45374f81964mr30100011cf.10.1723793051766; Fri, 16 Aug 2024 00:24:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723793051; cv=none; d=google.com; s=arc-20160816; b=CqBbzthu0//1hzAaYWScIVrxq22dAQ5ylyBagTk+GThGwfD7RcrZm5YjphZXCjFwPs HqZSL737RdUUN6xtWSgNXy9T5Kb0REGcLtz4h/RIoBFiZcpx+qcEWeWgq3R++hoW52z/ rkSxyVfVPOb0ev05mJ34Z1WTPTZG0d+wGVxsvjNPqRum4DUF9fPUFeaAArMEJC2oNzg6 HSLLF0fXXVuG7prMubLEVHwHNPJuGLadloR5L+cyB8Qp+aN/CdnNOpyOIUWVDlKgu8Ns 4bBTzClUxQseKZnyfHimv9i1KOOov+Q5Q8MHJq+3l6LxodLkgFI8ZKMtoRJQfHQRAcb5 3bww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eY2K2/64+QKeWeBSKyuHFBnKeWv7V3FsHg7jq9ZTy0Y=; fh=p/+L0Odm18RRMlFO3Np611soLgx+p9X23e419/JuZ6o=; b=HZ+nsofsYMBn2jhwxVMrA0XmAh6WD6ZN5xExfkE4z/xvyPwM8fuFaTYD+SEQsX0qJX 88ehZdQ9dfgRYCVn+3tT+E5z+RoTPMnToIFNH/YFcJGFWq6j0aOVElw2GEOUFY3Sjxwa MpckaSPCCfsruE4yexgH5XPc9edCAMY2D1mpk9Y77r/O5enjJHTlcGWZeOtbxtsYrXpd DNW+WJhhj8pKAY0MPfD5Skwnzgi5gxunKosCIofgsE8LqwwguPq4x0OOINfYev2is4/f cLGrjCAzV66n/JulEm1Nc1V0ajNCjyQ51Geb7MAX9oQVn8rMz20fp7mONdxHxzsiOetu uIuQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=htwc9HDy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580a:f89b:0:1b6b:8c7b:90f9:144f]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-201f037588esm20195525ad.171.2024.08.16.00.23.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 00:23:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: chauser@pullman.com Subject: [PATCH v3 6/6] target/sparc: Add gen_trap_if_nofpu_fpexception Date: Fri, 16 Aug 2024 17:23:11 +1000 Message-ID: <20240816072311.353234-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240816072311.353234-1-richard.henderson@linaro.org> References: <20240816072311.353234-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Model fp_exception state, in which only fp stores are allowed until such time as the FQ has been flushed. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 90 +++++++++++++++++++++++++++------------- 1 file changed, 61 insertions(+), 29 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6d4c0e79c9..46eb27c497 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1465,15 +1465,48 @@ static void gen_op_fpexception_im(DisasContext *dc, int ftt) gen_exception(dc, TT_FP_EXCP); } -static int gen_trap_ifnofpu(DisasContext *dc) +static bool gen_trap_ifnofpu(DisasContext *dc) { #if !defined(CONFIG_USER_ONLY) if (!dc->fpu_enabled) { gen_exception(dc, TT_NFPU_INSN); - return 1; + return true; } #endif - return 0; + return false; +} + +static bool gen_trap_iffpexception(DisasContext *dc) +{ +#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + /* + * There are 3 states for the sparc32 fpu: + * Normally the fpu is in fp_execute, and all insns are allowed. + * When an exception is signaled, it moves to fp_exception_pending state. + * Upon seeing the next FPop, the fpu moves to fp_exception state, + * populates the FQ, and generates an fp_exception trap. + * The fpu remains in fp_exception state until FQ becomes empty + * after execution of a STDFQ instruction. While the fpu is in + * fp_exception state, and FPop, fp load or fp branch insn will + * return to fp_exception_pending state, set FSR.FTT to sequence_error, + * and the insn will not be entered into the FQ. + * + * In QEMU, we do not model the fp_exception_pending state and + * instead populate FQ and raise the exception immediately. + * But we can still honor fp_exception state by noticing when + * the FQ is not empty. + */ + if (dc->fsr_qne) { + gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + return true; + } +#endif + return false; +} + +static bool gen_trap_if_nofpu_fpexception(DisasContext *dc) +{ + return gen_trap_ifnofpu(dc) || gen_trap_iffpexception(dc); } /* asi moves */ @@ -2643,7 +2676,7 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) { DisasCompare cmp; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } gen_fcompare(&cmp, a->cc, a->cond); @@ -4482,7 +4515,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) if (addr == NULL) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (sz == MO_128 && gen_trap_float128(dc)) { @@ -4510,6 +4543,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz) if (addr == NULL) { return false; } + /* Store insns are ok in fp_exception_pending state. */ if (gen_trap_ifnofpu(dc)) { return true; } @@ -4574,7 +4608,7 @@ static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) if (addr == NULL) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4598,7 +4632,7 @@ static bool do_ldxfsr(DisasContext *dc, arg_r_r_ri *a, bool entire) if (addr == NULL) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4635,6 +4669,7 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) if (addr == NULL) { return false; } + /* Store insns are ok in fp_exception_pending state. */ if (gen_trap_ifnofpu(dc)) { return true; } @@ -4677,7 +4712,7 @@ static bool do_ff(DisasContext *dc, arg_r_r *a, { TCGv_i32 tmp; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4718,7 +4753,7 @@ static bool do_env_ff(DisasContext *dc, arg_r_r *a, { TCGv_i32 tmp; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4738,7 +4773,7 @@ static bool do_env_fd(DisasContext *dc, arg_r_r *a, TCGv_i32 dst; TCGv_i64 src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4758,7 +4793,7 @@ static bool do_dd(DisasContext *dc, arg_r_r *a, { TCGv_i64 dst, src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4780,7 +4815,7 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, { TCGv_i64 dst, src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4820,7 +4855,7 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, TCGv_i64 dst; TCGv_i32 src; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -4863,7 +4898,7 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, { TCGv_i128 t; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4884,7 +4919,7 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, TCGv_i128 src; TCGv_i32 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4907,7 +4942,7 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, TCGv_i128 src; TCGv_i64 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4930,7 +4965,7 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, TCGv_i32 src; TCGv_i128 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -4953,10 +4988,7 @@ static bool do_env_qd(DisasContext *dc, arg_r_r *a, TCGv_i64 src; TCGv_i128 dst; - if (gen_trap_ifnofpu(dc)) { - return true; - } - if (gen_trap_float128(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5013,7 +5045,7 @@ static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, { TCGv_i32 src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5222,7 +5254,7 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, { TCGv_i64 dst, src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5246,7 +5278,7 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a) TCGv_i64 dst; TCGv_i32 src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (!(dc->def->features & CPU_FEATURE_FSMULD)) { @@ -5355,7 +5387,7 @@ static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, { TCGv_i128 src1, src2; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -5379,7 +5411,7 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) TCGv_i64 src1, src2; TCGv_i128 dst; - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) { @@ -5469,7 +5501,7 @@ static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e) if (avail_32(dc) && a->cc != 0) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5493,7 +5525,7 @@ static bool do_fcmpd(DisasContext *dc, arg_FCMPd *a, bool e) if (avail_32(dc) && a->cc != 0) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } @@ -5517,7 +5549,7 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) if (avail_32(dc) && a->cc != 0) { return false; } - if (gen_trap_ifnofpu(dc)) { + if (gen_trap_if_nofpu_fpexception(dc)) { return true; } if (gen_trap_float128(dc)) {