From patchwork Thu Aug 15 12:11:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 819819 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC60F179647 for ; Thu, 15 Aug 2024 12:12:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723723929; cv=none; b=pXSZqA4kLapikaZDlTqVWXQpzHQgI79L/MxwIlZn38Qo5jAFOTOkG3puGoJ00pJGX9Ap0hJEL4ZgeWD6QVTyBM1uEtaLKFc67XnNheRdljNRXKObT5s1nObICDLjzOo65gnBKbK1zxmJdTvMoC9N/u0eeUnGtY99jtVtesX2qmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723723929; c=relaxed/simple; bh=cwZh/t6PTsAHn+9WQxZBnLBvMyUdjRRDOwKT+TpDcdY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VBYV4YjOYajXOa1z91kASOuep4wZjZt1Cwy0oJaOGaguoIghHdx8Cs5qXwTOdOz5VExQYQo2uOKYiNZwuXcgMesfptzoQEhiCt+37XhbdrKQ4dpuceGAV9Q1/o+QaivmxeDRkDgwFCjwpoueH6L6QtWcfq3Zh4EKqQiH+tVbIeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=2rJq4wM5; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="2rJq4wM5" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-36d2a601c31so451047f8f.0 for ; Thu, 15 Aug 2024 05:12:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1723723925; x=1724328725; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KmzCGQhj8OJq5H6Rk1aaVdY9d2NxnBFrZh6OEVj8AIA=; b=2rJq4wM5sM5B8z5GCUyW0ho3HWC+XbhkZZ4DtvA3++cKCcpzz1Y3LMMgUarP2o5IrB uDeX/WTJNMPW9wLA7qL7VG0pEtu7mCvGtdqW7w99xu3wk1ngU+Cyem5wge7KEvreaEE7 6N8knl+x5Lfx0r1sXJNovK3n1d7iKk6UuoiNOaRBh5kkzR5goBxUn00Q0J62ElnEcczw cnR7K11cl+sHSrCwT1pXav2XUpgk2LN17UXk7oKeJYSoKlAeq9sgbtqyFLcFJ6tjBrgp NheaRB3S2jxEvZoom+roNn5Dh2orVeynAw4xxX5JI+7jBra197LbaODieeg507VRYGnz lAtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723723925; x=1724328725; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KmzCGQhj8OJq5H6Rk1aaVdY9d2NxnBFrZh6OEVj8AIA=; b=HU+dLi6czYQ7+yCJX3gwtBWimJZtYjtsVGDLFTP/wWWXaxz2q2m9K1aI0F+jqdL9xm vB651ZhA//qyRMSRwFFQt6czcF7h4MpirbpmDYrw9VmGtBSFUooZS2ntXw29qOshj3Rv /mm1PPd5TS7bEB1j0KHrhGeT63n82yXrTo46HDglkSIPH2SMw7fQZ5YQLC1dC7B/wNIH XnSYhXMOXlHQfcsUtixPkWkmOvgGU9J77gHD8YSnO+sM8wBpzevTYIgGHoFzboEJnWtx aQhX4RsHI5jHnlG9Ut0DsHyQo0CGXace7sJgnFitDnLMTPju4VhwtW3XILOSsABJsYvj J8mQ== X-Forwarded-Encrypted: i=1; AJvYcCWBzRXa07VitGHcZ6cd9OwKEqrl95eAWiad55ogAJt5BvaDAZ5FakNKVF/HzTVxcXGCdBsZzs3oRGe1wIiqJWmKDs+zmDFf8HFBTVk= X-Gm-Message-State: AOJu0YyfD9aUo2XPWIFenySILXSaZaAWxOfD5kdj4pIqxUTIFF2ViekA /Cq1LT5/ioag69+xYBvhS+FOOdvtZs4HF3a53jMLy8Z9wNQFidQAiQxAOsZWcHM= X-Google-Smtp-Source: AGHT+IEbGIOFR16Gu1KgKoWgRq+sOlXFPXD2d0oLOy3ZdnJRcNKoYTkm5RRFB1N8wm740uDm1DeA3A== X-Received: by 2002:a05:6000:10f:b0:368:d0d:a5d6 with SMTP id ffacd0b85a97d-371777e47edmr3608074f8f.50.1723723924673; Thu, 15 Aug 2024 05:12:04 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:04 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:11:55 +0000 Subject: [PATCH 1/8] dt-bindings: iio: adc: ad7606: Make corrections on spi conditions Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-1-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=1468; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=cwZh/t6PTsAHn+9WQxZBnLBvMyUdjRRDOwKT+TpDcdY=; b=yeCoKWpDjHevYEwDjsK5Y8EdnkRjt/hXioQekXkONYv+DWh369A26wYcTT/cqxJ6KW3yqxkhx mnpuXzTpNJ4CWLNMlSg8mhrnwJpOGn1sr0vHvJbQj85Pyqe/Hu/EFEo X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The SPI conditions are not always required, because there is also a parallel interface. The way used to detect that the SPI interface is used is to check if the reg value is between 0 and 256. There is also a correction on the spi-cpha that is not required when SPI interface is selected, while spi-cpol is. Signed-off-by: Guillaume Stols --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 69408cae3db9..c0008d36320f 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -117,15 +117,26 @@ properties: required: - compatible - reg - - spi-cpha - avcc-supply - vdrive-supply - interrupts - adi,conversion-start-gpios -allOf: - - $ref: /schemas/spi/spi-peripheral-props.yaml# +# This checks if reg is a chipselect so the device is on an SPI +# bus, the if-clause will fail if reg is a tuple such as for a +# platform device. +if: + properties: + reg: + minimum: 0 + maximum: 256 +then: + allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - required: + - spi-cpol +allOf: - if: properties: compatible: From patchwork Thu Aug 15 12:11:56 2024 Content-Type: text/plain; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:05 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:11:56 +0000 Subject: [PATCH 2/8] dt-bindings: iio: adc: ad7606: Add iio backend bindings Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-2-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=3779; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=rXhZdUWJsqDazB5Vkbf8w2K7TEhns08C2q9VAY7oRJ8=; b=HPwEMFBxPMurmX27U87sY6QHKVNxGxR1eZ9Vd9WXBPxs9E9Zy3T97AKPeqbeZKiZbNK8VxrxE PeQ+5wj6O3GCZwcklTVKBAlaPuTPu2KCjnRLXLXzbln0dnP6I24b/Vm X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Add the required properties for iio-backend support, as well as an example and the conditions to mutually exclude interruption and conversion trigger with iio-backend. The iio-backend's function is to controls the communication, and thus the interruption pin won't be available anymore. As a consequence, the conversion pin must be controlled externally since we will miss information about when every single conversion cycle (i.e conversion + data transfert) ends, hence a PWM is introduced to trigger the conversions. Signed-off-by: Guillaume Stols --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 75 +++++++++++++++++++++- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index c0008d36320f..4b324f7e3207 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -114,13 +114,28 @@ properties: assumed that the pins are hardwired to VDD. type: boolean + pwms: + description: + In case the conversion is triggered by a PWM instead of a GPIO plugged to + the CONVST pin, the PWM must be referenced. + minItems: 1 + maxItems: 2 + + pwm-names: + minItems: 1 + maxItems: 2 + + io-backends: + description: + A reference to the iio-backend, which is responsible handling the BUSY + pin's falling edge and communication. + An example of backend can be found at + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html + required: - compatible - - reg - avcc-supply - vdrive-supply - - interrupts - - adi,conversion-start-gpios # This checks if reg is a chipselect so the device is on an SPI # bus, the if-clause will fail if reg is a tuple such as for a @@ -137,6 +152,35 @@ then: - spi-cpol allOf: + # Communication is handled either by the backend or an interrupt. + - if: + properties: + pwms: false + then: + required: + - adi,conversion-start-gpios + + - if: + properties: + adi,conversion-start-gpios: false + then: + required: + - pwms + + - if: + properties: + interrupts: false + then: + required: + - io-backends + + - if: + properties: + io-backends: false + then: + required: + - interrupts + - if: properties: compatible: @@ -178,12 +222,37 @@ allOf: adi,sw-mode: false else: properties: + pwms: + maxItems: 1 + pwm-names: + maxItems: 1 adi,conversion-start-gpios: maxItems: 1 unevaluatedProperties: false examples: + - | + #include + / { + adi_adc { + compatible = "adi,ad7606b"; + + pwms = <&axi_pwm_gen 0 0>; + + avcc-supply = <&adc_vref>; + vdrive-supply = <&vdd_supply>; + + reset-gpios = <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios = <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends = <&iio_backend>; + }; + }; + - | #include #include From patchwork Thu Aug 15 12:11:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 819580 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8454217AE1E for ; Thu, 15 Aug 2024 12:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:05 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:11:57 +0000 Subject: [PATCH 3/8] Documentation: iio: Document ad7606 driver Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-3-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=5859; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=T+/8clE2TUaqmdcnvPJh5S/25cCAbqiTNGruqzSK9iw=; b=wzKQoSPu+VfAa+wJRFs+HI3IfaOTPHX7nl+/FKEC2IQpmjyEodlyayl1On3onh7ctSvvTaSuR YLrYomCS9lHBQ7qTdpwPhvpgikWsXwVmdnXzyrWUXBGAEkewLr1utU/ X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= The Analog Devices Inc. AD7606 (and similar chips) are complex ADCs that will benefit from a detailed driver documentation. This documents the current features supported by the driver. Signed-off-by: Guillaume Stols --- Documentation/iio/ad7606.rst | 142 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/Documentation/iio/ad7606.rst b/Documentation/iio/ad7606.rst new file mode 100644 index 000000000000..e9578399e80d --- /dev/null +++ b/Documentation/iio/ad7606.rst @@ -0,0 +1,142 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD7606 driver +============= + +ADC driver for Analog Devices Inc. AD7606 and similar devices. The module name +is ``ad7606``. + +Supported devices +================= + +The following chips are supported by this driver: + +* `AD7605 `_ +* `AD7606 `_ +* `AD7606B `_ +* `AD7616 `_ + +Supported features +================== + +SPI wiring modes +---------------- + +ad7606x ADCs can output data on several SDO lines (1/2/4/8). The driver +currently supports only 1 SDO line. + +Parallel wiring mode +-------------------- + +AD7606x ADC have also a parallel interface, with 16 lines (that can be reduced +to 8 in byte mode). The parallel interface is selected by declaring the device +as platform in the device tree (with no io-backends node defined, see below). + +IIO-backend mode +---------------- + +This mode allows to reach the best sample rates, but it requires an external +hardware (eg HDL or APU) to handle the low level communication. +The backend mode is enabled when trough the definition of the "io-backends" +property in the device tree. +The reference configuration for the current implementation of IIO-backend mode +is the HDL reference provided by ADI: +https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl +This implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM +connected to the conversion trigger pin. + ++---+ +---------------------------- +| | +-------+ |AD76xx +| A | controls | | | +| D |-------------->| PWM |-------------->| cnvst +| 7 | | | | +| 6 | +-------+ | +| 0 | controls +-----------+------------ | +| 6 |---------->| | |<--| frstdata +| | | Backend | Backend |<--| busy +| D | | Driver | | | +| R | | | |-->| clk +| I | requests |+---------+| DMA | | +| V |----------->| Buffer ||<---- |<=>| DATA +| E | |+---------+| | | +| R | +-----------+-----------+ | +| |-------------------------------------->| reset/configuration gpios ++---+ +----------------------------- + + +Software and hardware modes +--------------------------- + +While all the AD7606 series parts can be configured using GPIOs, some of them +can be configured using register. +The chip that support software mode have more values avalaible for configuring +the device, as well as more settings, and allow to control the range and +calibration per channel. +The following settings are available per channel in software mode: + - Scale +Also, there is a broader choice of oversampling ratios in software mode. + +Conversion triggering +--------------------- + +The conversion can be triggered by two distinct ways: + + - A GPIO is connected to the conversion trigger pin, and this GPIO is controlled + by the driver directly. In this configuration, the driver set back the + conversion trigger pin to high as soon as it has read all the conversions. + + - An external source is connected to the conversion trigger pin. In the + current implementation, it must be a PWM. In this configuration, the driver + does not control directly the conversion trigger pin. Instead, it can + control the PWM's frequency. This trigger is enabled only for iio-backend. + +Reference voltage +----------------- + +2 possible reference voltage sources are supported: + + - Internal reference (2.5V) + - External reference (2.5V) + +The source is determined by the device tree. If ``refin-supply`` is present, +then the external reference is used, else the internal reference is used. + +Oversampling +------------ + +This family supports oversampling to improve SNR. +In software mode, the following ratios are available: +1 (oversampling disabled)/2/4/8/16/32/64/128/256. + +Unimplemented features +---------------------- + +- 2/4/8 SDO lines +- CRC indication +- Calibration + +Device buffers +============== + +IIO triggered buffer +-------------------- + +This driver supports IIO triggered buffers, with a "built in" trigger, i.e the +trigger is allocated and linked by the driver, and a new conversion is triggered +as soon as the samples are transferred, and a timestamp channel is added to make +up for the potential jitter induced by the delays in the interrupt handling. + +IIO backend buffer +------------------ + +When IIO backend is used, the trigger is not needed, and the sample rate is +considered as stable, hence there is no timestamp channel. The communication is +delegated to an external logic, called a backend, and the backend's driver +handles the buffer. When this mode is enabled, the driver cannot control the +conversion pin, because the busy pin is bound to the backend. + + + + + From patchwork Thu Aug 15 12:11:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Stols X-Patchwork-Id: 819817 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D47317BEB4 for ; Thu, 15 Aug 2024 12:12:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723723932; cv=none; b=epa/d5PehkKpMCUSTG/dYyAI8UhvkSQpB2/5hXrLJem+g8z10hB7j8Jj5R/mWI2zmhjmyibKl1CfNpytM2Wy4rHcznbVdznEPAsFiyQ0yZsTuIhZf+9ztw4U2QU0WPPgCEgWn2BztDc9yvy/NBX2i8d1/MJBw1yxRTOlAjRlDzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723723932; c=relaxed/simple; bh=B299RubzcyeAZYqSINS1JMw78PJqVT8lqVWbm+KhLHQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hjSCLHn3vpLr/yT8LeeVYYEkHOXwl7n6GOEpB2/TaTPe6ntyIdwbCedn9askS+3M4bvBJOFiJjqYAxvN/NNtritWEBQJ9iGC/lnLHYthMVrOI0U8E5I0PX4wnX3MbCf1NJ3mWsWuqKrjeU1EumTNt92yiS+2kZZPMCiOIygr4NA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ZEmvrITb; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ZEmvrITb" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4280c55e488so4341555e9.0 for ; Thu, 15 Aug 2024 05:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1723723927; x=1724328727; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aIfifid+gNmxqdjRD2+a9HhTRK2zF1nl/3in+BtGhPo=; b=ZEmvrITbVbmkcj5jQFb/DuAQwP1GSlJcJyhT1Fo9l4OWrmQsUIA0CmstuSK+C4nn4e +maA6XI7ioCWHKIng9ypRFOTs3scA6NFtiQEyI0EVF/cRoVxaRzgbBgVrcw7DaDS4jN9 WakjrUmtwTS8NC/it8wu2LI5mD6OYwLVtNNV9mevmY9sbrKhxARZU1EjahEuGFluMbKP t6xqHFCqUiReiLzDXOvfTLOAgXmoXEw7VRRKggIhGkJQ0M7UJi2vTLSwXXcIgjy9H1Dl yvxRVv7Qex+W37iTWCuWu/PAxmZ4FdoU3dM5U1nGsNAkckTVLbK/UAMsFRPzqvdsRB1+ Zz8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723723927; x=1724328727; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aIfifid+gNmxqdjRD2+a9HhTRK2zF1nl/3in+BtGhPo=; b=xJx59EdD2Zi0WOCwbyKxD+IwRxODIL165+IpiS74XWGqRaKOD7SXmJmvmcg9uaAcrt qGNYxntCqdlj9WRSekTxuzJzyLaPCD4lcLWNzqcVJxiqrpWwf+RD7vwiQ0D73869khCb U5dpteqoMhSbjibEmP4HvXpws8GKcgkJg7bLLFhQdumKysCfgPOsAGB4aaRwEzRMUFMy nVnU4jsYLY7/nCRq2lSi1K85p63tm6WP/bi3Hwn8QjTr04YwxD5lY1szSKcsbfmOw0hD Xa3I0RnrzzlPaOSBeCHahRe/WtgHCAmQMzCBe+PrsXDQ53FSnHStu742cZOSatLazclc KqNw== X-Forwarded-Encrypted: i=1; AJvYcCWIfiLdSoCO10egrQ+iSk0UNcKkqYoBEMluSEtBLxQ/hLuvwwV4dSXI2TpeU8XhkatKcZTFUjD6eakX6GRxInB4jYLsw6ejygLAadM= X-Gm-Message-State: AOJu0Yz+8zcoQh4mxXnWNLLMB73/yGPGHP2rRB4kTkJcLfmP3yZ9YMr1 1qtRH/QlSnSBTwYW7I8/jWQWu6PbBUY4H3ZgfLKTDvzjBMX3BGf2jsHDjDAt5kQ= X-Google-Smtp-Source: AGHT+IEuybZDakhKeQ5LH52V3RpeDuVw/uxz9FrF2X2Ngvg5W3lc4Fx9NnyZt1280p66tj9dqkB9jg== X-Received: by 2002:a05:600c:348b:b0:424:8be4:f2c with SMTP id 5b1f17b1804b1-429e231f76dmr18552725e9.2.1723723927027; Thu, 15 Aug 2024 05:12:07 -0700 (PDT) Received: from [127.0.1.1] (frhb82016ds.ikexpress.com. [185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:06 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:11:58 +0000 Subject: [PATCH 4/8] pwm: Export pwm_get_state_hw Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-4-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=1631; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=B299RubzcyeAZYqSINS1JMw78PJqVT8lqVWbm+KhLHQ=; b=R0SYVR5ABChT/agrkOGtqE560UOP8iseJdjHPPNT794iaKR5TkwlROnIsf6vbGNXL+qEbca08 3vR+WhJM5zGB++xcBB8es5v4vgNmrPQDw8zW1fS8VOXM6g+CfvJksiB X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= This function can be used in some other drivers, for instance when we want to retrieve the real frequency vs the one that was asked. Signed-off-by: Guillaume Stols --- drivers/pwm/core.c | 3 ++- include/linux/pwm.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 21fca27bb8a3..82e05ed88310 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -651,7 +651,7 @@ int pwm_apply_atomic(struct pwm_device *pwm, const struct pwm_state *state) } EXPORT_SYMBOL_GPL(pwm_apply_atomic); -static int pwm_get_state_hw(struct pwm_device *pwm, struct pwm_state *state) +int pwm_get_state_hw(struct pwm_device *pwm, struct pwm_state *state) { struct pwm_chip *chip = pwm->chip; const struct pwm_ops *ops = chip->ops; @@ -685,6 +685,7 @@ static int pwm_get_state_hw(struct pwm_device *pwm, struct pwm_state *state) return ret; } +EXPORT_SYMBOL_GPL(pwm_get_state_hw); /** * pwm_adjust_config() - adjust the current PWM config to the PWM arguments diff --git a/include/linux/pwm.h b/include/linux/pwm.h index fd100c27f109..d48ea3051e28 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -369,6 +369,7 @@ int pwm_apply_might_sleep(struct pwm_device *pwm, const struct pwm_state *state) int pwm_apply_atomic(struct pwm_device *pwm, const struct pwm_state *state); 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:07 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:11:59 +0000 Subject: [PATCH 5/8] platform: add platform_get_device_match_data() helper Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-5-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=1781; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=NbKx0MzTSy4AkOnvlPHkNNwV65/pkwG9IF0PJXDZUNw=; b=VOYJGuD/1ccizW8foihyuYIcvcsufWDfHQhMJgly8oXiPmQELygHZcqqg/NPsa767PekcfJOM vx/cis54SwFDlOLGtkc07Yo/YSNxVhQeNHA7o9alToZqiRWmpOqxr9/ X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Inspired from spi_get_device_match_data() helper: if OF or ACPI driver data is available, platform_get_device_id will return NULL because platform_match_id is not called, and pdev->id_entry is never populated. This helper function checks if match data is available, and otherwise returns the ID table data. Signed-off-by: Guillaume Stols --- drivers/base/platform.c | 12 ++++++++++++ include/linux/platform_device.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 4c3ee6521ba5..26e9a026eb05 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -1090,6 +1090,18 @@ static const struct platform_device_id *platform_match_id( return NULL; } +const void *platform_get_device_match_data(const struct platform_device *pdev) +{ + const struct platform_device_id *match; + + match = device_get_match_data(&pdev->dev); + if (match) + return match; + + return (const void *)platform_get_device_id(pdev)->driver_data; +} +EXPORT_SYMBOL_GPL(platform_get_device_match_data); + #ifdef CONFIG_PM_SLEEP static int platform_legacy_suspend(struct device *dev, pm_message_t mesg) diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index d422db6eec63..e2cc09ecc447 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -45,6 +45,7 @@ struct platform_device { }; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:08 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:12:00 +0000 Subject: [PATCH 6/8] iio: adc: ad7606: Add PWM support for conversion trigger Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-6-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=9222; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=JiY1QWQ/CFROpK9K5j1ChfJ3QqmS9Qz+FrZxBwt17/E=; b=eVkvSg4+8MrEnNbhPKJTAD6OHIQxQobdWOOey4+hytnUCICX7iLYZOARZXlC2b2YgUcrFkai1 VoA3QLhdWYGCRiMnsCxq0hQnAFjEaVCsUIFwW/rRDryG5WrRJyYhBah X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= Until now, the conversion were triggered by setting high the GPIO connected to the convst pin. This commit gives the possibility to connect the convst pin to a PWM. Connecting a PWM allows to have a better control on the samplerate, but it must be handled with care, as it is completely decorrelated of the driver's busy pin handling. Hence it is not recommended to be used "as is" but must be exploited in conjonction with IIO backend, and for now only a sampling frequency of 2 kHz is available. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 162 +++++++++++++++++++++++++++++++++++++++-------- drivers/iio/adc/ad7606.h | 3 + 2 files changed, 140 insertions(+), 25 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 539e4a8621fe..2c9ddcd0ad77 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -13,11 +13,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include @@ -82,6 +84,76 @@ static int ad7606_reg_access(struct iio_dev *indio_dev, } } +static int ad7606_pwm_set_high(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return -EINVAL; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + +static int ad7606_pwm_set_low(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return -EINVAL; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = 0; + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + +static int ad7606_pwm_set_swing(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return -EINVAL; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + cnvst_pwm_state.enabled = true; + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + +static bool ad7606_pwm_is_swinging(struct ad7606_state *st) +{ + struct pwm_state cnvst_pwm_state; + + if (!st->cnvst_pwm) + return false; + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period && + cnvst_pwm_state.duty_cycle != 0; +} + +static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) +{ + struct pwm_state cnvst_pwm_state; + bool is_swinging = ad7606_pwm_is_swinging(st); + bool is_high; + + if (freq == 0) + return -EINVAL; + + /*Retrieve the previous state */ + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period; + + cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); + cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL; + if (is_high) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; + else if (is_swinging) + cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; + + return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); +} + static int ad7606_read_samples(struct ad7606_state *st) { unsigned int num = st->chip_info->num_channels - 1; @@ -141,9 +213,21 @@ static irqreturn_t ad7606_trigger_handler(int irq, void *p) static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch) { struct ad7606_state *st = iio_priv(indio_dev); + struct pwm_state cnvst_pwm_state; int ret; + bool pwm_swings = false; - gpiod_set_value(st->gpio_convst, 1); + if (st->gpio_convst) { + gpiod_set_value(st->gpio_convst, 1); + } else { + pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); + /* Keep the current PWM state to switch it back off if needed*/ + if (ad7606_pwm_is_swinging(st)) + pwm_swings = true; + ret = ad7606_pwm_set_high(st); + if (!ret) + return ret; + } ret = wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000)); if (!ret) { @@ -154,7 +238,12 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch) ret = ad7606_read_samples(st); if (ret == 0) ret = st->data[ch]; - + if (!st->gpio_convst) { + if (!pwm_swings) + ret = ad7606_pwm_set_low(st); + else + ret = ad7606_pwm_set_swing(st); + } error_ret: gpiod_set_value(st->gpio_convst, 0); @@ -169,6 +258,7 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, { int ret, ch = 0; struct ad7606_state *st = iio_priv(indio_dev); + struct pwm_state cnvst_pwm_state; switch (m) { case IIO_CHAN_INFO_RAW: @@ -419,8 +509,9 @@ static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; - st->gpio_convst = devm_gpiod_get(dev, "adi,conversion-start", - GPIOD_OUT_LOW); + st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_convst)) return PTR_ERR(st->gpio_convst); @@ -489,6 +580,7 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 1); + ad7606_pwm_set_swing(st); return 0; } @@ -498,6 +590,7 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 0); + ad7606_pwm_set_low(st); return 0; } @@ -545,6 +638,11 @@ static const struct iio_trigger_ops ad7606_trigger_ops = { .validate_device = iio_trigger_validate_own_device, }; +static void ad7606_pwm_disable(void *data) +{ + pwm_disable(data); +} + int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, const char *name, unsigned int id, const struct ad7606_bus_ops *bops) @@ -635,20 +733,42 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, return ret; } - st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", - indio_dev->name, - iio_device_id(indio_dev)); - if (!st->trig) - return -ENOMEM; - - st->trig->ops = &ad7606_trigger_ops; - iio_trigger_set_drvdata(st->trig, indio_dev); - ret = devm_iio_trigger_register(dev, st->trig); - if (ret) - return ret; - - indio_dev->trig = iio_trigger_get(st->trig); + /* If convst pin is not defined, setup PWM*/ + if (!st->gpio_convst) { + st->cnvst_pwm = devm_pwm_get(dev, NULL); + if (IS_ERR(st->cnvst_pwm)) + return PTR_ERR(st->cnvst_pwm); + ret = devm_add_action_or_reset(dev, ad7606_pwm_disable, + st->cnvst_pwm); + if (ret) + return ret; + /* + * Set the sampling rate to 2 kHz so to be sure that the interruption can be + * handled between within a single pulse. + */ + ret = ad7606_set_sampling_freq(st, 2 * KILO); + if (ret) + return ret; + } else { + st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + st->trig->ops = &ad7606_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret = devm_iio_trigger_register(dev, st->trig); + if (ret) + return ret; + indio_dev->trig = iio_trigger_get(st->trig); + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad7606_trigger_handler, + &ad7606_buffer_ops); + if (ret) + return ret; + } ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt, @@ -657,13 +777,6 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; - ret = devm_iio_triggered_buffer_setup(dev, indio_dev, - &iio_pollfunc_store_time, - &ad7606_trigger_handler, - &ad7606_buffer_ops); - if (ret) - return ret; - return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, IIO_AD7606); @@ -693,7 +806,6 @@ static int ad7606_resume(struct device *dev) gpiod_set_value(st->gpio_standby, 1); ad7606_reset(st); } - return 0; } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 0c6a88cc4695..60bac1894a91 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -38,6 +38,8 @@ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\ 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) +struct pwm_device *cnvst_pwm; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:09 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:12:01 +0000 Subject: [PATCH 7/8] iio: adc: ad7606: Switch to xxx_get_device_match_data Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-7-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=13866; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=mzJbwcOvbairLbN592J/ttZQ0Yv4RcpSamoG1D3d/tg=; b=xBft+6Y3H404nyXMc+9qiyy0VX26Tz2lw9fFxb8SAzrb802pcLqiky4+HcixpfwElNXeH+39M GY4H62Cj8dvBEjXc4c1Sk2hm+TX1+vH5Z9S4S+T6pnaBWU+FUcSlL7u X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= On the parallel version, the current implementation is only compatible with id tables and won't work with fx_nodes. So in this commit, the goal is to switch to use get_device_match_data, in order to simplify the logic of retrieving chip data. Also, chip info is moved in the .h file so to be accessible to all the driver files that can set a pointer to the corresponding chip as the driver data. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 106 ++-------------------------------- drivers/iio/adc/ad7606.h | 132 ++++++++++++++++++++++++++++++++++++++++--- drivers/iio/adc/ad7606_par.c | 22 ++++---- drivers/iio/adc/ad7606_spi.c | 31 +++++----- 4 files changed, 154 insertions(+), 137 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 2c9ddcd0ad77..99d5ca5c2348 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -43,14 +43,6 @@ static const unsigned int ad7616_sw_scale_avail[3] = { 76293, 152588, 305176 }; -static const unsigned int ad7606_oversampling_avail[7] = { - 1, 2, 4, 8, 16, 32, 64, -}; - -static const unsigned int ad7616_oversampling_avail[8] = { - 1, 2, 4, 8, 16, 32, 64, 128, -}; - static int ad7606_reset(struct ad7606_state *st) { if (st->gpio_reset) { @@ -415,96 +407,6 @@ static const struct attribute_group ad7606_attribute_group_range = { .attrs = ad7606_attributes_range, }; -static const struct iio_chan_spec ad7605_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(4), - AD7605_CHANNEL(0), - AD7605_CHANNEL(1), - AD7605_CHANNEL(2), - AD7605_CHANNEL(3), -}; - -static const struct iio_chan_spec ad7606_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(8), - AD7606_CHANNEL(0), - AD7606_CHANNEL(1), - AD7606_CHANNEL(2), - AD7606_CHANNEL(3), - AD7606_CHANNEL(4), - AD7606_CHANNEL(5), - AD7606_CHANNEL(6), - AD7606_CHANNEL(7), -}; - -/* - * The current assumption that this driver makes for AD7616, is that it's - * working in Hardware Mode with Serial, Burst and Sequencer modes activated. - * To activate them, following pins must be pulled high: - * -SER/PAR - * -SEQEN - * And following pins must be pulled low: - * -WR/BURST - * -DB4/SER1W - */ -static const struct iio_chan_spec ad7616_channels[] = { - IIO_CHAN_SOFT_TIMESTAMP(16), - AD7606_CHANNEL(0), - AD7606_CHANNEL(1), - AD7606_CHANNEL(2), - AD7606_CHANNEL(3), - AD7606_CHANNEL(4), - AD7606_CHANNEL(5), - AD7606_CHANNEL(6), - AD7606_CHANNEL(7), - AD7606_CHANNEL(8), - AD7606_CHANNEL(9), - AD7606_CHANNEL(10), - AD7606_CHANNEL(11), - AD7606_CHANNEL(12), - AD7606_CHANNEL(13), - AD7606_CHANNEL(14), - AD7606_CHANNEL(15), -}; - -static const struct ad7606_chip_info ad7606_chip_info_tbl[] = { - /* More devices added in future */ - [ID_AD7605_4] = { - .channels = ad7605_channels, - .num_channels = 5, - }, - [ID_AD7606_8] = { - .channels = ad7606_channels, - .num_channels = 9, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606_6] = { - .channels = ad7606_channels, - .num_channels = 7, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606_4] = { - .channels = ad7606_channels, - .num_channels = 5, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7606B] = { - .channels = ad7606_channels, - .num_channels = 9, - .oversampling_avail = ad7606_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), - }, - [ID_AD7616] = { - .channels = ad7616_channels, - .num_channels = 17, - .oversampling_avail = ad7616_oversampling_avail, - .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), - .os_req_reset = true, - .init_delay_ms = 15, - }, -}; - static int ad7606_request_gpios(struct ad7606_state *st) { struct device *dev = st->dev; @@ -644,7 +546,7 @@ static void ad7606_pwm_disable(void *data) } int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, - const char *name, unsigned int id, + const struct ad7606_chip_info *chip_info, const struct ad7606_bus_ops *bops) { struct ad7606_state *st; @@ -673,7 +575,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, return dev_err_probe(dev, ret, "Failed to enable specified AVcc supply\n"); - st->chip_info = &ad7606_chip_info_tbl[id]; + st->chip_info = chip_info; if (st->chip_info->oversampling_num) { st->oversampling_avail = st->chip_info->oversampling_avail; @@ -696,7 +598,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->info = &ad7606_info_no_os_or_range; } indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->name = name; + indio_dev->name = chip_info->name; indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; @@ -773,7 +675,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, NULL, &ad7606_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - name, indio_dev); + chip_info->name, indio_dev); if (ret) return ret; diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 60bac1894a91..aab8fefb84be 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,8 +40,19 @@ struct pwm_device *cnvst_pwm; +enum ad7606_supported_device_ids { + ID_AD7605_4, + ID_AD7606_8, + ID_AD7606_6, + ID_AD7606_4, + ID_AD7606B, + ID_AD7616, +}; + /** * struct ad7606_chip_info - chip specific information + * @name device name + * @id device id * @channels: channel specification * @num_channels: number of channels * @oversampling_avail pointer to the array which stores the available @@ -52,6 +63,8 @@ struct pwm_device *cnvst_pwm; * after a restart */ struct ad7606_chip_info { + enum ad7606_supported_device_ids id; + const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; const unsigned int *oversampling_avail; @@ -151,16 +164,119 @@ struct ad7606_bus_ops { }; int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, - const char *name, unsigned int id, + const struct ad7606_chip_info *info, const struct ad7606_bus_ops *bops); -enum ad7606_supported_device_ids { - ID_AD7605_4, - ID_AD7606_8, - ID_AD7606_6, - ID_AD7606_4, - ID_AD7606B, - ID_AD7616, +static const unsigned int ad7606_oversampling_avail[7] = { + 1, 2, 4, 8, 16, 32, 64, +}; + +static const unsigned int ad7616_oversampling_avail[8] = { + 1, 2, 4, 8, 16, 32, 64, 128, +}; + +static const struct iio_chan_spec ad7605_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(4), + AD7605_CHANNEL(0), + AD7605_CHANNEL(1), + AD7605_CHANNEL(2), + AD7605_CHANNEL(3), +}; + +static const struct iio_chan_spec ad7606_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(8), + AD7606_CHANNEL(0), + AD7606_CHANNEL(1), + AD7606_CHANNEL(2), + AD7606_CHANNEL(3), + AD7606_CHANNEL(4), + AD7606_CHANNEL(5), + AD7606_CHANNEL(6), + AD7606_CHANNEL(7), +}; + +/* + * The current assumption that this driver makes for AD7616, is that it's + * working in Hardware Mode with Serial, Burst and Sequencer modes activated. + * To activate them, following pins must be pulled high: + * -SER/PAR + * -SEQEN + * And following pins must be pulled low: + * -WR/BURST + * -DB4/SER1W + */ +static const struct iio_chan_spec ad7616_channels[] = { + IIO_CHAN_SOFT_TIMESTAMP(16), + AD7606_CHANNEL(0), + AD7606_CHANNEL(1), + AD7606_CHANNEL(2), + AD7606_CHANNEL(3), + AD7606_CHANNEL(4), + AD7606_CHANNEL(5), + AD7606_CHANNEL(6), + AD7606_CHANNEL(7), + AD7606_CHANNEL(8), + AD7606_CHANNEL(9), + AD7606_CHANNEL(10), + AD7606_CHANNEL(11), + AD7606_CHANNEL(12), + AD7606_CHANNEL(13), + AD7606_CHANNEL(14), + AD7606_CHANNEL(15), +}; + +static const struct ad7606_chip_info ad7605_4_info = { + .channels = ad7605_channels, + .num_channels = 5, + .name = "ad7605-4", + .id = ID_AD7605_4, +}; + +static const struct ad7606_chip_info ad7606_8_info = { + .channels = ad7606_channels, + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606-8", + .id = ID_AD7606_8, +}; + +static const struct ad7606_chip_info ad7606_6_info = { + .channels = ad7606_channels, + .num_channels = 7, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606-6", + .id = ID_AD7606_6, +}; + +static const struct ad7606_chip_info ad7606_4_info = { + .channels = ad7606_channels, + .num_channels = 5, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606-4", + .id = ID_AD7606_4, +}; + +static const struct ad7606_chip_info ad7606b_info = { + .channels = ad7606_channels, + .num_channels = 9, + .oversampling_avail = ad7606_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .name = "ad7606B", + .id = ID_AD7606B, +}; + +static const struct ad7606_chip_info ad7616_info = { + .channels = ad7616_channels, + .num_channels = 17, + .oversampling_avail = ad7616_oversampling_avail, + .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), + .os_req_reset = true, + .init_delay_ms = 15, + .name = "ad7616", + .id = ID_AD7616, }; #ifdef CONFIG_PM_SLEEP diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index d8408052262e..d83c0edc1e31 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -47,7 +47,7 @@ static const struct ad7606_bus_ops ad7606_par8_bops = { static int ad7606_par_probe(struct platform_device *pdev) { - const struct platform_device_id *id = platform_get_device_id(pdev); + const struct ad7606_chip_info *chip_info = platform_get_device_match_data(pdev); struct resource *res; void __iomem *addr; resource_size_t remap_size; @@ -64,26 +64,26 @@ static int ad7606_par_probe(struct platform_device *pdev) remap_size = resource_size(res); return ad7606_probe(&pdev->dev, irq, addr, - id->name, id->driver_data, + chip_info, remap_size > 1 ? &ad7606_par16_bops : &ad7606_par8_bops); } static const struct platform_device_id ad7606_driver_ids[] = { - { .name = "ad7605-4", .driver_data = ID_AD7605_4, }, - { .name = "ad7606-4", .driver_data = ID_AD7606_4, }, - { .name = "ad7606-6", .driver_data = ID_AD7606_6, }, - { .name = "ad7606-8", .driver_data = ID_AD7606_8, }, + { .name = "ad7605-4", .driver_data = (kernel_ulong_t)&ad7605_4_info, }, + { .name = "ad7606-4", .driver_data = (kernel_ulong_t)&ad7606_4_info, }, + { .name = "ad7606-6", .driver_data = (kernel_ulong_t)&ad7606_6_info, }, + { .name = "ad7606-8", .driver_data = (kernel_ulong_t)&ad7606_8_info, }, { } }; MODULE_DEVICE_TABLE(platform, ad7606_driver_ids); static const struct of_device_id ad7606_of_match[] = { - { .compatible = "adi,ad7605-4" }, - { .compatible = "adi,ad7606-4" }, - { .compatible = "adi,ad7606-6" }, - { .compatible = "adi,ad7606-8" }, - { }, + { .compatible = "adi,ad7605-4", .data = &ad7605_4_info }, + { .compatible = "adi,ad7606-4", .data = &ad7606_4_info }, + { .compatible = "adi,ad7606-6", .data = &ad7606_6_info }, + { .compatible = "adi,ad7606-8", .data = &ad7606_8_info }, + { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index 287a0591533b..c23a7448f851 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -307,10 +307,10 @@ static const struct ad7606_bus_ops ad7606B_spi_bops = { static int ad7606_spi_probe(struct spi_device *spi) { - const struct spi_device_id *id = spi_get_device_id(spi); + const struct ad7606_chip_info *chip_info = spi_get_device_match_data(spi); const struct ad7606_bus_ops *bops; - switch (id->driver_data) { + switch (chip_info->id) { case ID_AD7616: bops = &ad7616_spi_bops; break; @@ -323,28 +323,27 @@ static int ad7606_spi_probe(struct spi_device *spi) } return ad7606_probe(&spi->dev, spi->irq, NULL, - id->name, id->driver_data, - bops); + chip_info, bops); } static const struct spi_device_id ad7606_id_table[] = { - { "ad7605-4", ID_AD7605_4 }, - { "ad7606-4", ID_AD7606_4 }, - { "ad7606-6", ID_AD7606_6 }, - { "ad7606-8", ID_AD7606_8 }, - { "ad7606b", ID_AD7606B }, - { "ad7616", ID_AD7616 }, + { "ad7605-4", (kernel_ulong_t)&ad7605_4_info }, + { "ad7606-4", (kernel_ulong_t)&ad7606_4_info }, + { "ad7606-6", (kernel_ulong_t)&ad7606_6_info }, + { "ad7606-8", (kernel_ulong_t)&ad7606_8_info }, + { "ad7606b", (kernel_ulong_t)&ad7606b_info }, + { "ad7616", (kernel_ulong_t)&ad7616_info }, {} }; MODULE_DEVICE_TABLE(spi, ad7606_id_table); static const struct of_device_id ad7606_of_match[] = { - { .compatible = "adi,ad7605-4" }, - { .compatible = "adi,ad7606-4" }, - { .compatible = "adi,ad7606-6" }, - { .compatible = "adi,ad7606-8" }, - { .compatible = "adi,ad7606b" }, - { .compatible = "adi,ad7616" }, + { .compatible = "adi,ad7605-4", &ad7605_4_info }, + { .compatible = "adi,ad7606-4", &ad7606_4_info }, + { .compatible = "adi,ad7606-6", &ad7606_6_info }, + { .compatible = "adi,ad7606-8", &ad7606_8_info }, + { .compatible = "adi,ad7606b", &ad7606b_info }, + { .compatible = "adi,ad7616", &ad7616_info }, { }, }; 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[185.246.87.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37189897926sm1365082f8f.87.2024.08.15.05.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:12:10 -0700 (PDT) From: Guillaume Stols Date: Thu, 15 Aug 2024 12:12:02 +0000 Subject: [PATCH 8/8] iio:adc:ad7606: Add iio-backend support Precedence: bulk X-Mailing-List: linux-fbdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240815-ad7606_add_iio_backend_support-v1-8-cea3e11b1aa4@baylibre.com> References: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> In-Reply-To: <20240815-ad7606_add_iio_backend_support-v1-0-cea3e11b1aa4@baylibre.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , "Rafael J. Wysocki" , Jonathan Corbet Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Guillaume Stols , 20240705211452.1157967-2-u.kleine-koenig@baylibre.com, 20240712171821.1470833-2-u.kleine-koenig@baylibre.com, cover.1721040875.git.u.kleine-koenig@baylibre.com, aardelean@baylibre.com X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723723923; l=15684; i=gstols@baylibre.com; s=20240417; h=from:subject:message-id; bh=Xa18CiY1WUs7s+G2+TH89jQYkhJjsmYHoYi+3712ovI=; b=46nOiiSOXC3/K9nBMdvsND8Zy8yMu9lqq6Ja91ejfGSnWokBMrCCsawpC+cPC8dALfvEHLB+i ET3fpMadIu9C9a+UZpcqVVB9+Ok3xG+d3z7Nwd5GmbPtKipY+3Zw+zk X-Developer-Key: i=gstols@baylibre.com; a=ed25519; pk=XvMm5WHuV67sGYOJZqIYzXndbaJOlNd8Q6li6vnb4Cs= - Basic support for iio backend. - Supports IIO_CHAN_INFO_SAMP_FREQ R/W. - Only hardware mode is available, and that IIO_CHAN_INFO_RAW is not supported if iio-backend mode is selected. A small correction was added to the driver's file name in the Kconfig file's description. Signed-off-by: Guillaume Stols --- drivers/iio/adc/Kconfig | 3 +- drivers/iio/adc/ad7606.c | 103 +++++++++++++++++++++++++++++++++++-------- drivers/iio/adc/ad7606.h | 16 +++++++ drivers/iio/adc/ad7606_par.c | 98 +++++++++++++++++++++++++++++++++++++++- 4 files changed, 200 insertions(+), 20 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 88e8ce2e78b3..01248b6df868 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -227,9 +227,10 @@ config AD7606_IFACE_PARALLEL help Say yes here to build parallel interface support for Analog Devices: ad7605-4, ad7606, ad7606-6, ad7606-4 analog to digital converters (ADC). + It also support iio_backended devices for AD7606B. To compile this driver as a module, choose M here: the - module will be called ad7606_parallel. + module will be called ad7606_par. config AD7606_IFACE_SPI tristate "Analog Devices AD7606 ADC driver with spi interface support" diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 99d5ca5c2348..a753d5caa9f8 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -148,7 +149,15 @@ static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) static int ad7606_read_samples(struct ad7606_state *st) { - unsigned int num = st->chip_info->num_channels - 1; + unsigned int num = st->chip_info->num_channels; + + /* + * Timestamp channel does not contain sample, and no timestamp channel if + * backend is used. + */ + if (!st->back) + num--; + u16 *data = st->data; int ret; @@ -220,11 +229,15 @@ static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch) if (!ret) return ret; } - ret = wait_for_completion_timeout(&st->completion, - msecs_to_jiffies(1000)); - if (!ret) { - ret = -ETIMEDOUT; - goto error_ret; + + /* backend manages interruptions by itself.*/ + if (!st->back) { + ret = wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(1000)); + if (!ret) { + ret = -ETIMEDOUT; + goto error_ret; + } } ret = ad7606_read_samples(st); @@ -271,6 +284,12 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *val = st->oversampling; return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + pwm_get_state_hw(st->cnvst_pwm, &cnvst_pwm_state); + /* If the PWM is swinging, return the real frequency, otherwise 0 */ + *val = ad7606_pwm_is_swinging(st) ? + DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period) : 0; + return IIO_VAL_INT; } return -EINVAL; } @@ -360,6 +379,8 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, return ret; return 0; + case IIO_CHAN_INFO_SAMP_FREQ: + return ad7606_set_sampling_freq(st, val); default: return -EINVAL; } @@ -482,7 +503,6 @@ static int ad7606_buffer_postenable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 1); - ad7606_pwm_set_swing(st); return 0; } @@ -492,19 +512,53 @@ static int ad7606_buffer_predisable(struct iio_dev *indio_dev) struct ad7606_state *st = iio_priv(indio_dev); gpiod_set_value(st->gpio_convst, 0); - ad7606_pwm_set_low(st); return 0; } +static int ad7606_pwm_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + return ad7606_pwm_set_swing(st); +} + +static int ad7606_pwm_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + return ad7606_pwm_set_low(st); +} + +static int ad7606_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + /* The update scan mode is only for iio backend compatible drivers. + * If the specific update_scan_mode is not defined in the bus ops, + * just do nothing and return 0. + */ + if (st->bops->update_scan_mode) + return st->bops->update_scan_mode(indio_dev, scan_mask); + else + return 0; +} + static const struct iio_buffer_setup_ops ad7606_buffer_ops = { .postenable = &ad7606_buffer_postenable, .predisable = &ad7606_buffer_predisable, }; +static const struct iio_buffer_setup_ops ad7606_pwm_buffer_ops = { + .postenable = &ad7606_pwm_buffer_postenable, + .predisable = &ad7606_pwm_buffer_predisable, +}; + static const struct iio_info ad7606_info_no_os_or_range = { .read_raw = &ad7606_read_raw, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os_and_range = { @@ -512,6 +566,7 @@ static const struct iio_info ad7606_info_os_and_range = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_os_and_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os_range_and_debug = { @@ -520,6 +575,7 @@ static const struct iio_info ad7606_info_os_range_and_debug = { .debugfs_reg_access = &ad7606_reg_access, .attrs = &ad7606_attribute_group_os_and_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_os = { @@ -527,6 +583,7 @@ static const struct iio_info ad7606_info_os = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_os, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_info ad7606_info_range = { @@ -534,6 +591,7 @@ static const struct iio_info ad7606_info_range = { .write_raw = &ad7606_write_raw, .attrs = &ad7606_attribute_group_range, .validate_trigger = &ad7606_validate_trigger, + .update_scan_mode = &ad7606_update_scan_mode, }; static const struct iio_trigger_ops ad7606_trigger_ops = { @@ -602,8 +660,6 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, indio_dev->channels = st->chip_info->channels; indio_dev->num_channels = st->chip_info->num_channels; - init_completion(&st->completion); - ret = ad7606_reset(st); if (ret) dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n"); @@ -635,7 +691,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, return ret; } - /* If convst pin is not defined, setup PWM*/ + /* If convst pin is not defined, setup PWM */ if (!st->gpio_convst) { st->cnvst_pwm = devm_pwm_get(dev, NULL); if (IS_ERR(st->cnvst_pwm)) @@ -671,14 +727,25 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) return ret; } - ret = devm_request_threaded_irq(dev, irq, - NULL, - &ad7606_interrupt, - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - chip_info->name, indio_dev); - if (ret) - return ret; + if (st->bops->iio_backend_config) { + st->bops->iio_backend_config(dev, indio_dev); + indio_dev->setup_ops = &ad7606_pwm_buffer_ops; + } else { + /* Reserve the PWM use only for backend (force gpio_convst definition)*/ + if (!st->gpio_convst) + return dev_err_probe(dev, -EINVAL, + "Convst pin must be defined when not in backend mode"); + + init_completion(&st->completion); + ret = devm_request_threaded_irq(dev, irq, + NULL, + &ad7606_interrupt, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + chip_info->name, indio_dev); + if (ret) + return ret; + } return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, IIO_AD7606); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index aab8fefb84be..9a098cd77812 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -34,6 +34,12 @@ BIT(IIO_CHAN_INFO_SCALE), \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) +#define AD7606_BI_CHANNEL(num) \ + AD760X_CHANNEL(num, 0, \ + BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) + #define AD7616_CHANNEL(num) \ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\ 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)) @@ -61,6 +67,7 @@ enum ad7606_supported_device_ids { * @os_req_reset some devices require a reset to update oversampling * @init_delay_ms required delay in miliseconds for initialization * after a restart + * @has_backend defines if a backend is available for the given chip */ struct ad7606_chip_info { enum ad7606_supported_device_ids id; @@ -71,6 +78,7 @@ struct ad7606_chip_info { unsigned int oversampling_num; bool os_req_reset; unsigned long init_delay_ms; + bool has_backend; }; /** @@ -116,6 +124,7 @@ struct ad7606_state { unsigned int num_scales; const unsigned int *oversampling_avail; unsigned int num_os_ratios; + struct iio_backend *back; int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); int (*write_os)(struct iio_dev *indio_dev, int val); @@ -140,16 +149,21 @@ struct ad7606_state { /** * struct ad7606_bus_ops - driver bus operations + * @iio_backend_config function pointer for configuring the iio_backend for + * the compatibles that use it * @read_block function pointer for reading blocks of data * @sw_mode_config: pointer to a function which configured the device * for software mode * @reg_read function pointer for reading spi register * @reg_write function pointer for writing spi register * @write_mask function pointer for write spi register with mask + * @update_scan_mode function pointer for handling the calls to iio_info's update_scan + * mode when enabling/disabling channels. * @rd_wr_cmd pointer to the function which calculates the spi address */ struct ad7606_bus_ops { /* more methods added in future? */ + int (*iio_backend_config)(struct device *dev, struct iio_dev *indio_dev); int (*read_block)(struct device *dev, int num, void *data); int (*sw_mode_config)(struct iio_dev *indio_dev); int (*reg_read)(struct ad7606_state *st, unsigned int addr); @@ -160,6 +174,7 @@ struct ad7606_bus_ops { unsigned int addr, unsigned long mask, unsigned int val); + int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *scan_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; @@ -264,6 +279,7 @@ static const struct ad7606_chip_info ad7606b_info = { .num_channels = 9, .oversampling_avail = ad7606_oversampling_avail, .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), + .has_backend = true, .name = "ad7606B", .id = ID_AD7606B, }; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index d83c0edc1e31..5c8a04556e25 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -3,6 +3,8 @@ * AD7606 Parallel Interface ADC driver * * Copyright 2011 Analog Devices Inc. + * Copyright 2024 Analog Devices Inc. + * Copyright 2024 BayLibre SAS. */ #include @@ -11,10 +13,86 @@ #include #include #include +#include +#include +#include #include +#include #include "ad7606.h" +#ifdef CONFIG_IIO_BACKEND +static const struct iio_chan_spec ad7606b_bi_channels[] = { + AD7606_BI_CHANNEL(0), + AD7606_BI_CHANNEL(1), + AD7606_BI_CHANNEL(2), + AD7606_BI_CHANNEL(3), + AD7606_BI_CHANNEL(4), + AD7606_BI_CHANNEL(5), + AD7606_BI_CHANNEL(6), + AD7606_BI_CHANNEL(7), +}; + +static int ad7606_bi_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) +{ + struct ad7606_state *st = iio_priv(indio_dev); + unsigned int c, ret; + + for (c = 0; c < indio_dev->num_channels; c++) { + if (test_bit(c, scan_mask)) + ret = iio_backend_chan_enable(st->back, c); + else + ret = iio_backend_chan_disable(st->back, c); + if (ret) + return ret; + } + + return 0; +} + +static int ad7606_bi_setup_iio_backend(struct device *dev, struct iio_dev *indio_dev) +{ + struct ad7606_state *st = iio_priv(indio_dev); + unsigned int ret, c; + + st->back = devm_iio_backend_get(dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + /* If the device is iio_backend powered the PWM is mandatory */ + if (!st->cnvst_pwm) + return -EINVAL; + + ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev); + if (ret) + return ret; + + ret = devm_iio_backend_enable(dev, st->back); + if (ret) + return ret; + + struct iio_backend_data_fmt data = { + .sign_extend = true, + .enable = true, + }; + for (c = 0; c < indio_dev->num_channels; c++) { + ret = iio_backend_data_format_set(st->back, c, &data); + if (ret) + return ret; + } + + indio_dev->channels = ad7606b_bi_channels; + indio_dev->num_channels = 8; + + return 0; +} + +static const struct ad7606_bus_ops ad7606_bi_bops = { + .iio_backend_config = ad7606_bi_setup_iio_backend, + .update_scan_mode = ad7606_bi_update_scan_mode, +}; +#endif + static int ad7606_par16_read_block(struct device *dev, int count, void *buf) { @@ -52,7 +130,20 @@ static int ad7606_par_probe(struct platform_device *pdev) void __iomem *addr; resource_size_t remap_size; int irq; - +#ifdef CONFIG_IIO_BACKEND + struct iio_backend *back; + + /*For now, only the AD7606B is backend compatible.*/ + if (chip_info->has_backend) { + back = devm_iio_backend_get(&pdev->dev, NULL); + if (IS_ERR(back)) + return PTR_ERR(back); + + return ad7606_probe(&pdev->dev, 0, NULL, + chip_info, + &ad7606_bi_bops); + } +#endif irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -74,6 +165,7 @@ static const struct platform_device_id ad7606_driver_ids[] = { { .name = "ad7606-4", .driver_data = (kernel_ulong_t)&ad7606_4_info, }, { .name = "ad7606-6", .driver_data = (kernel_ulong_t)&ad7606_6_info, }, { .name = "ad7606-8", .driver_data = (kernel_ulong_t)&ad7606_8_info, }, + { .name = "ad7606b", .driver_data = (kernel_ulong_t)&ad7606b_info, }, { } }; MODULE_DEVICE_TABLE(platform, ad7606_driver_ids); @@ -83,6 +175,7 @@ static const struct of_device_id ad7606_of_match[] = { { .compatible = "adi,ad7606-4", .data = &ad7606_4_info }, { .compatible = "adi,ad7606-6", .data = &ad7606_6_info }, { .compatible = "adi,ad7606-8", .data = &ad7606_8_info }, + { .compatible = "adi,ad7606b", .data = &ad7606b_info }, { } }; MODULE_DEVICE_TABLE(of, ad7606_of_match); @@ -102,3 +195,6 @@ MODULE_AUTHOR("Michael Hennerich "); MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS(IIO_AD7606); +#ifdef CONFIG_IIO_BACKEND +MODULE_IMPORT_NS(IIO_BACKEND); +#endif