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[92.88.170.124]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5bd1a5dfc9fsm3662421a12.66.2024.08.14.02.05.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 14 Aug 2024 02:06:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson , Thomas Petazzoni , Waldemar Brodkorb , Aleksandar Rikalo , Jiaxun Yang Subject: [PATCH-for-9.1 v4 1/3] target/mips: Pass page table entry size as MemOp to get_pte() Date: Wed, 14 Aug 2024 11:04:50 +0200 Message-ID: <20240814090452.2591-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240814090452.2591-1-philmd@linaro.org> References: <20240814090452.2591-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to simplify the next commit, pass the PTE size as MemOp. Rename: native_shift -> native_op directory_shift -> directory_mop leaf_shift -> leaf_mop Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu/tlb_helper.c | 58 ++++++++++++++--------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 3ba6d369a6..60147ba0af 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -592,13 +592,13 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, * resulting in a TLB or XTLB Refill exception. */ -static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, +static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op, uint64_t *pte) { - if ((vaddr & ((entry_size >> 3) - 1)) != 0) { + if ((vaddr & (memop_size(op) - 1)) != 0) { return false; } - if (entry_size == 64) { + if (op == MO_64) { *pte = cpu_ldq_code(env, vaddr); } else { *pte = cpu_ldl_code(env, vaddr); @@ -607,8 +607,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, } static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, - int entry_size, int ptei) + MemOp op, int ptei) { + unsigned entry_size = memop_size(op) << 3; uint64_t result = entry; uint64_t rixi; if (ptei > entry_size) { @@ -624,14 +625,12 @@ static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, int directory_index, bool *huge_page, bool *hgpg_directory_hit, uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, - unsigned directory_shift, unsigned leaf_shift, int ptw_mmu_idx) + MemOp directory_mop, MemOp leaf_mop, int ptw_mmu_idx) { int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; - uint32_t direntry_size = 1 << (directory_shift + 3); - uint32_t leafentry_size = 1 << (leaf_shift + 3); uint64_t entry; uint64_t paddr; int prot; @@ -643,14 +642,14 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, /* wrong base address */ return 0; } - if (!get_pte(env, *vaddr, direntry_size, &entry)) { + if (!get_pte(env, *vaddr, directory_mop, &entry)) { return 0; } if ((entry & (1 << psn)) && hugepg) { *huge_page = true; *hgpg_directory_hit = true; - entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); + entry = get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew); w = directory_index - 1; if (directory_index & 0x1) { /* Generate adjacent page from same PTE for odd TLB page */ @@ -658,7 +657,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, *pw_entrylo0 = entry & ~lsb; /* even page */ *pw_entrylo1 = entry | lsb; /* odd page */ } else if (dph) { - int oddpagebit = 1 << leaf_shift; + int oddpagebit = 1 << leaf_mop; uint64_t vaddr2 = *vaddr ^ oddpagebit; if (*vaddr & oddpagebit) { *pw_entrylo1 = entry; @@ -669,10 +668,10 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, ptw_mmu_idx) != TLBRET_MATCH) { return 0; } - if (!get_pte(env, vaddr2, leafentry_size, &entry)) { + if (!get_pte(env, vaddr2, leaf_mop, &entry)) { return 0; } - entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); + entry = get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew); if (*vaddr & oddpagebit) { *pw_entrylo0 = entry; } else { @@ -711,7 +710,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, /* Native pointer size */ /*For the 32-bit architectures, this bit is fixed to 0.*/ - int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3; + MemOp native_op = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? MO_32 : MO_64; /* Indices from PWField */ int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F; @@ -728,11 +727,10 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, /* Other HTW configs */ int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; - unsigned directory_shift, leaf_shift; + MemOp directory_mop, leaf_mop; /* Offsets into tables */ unsigned goffset, uoffset, moffset, ptoffset0, ptoffset1; - uint32_t leafentry_size; /* Starting address - Page Table Base */ uint64_t vaddr = env->CP0_PWBase; @@ -759,23 +757,21 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, } /* HTW Shift values (depend on entry size) */ - directory_shift = (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift; - leaf_shift = (ptew == 1) ? native_shift + 1 : native_shift; + directory_mop = (hugepg && (ptew == 1)) ? native_op + 1 : native_op; + leaf_mop = (ptew == 1) ? native_op + 1 : native_op; - goffset = gindex << directory_shift; - uoffset = uindex << directory_shift; - moffset = mindex << directory_shift; - ptoffset0 = (ptindex >> 1) << (leaf_shift + 1); - ptoffset1 = ptoffset0 | (1 << (leaf_shift)); - - leafentry_size = 1 << (leaf_shift + 3); + goffset = gindex << directory_mop; + uoffset = uindex << directory_mop; + moffset = mindex << directory_mop; + ptoffset0 = (ptindex >> 1) << (leaf_mop + 1); + ptoffset1 = ptoffset0 | (1 << (leaf_mop)); /* Global Directory */ if (gdw > 0) { vaddr |= goffset; switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift, ptw_mmu_idx)) + directory_mop, leaf_mop, ptw_mmu_idx)) { case 0: return false; @@ -792,7 +788,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, vaddr |= uoffset; switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift, ptw_mmu_idx)) + directory_mop, leaf_mop, ptw_mmu_idx)) { case 0: return false; @@ -809,7 +805,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, vaddr |= moffset; switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift, ptw_mmu_idx)) + directory_mop, leaf_mop, ptw_mmu_idx)) { case 0: return false; @@ -827,10 +823,10 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, ptw_mmu_idx) != TLBRET_MATCH) { return false; } - if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { + if (!get_pte(env, vaddr, leaf_mop, &dir_entry)) { return false; } - dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); + dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew); pw_entrylo0 = dir_entry; /* Leaf Level Page Table - Second half of PTE pair */ @@ -839,10 +835,10 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, ptw_mmu_idx) != TLBRET_MATCH) { return false; } - if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { + if (!get_pte(env, vaddr, leaf_mop, &dir_entry)) { return false; } - dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); 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[92.88.170.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f414f06bsm145948166b.159.2024.08.14.02.06.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 14 Aug 2024 02:06:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson , Thomas Petazzoni , Waldemar Brodkorb , Aleksandar Rikalo , Jiaxun Yang Subject: [PATCH-for-9.1 v4 2/3] target/mips: Use correct MMU index in get_pte() Date: Wed, 14 Aug 2024 11:04:51 +0200 Message-ID: <20240814090452.2591-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240814090452.2591-1-philmd@linaro.org> References: <20240814090452.2591-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM or SM, while we only expect KM or ERL. Fix by propagating ptw_mmu_idx to get_pte(), and use the cpu_ld/st_code_mmu() API with the correct MemOpIdx. Reported-by: Thomas Petazzoni Reported-by: Waldemar Brodkorb Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2470 Fixes: 4e999bf419 ("target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/sysemu/tlb_helper.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 60147ba0af..0e94e00a5f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -593,16 +593,21 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, */ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op, - uint64_t *pte) + uint64_t *pte, unsigned ptw_mmu_idx) { + MemOpIdx oi; + if ((vaddr & (memop_size(op) - 1)) != 0) { return false; } + + oi = make_memop_idx(op | MO_TE, ptw_mmu_idx); if (op == MO_64) { - *pte = cpu_ldq_code(env, vaddr); + *pte = cpu_ldq_code_mmu(env, vaddr, oi, 0); } else { - *pte = cpu_ldl_code(env, vaddr); + *pte = cpu_ldl_code_mmu(env, vaddr, oi, 0); } + return true; } @@ -642,7 +647,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, /* wrong base address */ return 0; } - if (!get_pte(env, *vaddr, directory_mop, &entry)) { + if (!get_pte(env, *vaddr, directory_mop, &entry, ptw_mmu_idx)) { return 0; } @@ -668,7 +673,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, ptw_mmu_idx) != TLBRET_MATCH) { return 0; } - if (!get_pte(env, vaddr2, leaf_mop, &entry)) { + if (!get_pte(env, vaddr2, leaf_mop, &entry, ptw_mmu_idx)) { return 0; } entry = get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew); @@ -823,7 +828,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, ptw_mmu_idx) != TLBRET_MATCH) { return false; } - if (!get_pte(env, vaddr, leaf_mop, &dir_entry)) { + if (!get_pte(env, vaddr, leaf_mop, &dir_entry, ptw_mmu_idx)) { return false; } dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew); @@ -835,7 +840,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, ptw_mmu_idx) != TLBRET_MATCH) { return false; } - if (!get_pte(env, vaddr, leaf_mop, &dir_entry)) { + if (!get_pte(env, vaddr, leaf_mop, &dir_entry, ptw_mmu_idx)) { return false; } dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew); From patchwork Wed Aug 14 09:04:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 819102 Delivered-To: patch@linaro.org Received: by 2002:adf:cd01:0:b0:367:895a:4699 with SMTP id w1csp612073wrm; Wed, 14 Aug 2024 02:06:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWcvsJo8N/pFW48CielvRdSibmlFAMGXR3/F1Zyak/2FR02h/TWD06fmpJQfHzu6pnABhNLHQ==@linaro.org X-Google-Smtp-Source: AGHT+IEUwBd0DFZHVw9iGhfyVsv1ZQMB7Vq2O6iSXtPe7ji13TW8P1mtCGKCEGlYdvpDapeUbiZ2 X-Received: by 2002:a05:622a:4d88:b0:447:e808:ab24 with SMTP id d75a77b69052e-4535bb967cfmr24925681cf.50.1723626408915; Wed, 14 Aug 2024 02:06:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1723626408; cv=none; d=google.com; s=arc-20160816; b=nnvGD+IKOAn5+hqGkRdsPdT7YvjxieWW+xjPmvzhasIpoe4/79j9Hg0sRapDcrFNZQ mmQyoblQAyVsZW0OjWrtAA0R4DB1at4pqbZPtwWEl3KT7LDJW7txKApOh6F8NbnoPFIg vJPzAoM97/nbzqXr9B6bhxNQq3FKKH/68ZXVBXJpa/UQjL8xyj0RBlWd7nJ8M6tb8LU8 +wJFYtKINc4A4uiBy70zXQK+2u+208JbyuqhayqYzRuN9ZhyDJ5VawaBK3wI+xvH3S3m bGReh7Z6uii/+UQD9VKv9amyJe5s4Yc1yZYaP8yepODSJte653ptQKk08v6xQTPrKhBM mpNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2c0XRHjU0y3cm6Z6eyIislTDkEC9zABvUTWrSeWCGjw=; fh=KbgWYUS9OqO/4JTC9tmS48IRNwt9Cke8+NcPyuT3iko=; b=LaoQWtBVzbkevY3uV18v4jN9Bq2hg+9r3OpYcY7LFpSjmVoZVvXVqKCfj6yPRe88tk MBIaLy1BRXk8DkAc8okFeSHvt/XIR2KCEAGdVuSuNO5+zBJ7ezznsfNURCbxtBUXmHxQ UfSUYpPQLOcFggB+idndxk7Cz0QToicHATt+XRQeFw7b+Iz2DmpXS0RLQR+7Fy7UYt7K OUzVDUSIdZNmKfBbpKirlPr6YswiS1U84ykUIhe3nhoVD74SrbzTkRIytug7gxjWt0QW K2wX8Ikkm/QZxA+6YzpmbXplsGE7FNB7kD7SDrfQxRfYxI1iDfV/9cPZriGMdoEHMReX +JVA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="eVh4jqt/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[92.88.170.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f414e561sm145162166b.169.2024.08.14.02.06.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 14 Aug 2024 02:06:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson , Thomas Petazzoni , Waldemar Brodkorb , Aleksandar Rikalo , Jiaxun Yang Subject: [PATCH-for-9.1 v4 3/3] target/mips: Load PTE as DATA Date: Wed, 14 Aug 2024 11:04:52 +0200 Message-ID: <20240814090452.2591-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240814090452.2591-1-philmd@linaro.org> References: <20240814090452.2591-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PTE is not CODE so load it as normal DATA access. Fixes: 074cfcb4da ("Implement hardware page table walker for MIPS32") Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/sysemu/tlb_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 0e94e00a5f..3836137750 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -603,9 +603,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op, oi = make_memop_idx(op | MO_TE, ptw_mmu_idx); if (op == MO_64) { - *pte = cpu_ldq_code_mmu(env, vaddr, oi, 0); + *pte = cpu_ldq_mmu(env, vaddr, oi, 0); } else { - *pte = cpu_ldl_code_mmu(env, vaddr, oi, 0); + *pte = cpu_ldl_mmu(env, vaddr, oi, 0); } return true;