From patchwork Fri Nov 8 15:25:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178914 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860734ilf; Fri, 8 Nov 2019 07:26:53 -0800 (PST) X-Google-Smtp-Source: APXvYqwZVsuLjgZj3eH2s+qltSM70vg/l83NgeSNQ6aBT7vh8k0/V6qrCk8rMdgRAaRCZ9zlnN1c X-Received: by 2002:a50:fb85:: with SMTP id e5mr10719178edq.274.1573226813677; Fri, 08 Nov 2019 07:26:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226813; cv=none; d=google.com; s=arc-20160816; b=WKszJwEjCtXv4GwNKSHQG17ih3TxQQBi5ieoN3FxQVZO2+OXICHpPlVdwFVFnXn4zP Mi/zuj/85qBEnutVE67dAbd28Do1dnBZrjmYP4VS6VHEby4/+IRM5dqJeFANA0Pnu6Y7 00x4l2sPvAEpslMRVDOneXW7LTdCXTfYfOWdlrDy4TDyF7P4jOte6Igd5gtT6inI+RUk oWzm9YbQ+lWWeju7hFGgAtyxRDnkuWK5/EjRIu4rxwOgMlZe3LmDNDY+pJIKZEgKPdcV DX4bKeInLwC40rNpmlHNlkaZs24pAAs5B+MEYntJXWO+wo3TIkH+p2+TEqyIpZfNwwvN grJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SJ0pi6TcxZ7peU2M0iysnkfrxFwiFSB7n/XBu4wivSo=; b=qftHylymuvlE+yzP25OMPeL45VU16Jlv2K7v5c47z2gD5rGrG5GIOsmK2mCf0HnQ6D 4u8xhQdk6GAHN4SnBCnuiLNxUOYHEAtCv3C7XP9VexTvaSUiIuCNyF7bm9HBdMzVH2vV DiUTdEZrPxCQJc0o7/ug58nxOrZk5vY5yWy8BLXDP24KcL+uf3HlveNQ/LAGs227crmo lsdEhV4SeDJmUZUS3GDTpnLpLcBOiPKbut0q0bbD1P8lz/yM+y2BwDazPiBz/QercfXL zdjqrr7A+g9XXG+Yy+SDqVYH/2SbScFmrwHY6YNbmpQIHN1vbkFoNztWKptRWiJ/pG4V Na8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FJH028lD; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.26.53; Fri, 08 Nov 2019 07:26:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FJH028lD; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726819AbfKHP0w (ORCPT + 8 others); Fri, 8 Nov 2019 10:26:52 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45276 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726576AbfKHP0w (ORCPT ); Fri, 8 Nov 2019 10:26:52 -0500 Received: by mail-wr1-f66.google.com with SMTP id z10so2183736wrs.12 for ; Fri, 08 Nov 2019 07:26:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SJ0pi6TcxZ7peU2M0iysnkfrxFwiFSB7n/XBu4wivSo=; b=FJH028lD8udbYUj9HmW9HX+1pehY+1lWWRbuMjmApuHYEIKQLcSg0vICaIv4+60xTP SZObRA6SwQO9RwBVxZugqTUZI+vA8BvgqNj052zrmBwRHwWzaojQtHWRGbFCtztastzr pmnt/WYGWHFKd5AIcAMo8pJ6oAExUKnBYXeKVhe6kKjq+nXxzRdtnQJqvWgIRIrK+0ku 4w7Dv2dYtYuKDn+v92hj11WbpQkpItAZUnzsJTk2q+ms3DMjKlct9veZzcMJgZOs9qQH iADkZLXOARDNATZhqDbKKo0FVoWdnh6jiRIOlQnG9iluhoxnk9D5UjR8R2mtDUOOVWdC O1HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SJ0pi6TcxZ7peU2M0iysnkfrxFwiFSB7n/XBu4wivSo=; b=iGLRlOF9DhTwxLjg6010s1TjHKNlrtxSuiwIQCsU2VrWXsmdoh3Xt1FlZ5hICZnm7U S4U/d5fiyY00xHjs6K9385NGEgfpjwnU5XOH8mYx3koSOeRFA0OkW/ljLBJEYff6/hU4 esYHY+AJgDbvDmUv+oJpjKae7iE1SZFcsIBG5UKuOGqgTVzxV9TzjW7ghS1spxLmAbVF xB0SywEFkGe7AAzWwm7udrVEFzSK3xMHektXoQuG1Psaq9KwR+ooBcCkVb79RZrGRyG1 8SyQSVo3LN/S9h9sqLMtesKYSQg4SrI4SMN5+5by3KEaoyUoVI1npNekkGQVaONQwZ4R G//w== X-Gm-Message-State: APjAAAX/QrVDiSnMfcaHCh2c4ZTbtiKAUl4TY9qa/MwKQpHrlkZgAT/q 7TXuZeVpUna7edwOc+j14PK3gQ== X-Received: by 2002:adf:edc5:: with SMTP id v5mr8967125wro.322.1573226809763; Fri, 08 Nov 2019 07:26:49 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:49 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 2/8] iommu/arm-smmu-v3: Support platform SSID Date: Fri, 8 Nov 2019 16:25:02 +0100 Message-Id: <20191108152508.4039168-3-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For platform devices that support SubstreamID (SSID), firmware provides the number of supported SSID bits. Restrict it to what the SMMU supports and cache it into master->ssid_bits, which will also be used for PCI PASID. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 13 +++++++++++++ drivers/iommu/of_iommu.c | 6 +++++- include/linux/iommu.h | 2 ++ 3 files changed, 20 insertions(+), 1 deletion(-) -- 2.23.0 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 8da93e730d6f..33488da8f742 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -292,6 +292,12 @@ #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) +/* + * When the SMMU only supports linear context descriptor tables, pick a + * reasonable size limit (64kB). + */ +#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3)) + /* Convert between AArch64 (CPU) TCR format and SMMU CD format */ #define ARM_SMMU_TCR2CD(tcr, fld) FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \ FIELD_GET(ARM64_TCR_##fld, tcr)) @@ -638,6 +644,7 @@ struct arm_smmu_master { u32 *sids; unsigned int num_sids; bool ats_enabled; + unsigned int ssid_bits; }; /* SMMU private data for an IOMMU domain */ @@ -2572,6 +2579,12 @@ static int arm_smmu_add_device(struct device *dev) } } + master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); + + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) + master->ssid_bits = min_t(u8, master->ssid_bits, + CTXDESC_LINEAR_CDMAX); + group = iommu_group_get_for_dev(dev); if (!IS_ERR(group)) { iommu_group_put(group); diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 614a93aa5305..aab63e9f283f 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -194,8 +194,12 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, if (err) break; } - } + fwspec = dev_iommu_fwspec_get(dev); + if (!err && fwspec) + of_property_read_u32(master_np, "pasid-num-bits", + &fwspec->num_pasid_bits); + } /* * Two success conditions can be represented by non-negative err here: diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f84fe76f0eea..0a3d9c3c368a 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -576,6 +576,7 @@ struct iommu_group *fsl_mc_device_group(struct device *dev); * @ops: ops for this device's IOMMU * @iommu_fwnode: firmware handle for this device's IOMMU * @iommu_priv: IOMMU driver private data for this device + * @num_pasid_bits: number of PASID bits supported by this device * @num_ids: number of associated device IDs * @ids: IDs which this device may present to the IOMMU */ @@ -584,6 +585,7 @@ struct iommu_fwspec { struct fwnode_handle *iommu_fwnode; void *iommu_priv; u32 flags; + u32 num_pasid_bits; unsigned int num_ids; u32 ids[1]; }; From patchwork Fri Nov 8 15:25:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178920 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860804ilf; Fri, 8 Nov 2019 07:26:57 -0800 (PST) X-Google-Smtp-Source: APXvYqyb9MKBHzvb1jTMv07KsLaLjPQ2ylAngLz5b2zUW5KzudFFRt5s5xsFbX4K5aZ5JSoWAX2z X-Received: by 2002:aa7:d44c:: with SMTP id q12mr10824474edr.108.1573226817363; Fri, 08 Nov 2019 07:26:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226817; cv=none; d=google.com; s=arc-20160816; b=kWx14VlkvMUQwuZ8T98mW9GMppbvPNKuJ8RXK8OaQWcvPSW9ck6eVboNWJjAYVGQvO PHC+/P96rFlBXhKF3rWRkavlr7ysFCCVum4XKhSAp36w2ehroZI2fG3SbM6Sr+AcNnNn GlkOltOuGaXbulH2VR7As2M6y6Ou79tt4EFKQ/LCLGShXDAAVMs/ojrY1J2haGqfKpH/ 5Jx4KYiPSaNDjSbOfSL3xWDnngVyD5z+HRSloiX+lyoq2xKp4kWH4ZlLL+oBGaW8glX2 cf9+y2DcKLhU4AlTHJMNOgs8P7Ajp+kqAd1DnK3VfcCJxH9AZfWW67nIjsnsTuC1ovkP vBBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mnbYxHwwKDCCUndGgMW6LrNDIvr5LwgLaOHQExbW9co=; b=VeCy2TckJcFmZdcX/Pt55JTJ1/LK/wexPcCiA33RnVY/C+t6pNtdvTJ0ac/JokglCK /PU4BZd4T8zbtbvSXu91DdvRPcWYRA/VW3EggO6qaKk1JIXvPAo87Zl909mUA5/+IvUZ djhnS3vnfS4mNbOAHlTxb+Gzk2yZ/kenXckIkdsCT0vmxcPmMUAAK6xAqkWkKI9Xv7lD 1J7Jugw/5SDWKRnB/nqCDk2S99Q44tnR6zvHXuV7YJHe/SkfXlSpLlemRyrbC0y/HOfY uzu2YMV/gapczpkztD5GFrVcaMoV18HNqK3U6K9TmnqPzJ1+FmuNH15GdaeEWRdMab1r X+MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vt/ucZmg"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.26.57; Fri, 08 Nov 2019 07:26:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vt/ucZmg"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726935AbfKHP04 (ORCPT + 8 others); Fri, 8 Nov 2019 10:26:56 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:40018 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726879AbfKHP04 (ORCPT ); Fri, 8 Nov 2019 10:26:56 -0500 Received: by mail-wm1-f65.google.com with SMTP id f3so6620018wmc.5 for ; Fri, 08 Nov 2019 07:26:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mnbYxHwwKDCCUndGgMW6LrNDIvr5LwgLaOHQExbW9co=; b=vt/ucZmgN0eSNi3NEFrhHunIf8tyXq2gAai53SFY8mpYU92IidJLVOzDyQcqjyhBSr T8V4hxDutApsmCo8XT8vx9ZyQFWiamm0n6iIZ6FFeHocN8Ilpv/vzaCesmkkAXgGkqp6 Vv2LFDzC6AYGjeW0gkZmEjdOetkTjsCxun2mwuwI0nmbuKtRd8RcHpIsYdLXB0gSL+9r 7hn0cuTBF5GHBLoTjJ8AKFErIUJQ81Cx/c+1Ke/nQnNGY8yjrhGxGvT7Hv8IlzeQ2+co xdCufQTFaCf7u30IWO/faFmuYxPTNPO9uhAlm1Xm/j5QVooBAWITKWn/y10ru9QdDfzP a70g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mnbYxHwwKDCCUndGgMW6LrNDIvr5LwgLaOHQExbW9co=; b=aKB/G+CJ+xQf3h0HnS4jVwodCxmdbWjKUju5SOrDr1ax4+SZg3SJCvWEUnyIyz99XS UfgtgbkZy2i4yXIMhy6UzhcUSF/vuuikP055ClJ9td7+U1JBqWUMT/X3FR4P4xJQLuud H6l+Nsu1NL/yCtXeZwgUkVqAx8p5mGhur8gLdLshxyagwF39jSd1ubjJapeJzbgjluf+ F/NkAe/f1262OCNRkb1bmnun7UhoyaMCDZQayyDpBj4Al6uAqHDN25wLJqIg7M4UKgkz /VYeEWn84dYRXd1Gz0ojCQZiVhO3nL9fWgTCMFrkXctlvvMi6sb9Y9kYL+UgaBh3gXxd inVw== X-Gm-Message-State: APjAAAUAiZw3wbsa5EP+H5G32mOS2E2dI1KscAo21u0c4RhbFLlCLS1y f7ObAVdviFm8LKGNmC+TG1fUdA== X-Received: by 2002:a7b:c747:: with SMTP id w7mr9236169wmk.62.1573226813391; Fri, 08 Nov 2019 07:26:53 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:52 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 5/8] iommu/arm-smmu-v3: Add support for Substream IDs Date: Fri, 8 Nov 2019 16:25:05 +0100 Message-Id: <20191108152508.4039168-6-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org At the moment, the SMMUv3 driver implements only one stage-1 or stage-2 page directory per device. However SMMUv3 allows more than one address space for some devices, by providing multiple stage-1 page directories. In addition to the Stream ID (SID), that identifies a device, we can now have Substream IDs (SSID) identifying an address space. In PCIe, SID is called Requester ID (RID) and SSID is called Process Address-Space ID (PASID). Prepare the driver for SSID support, by adding context descriptor tables in STEs (previously a single static context descriptor). A complete stage-1 walk is now performed like this by the SMMU: Stream tables Ctx. tables Page tables +--------+ ,------->+-------+ ,------->+-------+ : : | : : | : : +--------+ | +-------+ | +-------+ SID->| STE |---' SSID->| CD |---' IOVA->| PTE |--> IPA +--------+ +-------+ +-------+ : : : : : : +--------+ +-------+ +-------+ Implement a single level of context descriptor table for now, but as with stream and page tables, an SSID can be split to index multiple levels of tables. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 132 ++++++++++++++++++++++++++++++------ 1 file changed, 111 insertions(+), 21 deletions(-) -- 2.23.0 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 122bed0168a3..df7d45503c65 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -227,6 +227,11 @@ #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) +#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0) +#define STRTAB_STE_1_S1DSS_TERMINATE 0x0 +#define STRTAB_STE_1_S1DSS_BYPASS 0x1 +#define STRTAB_STE_1_S1DSS_SSID0 0x2 + #define STRTAB_STE_1_S1C_CACHE_NC 0UL #define STRTAB_STE_1_S1C_CACHE_WBRA 1UL #define STRTAB_STE_1_S1C_CACHE_WT 2UL @@ -329,6 +334,7 @@ #define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0) #define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12) +#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12) #define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32) #define CMDQ_CFGI_1_LEAF (1UL << 0) #define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0) @@ -446,8 +452,11 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_CFGI_STE 0x3 #define CMDQ_OP_CFGI_ALL 0x4 + #define CMDQ_OP_CFGI_CD 0x5 + #define CMDQ_OP_CFGI_CD_ALL 0x6 struct { u32 sid; + u32 ssid; union { bool leaf; u8 span; @@ -566,6 +575,7 @@ struct arm_smmu_cd_table { }; struct arm_smmu_s1_cfg { + u8 s1fmt; u8 s1cdmax; struct arm_smmu_cd_table table; struct arm_smmu_ctx_desc cd; @@ -860,10 +870,16 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[1] |= FIELD_PREP(CMDQ_PREFETCH_1_SIZE, ent->prefetch.size); cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK; break; + case CMDQ_OP_CFGI_CD: + cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid); + /* Fallthrough */ case CMDQ_OP_CFGI_STE: cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf); break; + case CMDQ_OP_CFGI_CD_ALL: + cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); + break; case CMDQ_OP_CFGI_ALL: /* Cover the entire SID range */ cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); @@ -1456,6 +1472,33 @@ static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) } /* Context descriptor manipulation functions */ +static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, + int ssid, bool leaf) +{ + size_t i; + unsigned long flags; + struct arm_smmu_master *master; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_CFGI_CD, + .cfgi = { + .ssid = ssid, + .leaf = leaf, + }, + }; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + for (i = 0; i < master->num_sids; i++) { + cmd.cfgi.sid = master->sids[i]; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_cmdq_issue_sync(smmu); +} + static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu, struct arm_smmu_cd_table *table, size_t num_entries) @@ -1481,6 +1524,11 @@ static void arm_smmu_free_cd_leaf_table(struct arm_smmu_device *smmu, dmam_free_coherent(smmu->dev, size, table->ptr, table->ptr_dma); } +static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_s1_cfg *cfg, u32 ssid) +{ + return cfg->table.ptr + ssid * CTXDESC_CD_DWORDS; +} + static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) { u64 val = 0; @@ -1498,34 +1546,68 @@ static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) return val; } -static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, - struct arm_smmu_s1_cfg *cfg) +static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, + int ssid, struct arm_smmu_ctx_desc *cd) { u64 val; - __le64 *cdptr = cfg->table.ptr; + bool cd_live; + struct arm_smmu_device *smmu = smmu_domain->smmu; + __le64 *cdptr = arm_smmu_get_cd_ptr(&smmu_domain->s1_cfg, ssid); /* - * We don't need to issue any invalidation here, as we'll invalidate - * the STE when installing the new entry anyway. + * This function handles the following cases: + * + * (1) Install primary CD, for normal DMA traffic (SSID = 0). + * (2) Install a secondary CD, for SID+SSID traffic. + * (3) Update ASID of a CD. Atomically write the first 64 bits of the + * CD, then invalidate the old entry and mappings. + * (4) Remove a secondary CD. */ - val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) | -#ifdef __BIG_ENDIAN - CTXDESC_CD_0_ENDI | -#endif - CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET | - CTXDESC_CD_0_AA64 | FIELD_PREP(CTXDESC_CD_0_ASID, cfg->cd.asid) | - CTXDESC_CD_0_V; - /* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */ - if (smmu->features & ARM_SMMU_FEAT_STALL_FORCE) - val |= CTXDESC_CD_0_S; + if (!cdptr) + return -ENOMEM; - cdptr[0] = cpu_to_le64(val); + val = le64_to_cpu(cdptr[0]); + cd_live = !!(val & CTXDESC_CD_0_V); - val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK; - cdptr[1] = cpu_to_le64(val); + if (!cd) { /* (4) */ + val = 0; + } else if (cd_live) { /* (3) */ + val &= ~CTXDESC_CD_0_ASID; + val |= FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid); + /* + * Until CD+TLB invalidation, both ASIDs may be used for tagging + * this substream's traffic + */ + } else { /* (1) and (2) */ + cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); + cdptr[2] = 0; + cdptr[3] = cpu_to_le64(cd->mair); - cdptr[3] = cpu_to_le64(cfg->cd.mair); + /* + * STE is live, and the SMMU might fetch this CD at any + * time. Ensure that it observes the rest of the CD before we + * enable it. + */ + arm_smmu_sync_cd(smmu_domain, ssid, true); + + val = arm_smmu_cpu_tcr_to_cd(cd->tcr) | +#ifdef __BIG_ENDIAN + CTXDESC_CD_0_ENDI | +#endif + CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET | + CTXDESC_CD_0_AA64 | + FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | + CTXDESC_CD_0_V; + + /* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */ + if (smmu->features & ARM_SMMU_FEAT_STALL_FORCE) + val |= CTXDESC_CD_0_S; + } + + WRITE_ONCE(cdptr[0], cpu_to_le64(val)); + arm_smmu_sync_cd(smmu_domain, ssid, true); + return 0; } static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) @@ -1533,6 +1615,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; + cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; return arm_smmu_alloc_cd_leaf_table(smmu, &cfg->table, 1 << cfg->s1cdmax); } @@ -1664,6 +1747,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, if (s1_cfg) { BUG_ON(ste_live); dst[1] = cpu_to_le64( + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | @@ -1674,7 +1758,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); val |= (s1_cfg->table.ptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) | - FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS); + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); } if (s2_cfg) { @@ -2224,10 +2310,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; - arm_smmu_write_ctx_desc(smmu, cfg); + ret = arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); + if (ret) + goto out_free_tables; return 0; +out_free_tables: + arm_smmu_free_cd_tables(smmu_domain); out_free_asid: arm_smmu_bitmap_free(smmu->asid_map, asid); return ret; From patchwork Fri Nov 8 15:25:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 178919 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2860881ilf; Fri, 8 Nov 2019 07:27:01 -0800 (PST) X-Google-Smtp-Source: APXvYqyYY1pgblz6JTf/xgyqiTRFStvhRqNOgPpgJouW6wKbJNUH2VouUMsxcgOOzznbPmgU/9lU X-Received: by 2002:aa7:d2cf:: with SMTP id k15mr10769585edr.267.1573226821507; Fri, 08 Nov 2019 07:27:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573226821; cv=none; d=google.com; s=arc-20160816; b=GtWTjCGasgMxGR0kO7J7OmOQMPcls57zyT5/peihoFNbT0N+LW+VQaiAlXqTtYyAtF a7oXSc/WFm2uEvUtaGLj71LVjlX6DqYScZma6aYWIs0hyrZKnU4tMSAFfyu44fOggKs7 abmBbOVqh9aUpIDKenNpiaLdXRbQY654HYvf0aJlTtiDVUy07qESddAUVBLxSO3u1EGw 1KV8CM3Vm8lvgQINmmgj1eBt1cPqhEt0la0nM1pNBE/QI7VeQAN/hs+u7bv7pCfd8Qpa jRAr/ghUKZVuSo42YPoEvTzSa5ojQXdLefg+1AuNUVL/TR9rx8KbpnmDoARAc8OxnCIb GN1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FjGV9dHEsXE/CXRMwyPeo6zW+qyz6ot3r0JcxY8EA5E=; b=GPdCbHEkwoeCSdt8afTlPaFJReeHCHXu7+bKfKVw5D31j7ZtBmgUMqamx6N0HgCYE4 bdiaDfCZebGNl8KoT88ofI8bbgc1Jf2Wwl9M/iKWxTNDtPC/DGJVLw0EsKfTViGyARjQ Dja1Ip06RH0Uns06hs4nFlePexgC0dKM1r0AzCDljgL6OwSck++7eJUzwhBsSosZXzCR n4I554rqMT+VGHh0kr3+NiYgQ/qPDT+4TJfZGzE0w7wxe+VbApqqzc4Gau6k3FjZqgmS 51uygrEnn3594mcr53lWA1ACVh+Tp20UIvY+cARY5YMjP5qUKQKH9KGr1TXGKcZF0Gre 7lRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Stc/zRTg"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y31si4384892edb.47.2019.11.08.07.27.01; Fri, 08 Nov 2019 07:27:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Stc/zRTg"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726845AbfKHP1A (ORCPT + 8 others); Fri, 8 Nov 2019 10:27:00 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:34600 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726743AbfKHP1A (ORCPT ); Fri, 8 Nov 2019 10:27:00 -0500 Received: by mail-wr1-f66.google.com with SMTP id e6so7561545wrw.1 for ; Fri, 08 Nov 2019 07:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FjGV9dHEsXE/CXRMwyPeo6zW+qyz6ot3r0JcxY8EA5E=; b=Stc/zRTgvuJV42ldqRHlqe8DkziQ/xZI3K/M//32mxdJaRU1jz2L5/fMxZ1QFhpcGb EvSLry3iFu8329VB2GuTsvuMtRKQtUr6NhZe+OfFoUtq8NdYCPynlIwHbw/GjFUbmRC+ H6gal8DBpakRVo3SnhTJfseRLFp1XqfFkb3D3NUiwdPCcqFJAIgPj+gGr6Z9Up4EP+4P 8+Ut1quAnJxAurGbZKQH/VrQGWCWm7la8zmxc89J8tDCxR4MRqdAj9qnVky2l9P/QGSc 7hQrDyjXx2qQgCLFiaNFaKInDn2CY6ehhHcEYqTjArSQZFKJgu0xbSGyle/kTSvYSm0a jagQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FjGV9dHEsXE/CXRMwyPeo6zW+qyz6ot3r0JcxY8EA5E=; b=VCqo/qeaLZ3m1fEd0qhjkA4Lwt7kfUCdkUI9A8QTB+8YsqOSRRVaGwVddGpDrF41b0 XSXJ+rc0ImOLluSmaEY/J72KaNBrnsBjkLOsfymnt/HtRVTDSX9ln2To6G7vaqxjZzLi OjSVeEznACiX3WJa/bspJUfzYiZNdNmyecR0uTszA1Qds14WWuxhDfJ0DWLDD7EQF+Sd fndiRizAPH+mpl7lid/XRCo9nP5qXGFDDvOILnarAPcanbvpIOjq9UNsV7mHP+5eAYrJ HrRTBv+U+FhbKTktstCPBY5eE1MCspJ9APETEgN0T2XYQKQAwIKD83Wk0n8HCTTTFQtc 4lFw== X-Gm-Message-State: APjAAAVj/IV2Kl2kHL6WKhobpNCY2p+u2yIXnjn/vXtfAJuYobPPxnD0 ZzJ+cPH8+F4Kz+BYTSMWTZtPLQ== X-Received: by 2002:a5d:4c4e:: with SMTP id n14mr9845340wrt.260.1573226817077; Fri, 08 Nov 2019 07:26:57 -0800 (PST) Received: from localhost.localdomain ([85.195.192.192]) by smtp.gmail.com with ESMTPSA id w18sm6579232wrp.31.2019.11.08.07.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 07:26:56 -0800 (PST) From: Jean-Philippe Brucker To: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, will@kernel.org, robin.murphy@arm.com, zhangfei.gao@linaro.org, eric.auger@redhat.com, jonathan.cameron@huawei.com Subject: [PATCH v2 8/8] iommu/arm-smmu-v3: Add support for PCI PASID Date: Fri, 8 Nov 2019 16:25:08 +0100 Message-Id: <20191108152508.4039168-9-jean-philippe@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191108152508.4039168-1-jean-philippe@linaro.org> References: <20191108152508.4039168-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PASID for PCI devices that support it. Since the SSID tables are allocated by arm_smmu_attach_dev(), PASID has to be enabled early enough. arm_smmu_dev_feature_enable() would be too late, since by that time the main DMA domain has already been attached. Do it in add_device() instead. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 51 ++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) -- 2.23.0 Reviewed-by: Jonathan Cameron diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 88ec0bf33492..3ee313c08325 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2633,6 +2633,49 @@ static void arm_smmu_disable_ats(struct arm_smmu_master *master) atomic_dec(&smmu_domain->nr_ats_masters); } +static int arm_smmu_enable_pasid(struct arm_smmu_master *master) +{ + int ret; + int features; + int num_pasids; + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return -ENOSYS; + + pdev = to_pci_dev(master->dev); + + features = pci_pasid_features(pdev); + if (features < 0) + return -ENOSYS; + + num_pasids = pci_max_pasids(pdev); + if (num_pasids <= 0) + return -ENOSYS; + + ret = pci_enable_pasid(pdev, features); + if (!ret) + master->ssid_bits = min_t(u8, ilog2(num_pasids), + master->smmu->ssid_bits); + return ret; +} + +static void arm_smmu_disable_pasid(struct arm_smmu_master *master) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return; + + pdev = to_pci_dev(master->dev); + + if (!pdev->pasid_enabled) + return; + + master->ssid_bits = 0; + pci_disable_pasid(pdev); +} + static void arm_smmu_detach_dev(struct arm_smmu_master *master) { unsigned long flags; @@ -2841,13 +2884,16 @@ static int arm_smmu_add_device(struct device *dev) master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); + /* Note that PASID must be enabled before, and disabled after ATS */ + arm_smmu_enable_pasid(master); + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) master->ssid_bits = min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); ret = iommu_device_link(&smmu->iommu, dev); if (ret) - goto err_free_master; + goto err_disable_pasid; group = iommu_group_get_for_dev(dev); if (IS_ERR(group)) { @@ -2860,6 +2906,8 @@ static int arm_smmu_add_device(struct device *dev) err_unlink: iommu_device_unlink(&smmu->iommu, dev); +err_disable_pasid: + arm_smmu_disable_pasid(master); err_free_master: kfree(master); fwspec->iommu_priv = NULL; @@ -2880,6 +2928,7 @@ static void arm_smmu_remove_device(struct device *dev) arm_smmu_detach_dev(master); iommu_group_remove_device(dev); iommu_device_unlink(&smmu->iommu, dev); + arm_smmu_disable_pasid(master); kfree(master); iommu_fwspec_free(dev); }