From patchwork Fri Nov 8 05:19:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178849 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2158596ilf; Thu, 7 Nov 2019 21:20:09 -0800 (PST) X-Google-Smtp-Source: APXvYqzdJdYDfPT7z+pA9gxezXUJDj3CTtC8JlWmk54+XSipOgv0Qf5Gzxu5Y3qAtdDDVo6cNES+ X-Received: by 2002:aa7:dc1a:: with SMTP id b26mr8127279edu.139.1573190409499; Thu, 07 Nov 2019 21:20:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190409; cv=none; d=google.com; s=arc-20160816; b=ML54A3J20uDJ0VEaEMmZzFmsXxS7oDddvmeTqcX5OqgYXrbV7eoAMKrt7lLAwiI94R jcYJNrOyUjwV8bu9BSTxclPl9qS9vO+n9raHHLS7lo/Fz6VrM24sPNUEsh19+b5WfRqt 1b5b4BKSR+A/x7ySofX1ZKb73GesQK7MejWl+PbPQ+r6WNlbfs64MOlSTwMzRHcGRWxh /10zsTnl6N62ummyR0VJGtA6Kk2MUVwU0Fxd7LF0g8YlQtH0TIviawrCx5n21QVstoT1 yTfIO2z92+LDGttEmvRmL0s+imLyG4dnA0pf1GMp4vAbZXVBcVlYK/crDMBKiPELjzvG fmCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yc0niyL+e0o1G++JHufjcorcLLXvUhYDXt59boslzgg=; b=R5q/cvIrcEmm6M1QP7I/T3OTZ8+6RN+cykxlM+oIgx60wMl83HQrXI4ecAseBp9+D9 TTamZmRnMtS0SZpdeET0PmsSIYehMTX+zSPJg9qprc1BMTMGWCM7cfJMivv2nBqOVpCb U/fXX3fZeSiAqXnIgsfBaQDGKcDHlH0OPkYGG8Wcp/ZihA8hQUiDwYsqsQ/fHVW8SBf6 gGZ1zb4TFDgW3y/70IFo14yA+1W5RpK7LKR+vLFX2P+NBv/brkVXsvF/6WQl8X/Ze/2I SBUnwlcxgLxXBMVO5OH4pra/5k+iZxA7WhRpokKMrILCFphE980yWtmjbuNT7zTT881Q oUCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=VqXvYCt3; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u24si3676492edl.447.2019.11.07.21.20.09; Thu, 07 Nov 2019 21:20:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=VqXvYCt3; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725372AbfKHFUF (ORCPT + 8 others); Fri, 8 Nov 2019 00:20:05 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:39715 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725802AbfKHFUF (ORCPT ); Fri, 8 Nov 2019 00:20:05 -0500 Received: by mail-pl1-f193.google.com with SMTP id o9so3270427plk.6; Thu, 07 Nov 2019 21:20:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yc0niyL+e0o1G++JHufjcorcLLXvUhYDXt59boslzgg=; b=VqXvYCt3yjpIemP9x5nAW9klS4OYDVtIurvAczrm8dcH4b8jG/vIFrq7HA1zhqdEn1 WMmjWTT2tVk9wuQjqUzpDZlm/M8CCbwrETRX7+w+0nUluHW3CNl2B/iGn3Ja6NnEbsXp kf8vL/FOvPYedRq62dRG9jVGyG7wieYlyIv4oBqusl9akmvh0RKK6TKcIeooBUcOob/I H7lb4QLWxAzI8BaclZ2jWIpDuwDKY52OplmZwGyNALIK1a6EBhRcfKBfeCy2IvL3Xpao amyUwRxPbHN4UXXl8WWQKP/7RN3AW2p44AoRbPCEUf0riQEEJjiWwtQlnYHOykFdN9c8 p44g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yc0niyL+e0o1G++JHufjcorcLLXvUhYDXt59boslzgg=; b=ibpGaxS2RBIee4jXTi8/nvwlLLBgmk9C3pzjTToC0BCNOyQLSmCPb19rdZH4lT9+mY qJc4HjrDh32B7fqtb8654uS+5hbjXDJojweqCOqp+lrLuoWd2uGIs+vt6lLlKiSzoVrG Ish7EFfbu+J6Gi+k5kTdHaA2rDz2jiSYW6r5xGs1290NFcz388Oady7WlZa3IPtnXx5W hRuzsqSj6d2rtiI9JuaDtousxcmBfgOnICzBGUGfLbTRuHyqKhWOkOD5u1+HwzN/xxMM i8k6Km+yjqZFrONHAfFmIi5mMExu4xNGcVZsOwKvbyPjhy0s89YidyIkU9vmWkzyude0 TzKQ== X-Gm-Message-State: APjAAAVCsrw1hhBDXB5FcwfhL9+1MsO11E2B4JB2hGtXFkHJE2MmZw2o 0Ghr0RZ1CKASP/OWwRegca+cruJkUr91sA== X-Received: by 2002:a17:90a:9741:: with SMTP id i1mr10898615pjw.41.1573190404659; Thu, 07 Nov 2019 21:20:04 -0800 (PST) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id v19sm3798443pjr.14.2019.11.07.21.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2019 21:20:04 -0800 (PST) From: Joel Stanley To: Rob Herring , Greg KH , Jeremy Kerr Cc: Alistar Popple , Eddie James , Steven Rostedt , Ingo Molnar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 01/11] fsi: Add fsi-master class Date: Fri, 8 Nov 2019 15:49:35 +1030 Message-Id: <20191108051945.7109-2-joel@jms.id.au> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20191108051945.7109-1-joel@jms.id.au> References: <20191108051945.7109-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jeremy Kerr This change adds a device class for FSI masters, allowing access under /sys/class/fsi-master/, and easier udev rules. Signed-off-by: Jeremy Kerr Signed-off-by: Joel Stanley --- drivers/fsi/fsi-core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.24.0.rc1 Acked-by: Alistair Popple diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 1f76740f33b6..0861f6097b33 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1241,6 +1241,10 @@ static ssize_t master_break_store(struct device *dev, static DEVICE_ATTR(break, 0200, NULL, master_break_store); +struct class fsi_master_class = { + .name = "fsi-master", +}; + int fsi_master_register(struct fsi_master *master) { int rc; @@ -1249,6 +1253,7 @@ int fsi_master_register(struct fsi_master *master) mutex_init(&master->scan_lock); master->idx = ida_simple_get(&master_ida, 0, INT_MAX, GFP_KERNEL); dev_set_name(&master->dev, "fsi%d", master->idx); + master->dev.class = &fsi_master_class; rc = device_register(&master->dev); if (rc) { @@ -1350,8 +1355,15 @@ static int __init fsi_init(void) rc = bus_register(&fsi_bus_type); if (rc) goto fail_bus; + + rc = class_register(&fsi_master_class); + if (rc) + goto fail_class; + return 0; + fail_class: + bus_unregister(&fsi_bus_type); fail_bus: unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); return rc; @@ -1360,6 +1372,7 @@ postcore_initcall(fsi_init); static void fsi_exit(void) { + class_unregister(&fsi_master_class); bus_unregister(&fsi_bus_type); unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); ida_destroy(&fsi_minor_ida); From patchwork Fri Nov 8 05:19:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178850 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2158660ilf; Thu, 7 Nov 2019 21:20:11 -0800 (PST) X-Google-Smtp-Source: APXvYqz3TcnU522eh6YIBh8Zr4AFvrPyBF5F6IZ/MmnKEH+wl31l6P+eG7lkJObrINgKxEHEsE+t X-Received: by 2002:a17:906:958b:: with SMTP id r11mr7016004ejx.332.1573190411868; Thu, 07 Nov 2019 21:20:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190411; cv=none; d=google.com; s=arc-20160816; b=ouLBEau09DQRg+b0BuqePWz3XAyLkHY/6uC9Str+kY5eU8A2Dtlxl3AMLmHCCfPp/O MZkFltVq9IIOO3RbLT1T152Oue4mkv3//Ajb0FQlfNs5515cq/1E63YmNoc9QXx1KDQO IizK9OdGNmKxSoBxcqaD83UgLU9hWimJ8dEX3U+uSEuZHmpuz+TiB6XEd4OgAEsm8Yo/ MdyHfVkuaTW3jThkMYUM3HpJScvvb4FZd1NdrnpymhtsHTnCrI1Ork3/GZJTDbwgtsQG DVqlQQk2kUOBnmhJqvLNcBlhfkN3Lg/rUPPl/RagEi0otHVJ6BOCov9pmc9mBBQgzyVb 0O0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VminkHZjPJEfcePoxrblVvTvuZD1weWd1AQS3sguLYY=; b=ga7Ewli/MzPerDPULTxxEJ5z1lQmAKzM0zZFbfE0/lMLyapo4t/AxwvqKh8p50kKG4 YxtvPzTxXIkcHK55jkOrTV8uZKIs4Dq/eUnkIrOxuvOYpkA10+IqqMkRYtHhWyXPLGTD EResfJxQu78UqVelC8LajOQ9plTDASeytEWSaK6Q4OrthlWIEi/2Lk85WhDe0XTp6TGE 9n5ZodJMYxR06cmFig2zQBhgiSclUq2/IDmtXTZvaNlMvqukGfpkg4/tH/2YoVaFyFjS CIov16r/iES/wOEi2arnAgau8CyICAzvXtLkAvVOGNMTBCG5WfBcWeik19Pj5ucBNGVD 7gGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=F4Uy3yD+; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Jeremy Kerr Signed-off-by: Joel Stanley --- drivers/fsi/fsi-core.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) -- 2.24.0.rc1 Acked-by: Alistair Popple diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 0861f6097b33..c773c65a5058 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1241,8 +1241,17 @@ static ssize_t master_break_store(struct device *dev, static DEVICE_ATTR(break, 0200, NULL, master_break_store); +static struct attribute *master_attrs[] = { + &dev_attr_break.attr, + &dev_attr_rescan.attr, + NULL +}; + +ATTRIBUTE_GROUPS(master); + struct class fsi_master_class = { .name = "fsi-master", + .dev_groups = master_groups, }; int fsi_master_register(struct fsi_master *master) @@ -1261,20 +1270,6 @@ int fsi_master_register(struct fsi_master *master) return rc; } - rc = device_create_file(&master->dev, &dev_attr_rescan); - if (rc) { - device_del(&master->dev); - ida_simple_remove(&master_ida, master->idx); - return rc; - } - - rc = device_create_file(&master->dev, &dev_attr_break); - if (rc) { - device_del(&master->dev); - ida_simple_remove(&master_ida, master->idx); - return rc; - } - np = dev_of_node(&master->dev); if (!of_property_read_bool(np, "no-scan-on-init")) { mutex_lock(&master->scan_lock); From patchwork Fri Nov 8 05:19:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178852 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2158839ilf; Thu, 7 Nov 2019 21:20:22 -0800 (PST) X-Google-Smtp-Source: APXvYqzv+P0B44tz/7ISGStFWIbDVVagDv+8E4ZQzjF9nKUPWiPiEpMUAQN6OgF3v+FTtixsf7yB X-Received: by 2002:a05:6402:13cd:: with SMTP id a13mr8176610edx.57.1573190422355; Thu, 07 Nov 2019 21:20:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190422; cv=none; d=google.com; s=arc-20160816; b=01NLV7vDb82DFnIzhiEIK82+m99v+bIyTZwZAXUTNRDRYIqI62r8ntaMXq66wTtsXK /NxtGotOPvkihhfJzb9XgZValpipXTIjRevPw3pkpb1qPWs4w3W0t5qMo8SejjuIH+qh zONXcxsifNXoqy+N+a5I/Viw+Y3h6539U1BhhYjBJ6i1nPrIpLO4OcNJautlbzhGQlH0 oRg21RYVeUsx+8lRrD9L8rP7cYrKFbMnhKYDf3pKIkcA4Wo3SPnlz+84gVF3Fwmf723o x5XQYe7/UsM2PcpC0SZGMcpAd3VZz7ady/Z0BuoUTpF8nkLwu99jVYE28zduUNV6LHnb T+rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TKTqUgLFNP8L+2pgyNr2mJwmi4tnNe/kzgV9Is+uXFk=; b=BMLwST4s++DZxli4sgiFNJCwW0SiMyKm1Uy5nBhEZymUFNbJIi8Eec4Ty8LJZ5bHkm IhVRR0EXXVJYFz3vtsWpW30+3Qja+Z+PPtHRpmUeuMQEd/XDV4IRORN133r9tWp0VFxh bcQKegOQve1cBrcbNImgfiWf2A2EGjKxiZJgy2DE07H+LKCX+pw/0o/IFyBHEKT6JVmg P1cs7L0eJ4NWOz5mdmb8HvXz1wDExshdFl9R9duevGVfBBUiAZW63J51Ak8vktl1gC5Y n/u9Q+ahTuXqS6t+UEnMIumG3OsgDUHaZUcBr9rVHVg/sjMfFp+PkgFtlhEjQcbbcfyz afWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=eLIcO37R; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- include/trace/events/fsi.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.24.0.rc1 diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h index 92e5e89e52ed..9832cb8e0eb0 100644 --- a/include/trace/events/fsi.h +++ b/include/trace/events/fsi.h @@ -26,7 +26,7 @@ TRACE_EVENT(fsi_master_read, __entry->addr = addr; __entry->size = size; ), - TP_printk("fsi%d:%02d:%02d %08x[%zd]", + TP_printk("fsi%d:%02d:%02d %08x[%zu]", __entry->master_idx, __entry->link, __entry->id, @@ -56,7 +56,7 @@ TRACE_EVENT(fsi_master_write, __entry->data = 0; memcpy(&__entry->data, data, size); ), - TP_printk("fsi%d:%02d:%02d %08x[%zd] <= {%*ph}", + TP_printk("fsi%d:%02d:%02d %08x[%zu] <= {%*ph}", __entry->master_idx, __entry->link, __entry->id, @@ -93,7 +93,7 @@ TRACE_EVENT(fsi_master_rw_result, if (__entry->write || !__entry->ret) memcpy(&__entry->data, data, size); ), - TP_printk("fsi%d:%02d:%02d %08x[%zd] %s {%*ph} ret %d", + TP_printk("fsi%d:%02d:%02d %08x[%zu] %s {%*ph} ret %d", __entry->master_idx, __entry->link, __entry->id, From patchwork Fri Nov 8 05:19:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178853 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2158955ilf; Thu, 7 Nov 2019 21:20:30 -0800 (PST) X-Google-Smtp-Source: APXvYqzA41qqVpY3uHk5Pbq1ux4IbyqaQmP3WKQdkK6C96iiIlpniUroiGwLNfZ6bNMtD0L+fUpD X-Received: by 2002:aa7:c145:: with SMTP id r5mr8223689edp.102.1573190430798; Thu, 07 Nov 2019 21:20:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190430; cv=none; d=google.com; s=arc-20160816; b=KDo+WNzXJBW+AAVXUc7LTrQYieSu+2BmNzUIVTAssOx9n0c9CUvw09oKld2tAlf3RY 5GO999rFDchx2k/HcZ9iz0Gx+U2L61vO9BqiIMqDCPQwShNeiOYwQ6fv6MDrK6/rRBvU gkeBVJjSnheS12wlfYl2VUULWuCpu3m9ZS0A1lQUy0/xvSReaifK3QM8eifpNJ3gpNpq 9mGZq2Fz6tLYX1Mn2GbrCQihy2CxMSLVFJ7DR/ZNHRIS1xA6QDjySpXaq/FwEDN40cfQ tAG9hDf/gt5NzRVKKTHeKTaC+lNQtYGilz8YSKEmgp8nTYfz+lwON+V2pMTi/5CszlpU 6dVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=abrU7G2BP5v8QeCE5OZCvci6QXqITkbp0Z5/JmfzQPA=; b=QHwUga8Gl6pPuAtisNCkltA28URY1qdNl0D6FVn9NysXCwmI7jXEvyqC6P9JfIp36p 35XeEw1N7wFIUwiK+B+fjeTG6KYPXmOA1iVq3KiB1JBQTCfeQ3KpPsNHfV+gfmr7zkuY L0kswvBCwzfLKuur1I4pCOwFoEZT44BfO0nlSFVBnI57sPG2JGpLTqQ4Z23fhAzoX9cB Y6Ra1suY/wFcG6Cf5DFLkNQUWp0GlYlhMrst54s5kXr5hLmMjM3I4j7dvZnvCcg+YZ5D 4BXJw034KZzDK5T6kKut1ZW9LxuTeyhap0nBndnY7KTFuxNLFGTP89Dkp431jmi0g4x2 x1Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=XS4EhrtL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o14si3182142ejx.248.2019.11.07.21.20.30; Thu, 07 Nov 2019 21:20:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=XS4EhrtL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726125AbfKHFU0 (ORCPT + 8 others); Fri, 8 Nov 2019 00:20:26 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:42201 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727832AbfKHFU0 (ORCPT ); Fri, 8 Nov 2019 00:20:26 -0500 Received: by mail-pg1-f193.google.com with SMTP id q17so3292057pgt.9; Thu, 07 Nov 2019 21:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=abrU7G2BP5v8QeCE5OZCvci6QXqITkbp0Z5/JmfzQPA=; b=XS4EhrtLD7ira7yvelmd2Zy3twZdQh8w75/0Bvi5MIu/L4pOW3y8Uz4PCFCEcn0x2V UJRHR7EHVv4upN1s3mKOU+aXz8ou1jxdpweTYwgv4ZnBbnd7Ii4zfwrgAp55n2AvBJH3 1jhNhhQuZvooBbddpFbLmdVJs6jwPqfRAfvZpnzrHYf0XrHgX5EGpC7yIkL5+Us9WUFx BakG/iV27xw1PKS7f7ib3sHdPeWqSavpn0U224EvrUgbgOKPkXXEHgU5eVlcMk3CC16K aYQeJ7wbJ/sy2mgsQ4LVYZXgUfbtEZQm42iDbOBbjbnNadLsIbqADQtzfg1IwqX9IdC7 iKVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=abrU7G2BP5v8QeCE5OZCvci6QXqITkbp0Z5/JmfzQPA=; b=NYeyBd2IDy07Iavz8tGvYp6Twf0NJYuqy4p1gxO4t7XF7xWxzdMSlm34EyIhJuT6Wv UPcPQztEJc7XHj2k2gs4WYyd49Ddux1JAYXu7+FhBi12wNF5KlEWRwuJfZnPLRecPZAS B3L+y72NEpVtdsld12ZeD4BpUBDtSlMFOeD//Lbp6Ayw7sGpwIGz/yJYqbyztd+8t1Eu JRqfcQn+QxpVrHEWoOR+1xH4FlurUmLRqsASqQWtWaLMqxsT/5DGLtfyG+I7vt+z1qav AQOdzYtSkR1juvfm6dNwHTcpJbKXKP5ImY8gDDcS3fZwkiOE1A6Y7SpWl82/4MUIY3zo IhMg== X-Gm-Message-State: APjAAAWj2QVSr/46hU+4Q/zVWQWUMoZtXz9PBw/80q51m0Da4E2Tixsl YhkgILX+LEc5nkCbHfTaigQ= X-Received: by 2002:a63:495b:: with SMTP id y27mr9468935pgk.438.1573190425229; Thu, 07 Nov 2019 21:20:25 -0800 (PST) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id v19sm3798443pjr.14.2019.11.07.21.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2019 21:20:24 -0800 (PST) From: Joel Stanley To: Rob Herring , Greg KH , Jeremy Kerr Cc: Andrew Jeffery , Alistar Popple , Eddie James , Steven Rostedt , Ingo Molnar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 05/11] fsi: core: Fix small accesses and unaligned offsets via sysfs Date: Fri, 8 Nov 2019 15:49:39 +1030 Message-Id: <20191108051945.7109-6-joel@jms.id.au> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20191108051945.7109-1-joel@jms.id.au> References: <20191108051945.7109-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andrew Jeffery Subtracting the offset delta from four-byte alignment lead to wrapping of the requested length where `count` is less than `off`. Generalise the length handling to enable and optimise aligned access sizes for all offset and size combinations. The new formula produces the following results for given offset and count values: offset count | length --------------+------- 0 1 | 1 0 2 | 2 0 3 | 2 0 4 | 4 0 5 | 4 1 1 | 1 1 2 | 1 1 3 | 1 1 4 | 1 1 5 | 1 2 1 | 1 2 2 | 2 2 3 | 2 2 4 | 2 2 5 | 2 3 1 | 1 3 2 | 1 3 3 | 1 3 4 | 1 3 5 | 1 We might need something like this for the cfam chardevs as well, for example we don't currently implement any alignment restrictions / handling in the hardware master driver. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- drivers/fsi/fsi-core.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) -- 2.24.0.rc1 diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index c773c65a5058..e02ebcb0c9e6 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -544,6 +544,31 @@ static int fsi_slave_scan(struct fsi_slave *slave) return 0; } +static unsigned long aligned_access_size(size_t offset, size_t count) +{ + unsigned long offset_unit, count_unit; + + /* Criteria: + * + * 1. Access size must be less than or equal to the maximum access + * width or the highest power-of-two factor of offset + * 2. Access size must be less than or equal to the amount specified by + * count + * + * The access width is optimal if we can calculate 1 to be strictly + * equal while still satisfying 2. + */ + + /* Find 1 by the bottom bit of offset (with a 4 byte access cap) */ + offset_unit = BIT(__builtin_ctzl(offset | 4)); + + /* Find 2 by the top bit of count */ + count_unit = BIT(8 * sizeof(unsigned long) - 1 - __builtin_clzl(count)); + + /* Constrain the maximum access width to the minimum of both criteria */ + return BIT(__builtin_ctzl(offset_unit | count_unit)); +} + static ssize_t fsi_slave_sysfs_raw_read(struct file *file, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t off, size_t count) @@ -559,8 +584,7 @@ static ssize_t fsi_slave_sysfs_raw_read(struct file *file, return -EINVAL; for (total_len = 0; total_len < count; total_len += read_len) { - read_len = min_t(size_t, count, 4); - read_len -= off & 0x3; + read_len = aligned_access_size(off, count - total_len); rc = fsi_slave_read(slave, off, buf + total_len, read_len); if (rc) @@ -587,8 +611,7 @@ static ssize_t fsi_slave_sysfs_raw_write(struct file *file, return -EINVAL; for (total_len = 0; total_len < count; total_len += write_len) { - write_len = min_t(size_t, count, 4); - write_len -= off & 0x3; + write_len = aligned_access_size(off, count - total_len); rc = fsi_slave_write(slave, off, buf + total_len, write_len); if (rc) From patchwork Fri Nov 8 05:19:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178854 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2158994ilf; Thu, 7 Nov 2019 21:20:33 -0800 (PST) X-Google-Smtp-Source: APXvYqzLCrzjLGAGAlIko0G/fbxN6JtEED8mDzRxWvhDOPvF9wsXrkkuQerNDXqexGKguH9tnq0i X-Received: by 2002:aa7:c65a:: with SMTP id z26mr8128666edr.261.1573190432982; Thu, 07 Nov 2019 21:20:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190432; cv=none; d=google.com; s=arc-20160816; b=mhA9TM2locGrH9k8DLipYgjIKxej6Ho3E+y4tze9qnXEPWOkoQCAqSz85QlMNhvUAt NmJePp9EuY61EmnR20b48Ipke030izwAwb2Lp1xFbHtabtpXDZySj8MEFHqx7V+1ZUzn 3p84s+NjWVc4I8jlpZp7NddXDbLICL+fEXTgObUP8bXRflSOCHZZz2beaXvPOx0euHdL 5A7dDFxx8zPv3OabiQEhy4nVXGlD7+EYLunoYnUpj9h+O0TVB5WFbAWCIxKtd9v0L/lp J+6rsRebfiqraZeDEgxb6zsDYGtiu76w1zrwapDQuBYAnaTBm3Bl7NlAHRU/t3FQBzfF kHog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IsgxuNQAHTHcIJrS856EvYwzkJI0BrRT1sF+4RZoSHY=; b=BhyZ2/DVsTKbbjsDafXifN1J7fJglh/N74B3RwmC89Fvno52r1uRBBqaMDATNC9gIw ZZEMuPHvFNfJGPsJJueorXqGoT+sjm4VlchRg/dAXsN2xA0hbfaLziHEr8+Kcdo2LPUj G3EhPeE0jLMnfigZdLTSZekJ5znm/7syCtxeG4bpLzCp1sR2Cqpj/fso5yTnuW2tdcGo vdrM2eVHD1IHFn/ulJ1XhU77RGJh/rj2ffQBo2kpXcLDL28+KnKPb00xEKUUO9BRgJcx tCe4N4wlH/TEmaelsLTn+QK7lM9/gmhb6sdkI19suj2pBmRH6r9BkAHaaiHsHHqxG3DO kNog== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=OU9az6yy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fixes: 0604d53d4da8 ("fsi: Add fsi-master class") Signed-off-by: kbuild test robot Signed-off-by: Joel Stanley --- drivers/fsi/fsi-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.24.0.rc1 diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index e02ebcb0c9e6..8244da8a7241 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1272,7 +1272,7 @@ static struct attribute *master_attrs[] = { ATTRIBUTE_GROUPS(master); -struct class fsi_master_class = { +static struct class fsi_master_class = { .name = "fsi-master", .dev_groups = master_groups, }; From patchwork Fri Nov 8 05:19:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178856 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2159154ilf; Thu, 7 Nov 2019 21:20:45 -0800 (PST) X-Google-Smtp-Source: APXvYqxnipcF8sKqaPjJes/A9F0lmt9VWTyksBwUPIkJfnxJg8wx+XvOuoUb/gbAq54K3EgdEVhv X-Received: by 2002:a17:906:1342:: with SMTP id x2mr7007924ejb.304.1573190445707; Thu, 07 Nov 2019 21:20:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190445; cv=none; d=google.com; s=arc-20160816; b=tcd1DE4o44/+6FvJDVeM142tw25gn1z/YmCFpnRGhNtqRF11fEDn+qhnHyCl+xes3l xT7uN2x4cUgJjSp7Fztm84j7srGwsRsy5EJlo5s053M+UeGiGrmzvvqDLHf5w93kw6yE FakS4XHdoLa9gsAPsORdVi0U71P1kjgM1rDusiE5n+faxwvLPUzpRbJEfmLn/b1K6JZP q440IjjBo6F4OuJbEgIsLZl92WHrD37Kl3KJESFc22q189FIavlVv+LCKL2BLetzLslM qGPlszl1y7Ls0VcXNaUUK4YFHpjVHh+SgaN/gEFCzs0gpDPImstZGuBp+U1ag2/dZznt DA3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iGEIDbYmVZa9xwEGk6m/vD8N0Ug2Lhly+4TWkAdqLek=; b=MCtjLWhXkn3fKpxbDl6UjEdDMSt9AXAmwSIQT9X4rVl4H65A3/Ez081OjqU+VRITN0 lAzdDPwLs0qfAjD70cOXIlFj6Wa8iAUsMkK5DDYzibszKfqis13I/36yphvlY5dqTXdG Gc7mdUUvfFISEXXah92c8CmLVFIE0Fa2XbK3kAs5DMp7AslBofXuj6xuIqLDdNfUkU2n Ka3iMsUtrZHmsgAeJ9oKG5j4xkLCEtp+1IDNLMO+o8wPVhAJo2R8sUC47l1W/hBFd482 sP1Eyn+7H2OvokDGtmVnKSIax5Yfh87vWzFRSVaSfYNeGcsPFwTxr6yABbP5rFYzanD0 BYDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=DQV4QErw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ot13si223536ejb.199.2019.11.07.21.20.45; Thu, 07 Nov 2019 21:20:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=DQV4QErw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727832AbfKHFUp (ORCPT + 8 others); Fri, 8 Nov 2019 00:20:45 -0500 Received: from mail-pl1-f180.google.com ([209.85.214.180]:45971 "EHLO mail-pl1-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726480AbfKHFUo (ORCPT ); Fri, 8 Nov 2019 00:20:44 -0500 Received: by mail-pl1-f180.google.com with SMTP id y24so3253288plr.12; Thu, 07 Nov 2019 21:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iGEIDbYmVZa9xwEGk6m/vD8N0Ug2Lhly+4TWkAdqLek=; b=DQV4QErwJZi1nk+I+ExV4GgrAt+hvlcVydeGwaA7/epaVfYBs5u+HOBas9IumvCH3N JxSoAVsemwQmhL9lwpjUyMccGjyCWAW8DMxKTol2RUQoNpM2zOk91ztHOozH88yCXnyS nQiyemAGRfY5zntLTi69NaA4DiECMQuM9cq9WdGTiSpag2j2HasNUGlKW0w9R5revTGH wvMIlyXkvzCyDczcv3X6NokPLYkJj8lxtymgsnm77GRivHxrwy3Wi2/uWPUWCQ7ka4u6 P+8I074TJg0IbfKtoUmk7RQLoOBZytBQn4RkJywcfMiFBonHKqy1FHK7keHZCkf2uKMz SZTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iGEIDbYmVZa9xwEGk6m/vD8N0Ug2Lhly+4TWkAdqLek=; b=ekji1qR0um3DPy+zsbaiLTqRLRFnKDvshyv92shtghVDbh0KL/tX/9x5Xnloe2/JtU oXAzpV7rhFWf6tNRPLqz7Z+2hqHMVYl1QrnlpHDNq5fcdXVBjtTy9I4XN0FVer+3PC9k LHcVBjw2PFOZbpLdDBSSI5VRfWRH45zQdGLr/WNIFOpkEWY9FLFRPegsTWP9LxMkDfyi kF2cI460mS2Emws/b2MQ6icmxrJXK4Q3qp40qmBIgZGRW+AIVA/HzrKChxRsYlwnKpOv LlOZz0ObCE57bY26xDFjRJm8zD/eiXFmikBqC91q2+5PCPOyEMVZIWRAVPHAZb/5bkJq SgyQ== X-Gm-Message-State: APjAAAUQlaUW3HuCXWRnmzv1b6gN+OOYeCj6reox0nSDxcvl3CxWR+x/ wfx0kWdufTB6rSbaoCqBdKA= X-Received: by 2002:a17:902:ba91:: with SMTP id k17mr8454858pls.100.1573190443329; Thu, 07 Nov 2019 21:20:43 -0800 (PST) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id v19sm3798443pjr.14.2019.11.07.21.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2019 21:20:42 -0800 (PST) From: Joel Stanley To: Rob Herring , Greg KH , Jeremy Kerr Cc: Alistar Popple , Eddie James , Steven Rostedt , Ingo Molnar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 08/11] dt-bindings: fsi: Add description of FSI master Date: Fri, 8 Nov 2019 15:49:42 +1030 Message-Id: <20191108051945.7109-9-joel@jms.id.au> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20191108051945.7109-1-joel@jms.id.au> References: <20191108051945.7109-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the FSI master present in the AST2600. Signed-off-by: Joel Stanley --- .../bindings/fsi/fsi-master-aspeed.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt -- 2.24.0.rc1 Acked-by: Alistair Popple diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt b/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt new file mode 100644 index 000000000000..b758f91914f7 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt @@ -0,0 +1,24 @@ +Device-tree bindings for AST2600 FSI master +------------------------------------------- + +The AST2600 contains two identical FSI masters. They share a clock and have a +separate interrupt line and output pins. + +Required properties: + - compatible: "aspeed,ast2600-fsi-master" + - reg: base address and length + - clocks: phandle and clock number + - interrupts: platform dependent interrupt description + - pinctrl-0: phandle to pinctrl node + - pinctrl-names: pinctrl state + +Examples: + + fsi-master { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b000 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + }; From patchwork Fri Nov 8 05:19:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178857 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2159261ilf; Thu, 7 Nov 2019 21:20:51 -0800 (PST) X-Google-Smtp-Source: APXvYqxvJIZ5I0MKzw5309sc+p1CLajSieApTOouL2Z0KHPhO6lzeHNrHMU4bDh+hFd4LX/pZPLp X-Received: by 2002:a17:906:505:: with SMTP id j5mr6940688eja.167.1573190451721; Thu, 07 Nov 2019 21:20:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190451; cv=none; d=google.com; s=arc-20160816; b=B/fW/I3VJR1Ja/dVV8nt+x9JtoUtpMFSkRKnYw9a+VHbM3oEHm57QoEzhJlModJgkI C1JaG6IbM/lKOLte+32rhgIeVwY+582+bBtXMrD4o5vaMv24ShzvaJOzlxnbBhkRtgw4 RXmbR4Nff2/2A7BFF0dBh4wTSJW7CVMlAPBijHSxSWsoPCpLlK1yPfYx/445w2+I+ikr Bc+JtuqaeIdRSb2dHBC1zQUyk/enm/sNuYtTX0IuHIt6IRUFGoFp2uVg6fgP11XXZUl+ 8fv/HAIr+I1IGgXoZKIw9ttQ8fNNbI4ppX534uxtyfEX4rtvL4EAzBpP0jLaKPauLk8t kThw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=75+GBsm3s/u8w6X4ShxUr5jXVzQl8E1Ldm8VDSkE0ok=; b=qR9ZJisYVpptaQ0n29xnlNmtd4lg8Tjv6nzg1fv1CJjKuaIxfn0b+yEfrTc+aoDsd1 D61o+0MPb9v4nDFWhTPB2Vbn/Q35vTDDLVwhmm7nsXoi3fegrk5AX2FQ8UxK6XQnMqhU 1qS10UXK5PQNDTrqp/gyUyhX5eqN/QcSl8tlGEaTW4LpHwkEbadKKi3T7vyXoDiROU3N vZC0ksUABzJmRxaltMOOaP/OEPukACIZWDpOSlZ57dbBb4qVAM4dw7f6VRdrH9yqWUaY wXE5Tpf2oKSTTcHB/xYpd0a+efjX12+kfKRrGXCmLd6f9BgrLZ+WXVCvEuMZr6a52pEF RMHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=aRwHnnd9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t17si2988244ejj.144.2019.11.07.21.20.51; Thu, 07 Nov 2019 21:20:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=aRwHnnd9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730059AbfKHFUu (ORCPT + 8 others); Fri, 8 Nov 2019 00:20:50 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33704 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730040AbfKHFUt (ORCPT ); Fri, 8 Nov 2019 00:20:49 -0500 Received: by mail-pl1-f195.google.com with SMTP id ay6so3300156plb.0; Thu, 07 Nov 2019 21:20:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=75+GBsm3s/u8w6X4ShxUr5jXVzQl8E1Ldm8VDSkE0ok=; b=aRwHnnd9+o9vNBa90kdKBJ5woCmX7y7E1jRHJtYC1NZ8YE6nFGm48L1pZXuxzClkmF YVZ0nBgMu9g4wIZvjpvTyqev4ABDxMKThxtSkgPYVlJx0ei+cfm15xOMVh0451Q7M/5M LvzwCEc2ha9KyP18JOufPWlSpxoM0X9q4Gghmz1mqw/RkZb1qhxwbrkewWEcgv+eRzVp TyEwoGJRnpODDSMVlzoL6/MKK2Rfpx5gVgZhqGSmIh+uJj3rjz4Ms91BLUIA850pvmqM weUqauZ5OpopcankkksJHF2fNTNpN/ovE40bD/RUvJnwzIshPO4Z3ke/kkPDpQSWAIir 1NHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=75+GBsm3s/u8w6X4ShxUr5jXVzQl8E1Ldm8VDSkE0ok=; b=JtfsOTgWMFvdKTLO4ejRTIEURLc2FCTOFaRgyQrctLIDitk1MhxYWXQ0CK7uuC53ag NFlpeQWnuXkWL7wyOgjeX0JVxM6y6/oZ8/ho977gmY/msm+oLosVQW1SURhuoGD+1VMG qEgp2YsXC88yigAWAhzxaVg/49tdyBzDp+4Vyg4BeQpk5NndedMetQMDXEp+UTkc6iq7 aLoy3cUybuNaDKIOUbJgAwdE3/XhMSKUj8/QskxG7EufNNAv8F8GXvlJhSkMmsodOPEz 16W8CUwe5RFV5WTnreNmWE9fwXcKS0ZigckP0dkLMyjUybpIMnk6/TPe1jyLa6cnbuZj lD7g== X-Gm-Message-State: APjAAAUF7YUNIeD0IEq6xXQGnLBW/TxSQs7o90JHcrb6x68eFEvwI0fZ PRruzHAJk3w88H7AyT2SBs4= X-Received: by 2002:a17:902:bb8f:: with SMTP id m15mr4846211pls.121.1573190448378; Thu, 07 Nov 2019 21:20:48 -0800 (PST) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id v19sm3798443pjr.14.2019.11.07.21.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2019 21:20:47 -0800 (PST) From: Joel Stanley To: Rob Herring , Greg KH , Jeremy Kerr Cc: Alistar Popple , Eddie James , Steven Rostedt , Ingo Molnar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 09/11] fsi: Add ast2600 master driver Date: Fri, 8 Nov 2019 15:49:43 +1030 Message-Id: <20191108051945.7109-10-joel@jms.id.au> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20191108051945.7109-1-joel@jms.id.au> References: <20191108051945.7109-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ast2600 BMC has a pair of FSI masters in it, behind an AHB to OPB bridge. The master driver supports reads and writes of full words, half word and byte accesses to remote CFAMs. It can perform very basic error recovery through resetting of the FSI port when an error is detected, and the issuing of breaks and terms. Signed-off-by: Joel Stanley -- v2: - remove debugging - squash in fixes --- drivers/fsi/Kconfig | 8 + drivers/fsi/Makefile | 1 + drivers/fsi/fsi-master-aspeed.c | 522 ++++++++++++++++++++++++++++++++ 3 files changed, 531 insertions(+) create mode 100644 drivers/fsi/fsi-master-aspeed.c -- 2.24.0.rc1 Acked-by: Alistair Popple diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index c612db7a914a..92ce6d85802c 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -53,6 +53,14 @@ config FSI_MASTER_AST_CF lines driven by the internal ColdFire coprocessor. This requires the corresponding machine specific ColdFire firmware to be available. +config FSI_MASTER_ASPEED + tristate "FSI ASPEED master" + help + This option enables a FSI master that is present behind an OPB bridge + in the AST2600. + + Enable it for your BMC kernel in an OpenPower or IBM Power system. + config FSI_SCOM tristate "SCOM FSI client device driver" ---help--- diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile index e4a2ff043c32..da218a1ad8e1 100644 --- a/drivers/fsi/Makefile +++ b/drivers/fsi/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_FSI) += fsi-core.o obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o +obj-$(CONFIG_FSI_MASTER_ASPEED) += fsi-master-aspeed.o obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o obj-$(CONFIG_FSI_SCOM) += fsi-scom.o diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c new file mode 100644 index 000000000000..d1b83f035483 --- /dev/null +++ b/drivers/fsi/fsi-master-aspeed.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (C) IBM Corporation 2018 +// FSI master driver for AST2600 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsi-master.h" + +struct fsi_master_aspeed { + struct fsi_master master; + struct device *dev; + void __iomem *base; + struct clk *clk; +}; + +#define to_fsi_master_aspeed(m) \ + container_of(m, struct fsi_master_aspeed, master) + +/* Control register (size 0x400) */ +static const u32 ctrl_base = 0x80000000; + +static const u32 fsi_base = 0xa0000000; + +#define OPB_FSI_VER 0x00 +#define OPB_TRIGGER 0x04 +#define OPB_CTRL_BASE 0x08 +#define OPB_FSI_BASE 0x0c +#define OPB_CLK_SYNC 0x3c +#define OPB_IRQ_CLEAR 0x40 +#define OPB_IRQ_MASK 0x44 +#define OPB_IRQ_STATUS 0x48 + +#define OPB0_SELECT 0x10 +#define OPB0_RW 0x14 +#define OPB0_XFER_SIZE 0x18 +#define OPB0_FSI_ADDR 0x1c +#define OPB0_FSI_DATA_W 0x20 +#define OPB0_STATUS 0x80 +#define OPB0_FSI_DATA_R 0x84 + +#define OPB0_WRITE_ORDER1 0x4c +#define OPB0_WRITE_ORDER2 0x50 +#define OPB1_WRITE_ORDER1 0x54 +#define OPB1_WRITE_ORDER2 0x58 +#define OPB0_READ_ORDER1 0x5c +#define OPB1_READ_ORDER2 0x60 + +#define OPB_RETRY_COUNTER 0x64 + +/* OPBn_STATUS */ +#define STATUS_HALFWORD_ACK BIT(0) +#define STATUS_FULLWORD_ACK BIT(1) +#define STATUS_ERR_ACK BIT(2) +#define STATUS_RETRY BIT(3) +#define STATUS_TIMEOUT BIT(4) + +/* OPB_IRQ_MASK */ +#define OPB1_XFER_ACK_EN BIT(17) +#define OPB0_XFER_ACK_EN BIT(16) + +/* OPB_RW */ +#define CMD_READ BIT(0) +#define CMD_WRITE 0 + +/* OPBx_XFER_SIZE */ +#define XFER_FULLWORD (BIT(1) | BIT(0)) +#define XFER_HALFWORD (BIT(0)) +#define XFER_BYTE (0) + +#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ + +#define DEFAULT_DIVISOR 14 +#define OPB_POLL_TIMEOUT 10000 + +static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, + u32 val, u32 transfer_size) +{ + void __iomem *base = aspeed->base; + u32 reg, status; + int ret; + + writel(CMD_WRITE, base + OPB0_RW); + writel(transfer_size, base + OPB0_XFER_SIZE); + writel(addr, base + OPB0_FSI_ADDR); + writel(val, base + OPB0_FSI_DATA_W); + writel(0x1, base + OPB_IRQ_CLEAR); + writel(0x1, base + OPB_TRIGGER); + + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, + (reg & OPB0_XFER_ACK_EN) != 0, + 0, OPB_POLL_TIMEOUT); + + status = readl(base + OPB0_STATUS); + + /* Return error when poll timed out */ + if (ret) + return ret; + + /* Command failed, master will reset */ + if (status & STATUS_ERR_ACK) + return -EIO; + + return 0; +} + +static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val) +{ + return __opb_write(aspeed, addr, val, XFER_BYTE); +} + +static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val) +{ + return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD); +} + +static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val) +{ + return __opb_write(aspeed, addr, (__force u32)val, XFER_FULLWORD); +} + +static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, + u32 transfer_size, void *out) +{ + void __iomem *base = aspeed->base; + u32 result, reg; + int status, ret; + + writel(CMD_READ, base + OPB0_RW); + writel(transfer_size, base + OPB0_XFER_SIZE); + writel(addr, base + OPB0_FSI_ADDR); + writel(0x1, base + OPB_IRQ_CLEAR); + writel(0x1, base + OPB_TRIGGER); + + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, + (reg & OPB0_XFER_ACK_EN) != 0, + 0, OPB_POLL_TIMEOUT); + + status = readl(base + OPB0_STATUS); + + result = readl(base + OPB0_FSI_DATA_R); + + /* Return error when poll timed out */ + if (ret) + return ret; + + /* Command failed, master will reset */ + if (status & STATUS_ERR_ACK) + return -EIO; + + if (out) { + switch (transfer_size) { + case XFER_BYTE: + *(u8 *)out = result; + break; + case XFER_HALFWORD: + *(u16 *)out = result; + break; + case XFER_FULLWORD: + *(u32 *)out = result; + break; + default: + return -EINVAL; + } + + } + + return 0; +} + +static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out) +{ + return __opb_read(aspeed, addr, XFER_FULLWORD, out); +} + +static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out) +{ + return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out); +} + +static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out) +{ + return __opb_read(aspeed, addr, XFER_BYTE, (void *)out); +} + +static int check_errors(struct fsi_master_aspeed *aspeed, int err) +{ + int ret; + + if (err == -EIO) { + /* Check MAEB (0x70) ? */ + + /* Then clear errors in master */ + ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, + cpu_to_be32(FSI_MRESP_RST_ALL_MASTER)); + if (ret) { + /* TODO: log? return different code? */ + return ret; + } + /* TODO: confirm that 0x70 was okay */ + } + + /* This will pass through timeout errors */ + return err; +} + +static int aspeed_master_read(struct fsi_master *master, int link, + uint8_t id, uint32_t addr, void *val, size_t size) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + int ret; + + if (id != 0) + return -EINVAL; + + addr += link * FSI_HUB_LINK_SIZE; + + switch (size) { + case 1: + ret = opb_readb(aspeed, fsi_base + addr, val); + break; + case 2: + ret = opb_readw(aspeed, fsi_base + addr, val); + break; + case 4: + ret = opb_readl(aspeed, fsi_base + addr, val); + break; + default: + return -EINVAL; + } + + ret = check_errors(aspeed, ret); + if (ret) + return ret; + + return 0; +} + +static int aspeed_master_write(struct fsi_master *master, int link, + uint8_t id, uint32_t addr, const void *val, size_t size) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + int ret; + + if (id != 0) + return -EINVAL; + + addr += link * FSI_HUB_LINK_SIZE; + + switch (size) { + case 1: + ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val); + break; + case 2: + ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val); + break; + case 4: + ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val); + break; + default: + return -EINVAL; + } + + ret = check_errors(aspeed, ret); + if (ret) + return ret; + + return 0; +} + +static int aspeed_master_link_enable(struct fsi_master *master, int link) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + int idx, bit, ret; + __be32 reg, result; + + idx = link / 32; + bit = link % 32; + + reg = cpu_to_be32(0x80000000 >> bit); + + ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg); + if (ret) + return ret; + + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + ret = opb_readl(aspeed, ctrl_base + FSI_MENP0 + (4 * idx), &result); + if (ret) + return ret; + + if (result != reg) { + dev_err(aspeed->dev, "%s failed: %08x\n", __func__, result); + return -EIO; + } + + return 0; +} + +static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id) +{ + uint32_t addr; + __be32 cmd; + + addr = 0x4; + cmd = cpu_to_be32(0xecc00000); + + return aspeed_master_write(master, link, id, addr, &cmd, 4); +} + +static int aspeed_master_break(struct fsi_master *master, int link) +{ + uint32_t addr; + __be32 cmd; + + addr = 0x0; + cmd = cpu_to_be32(0xc0de0000); + + return aspeed_master_write(master, link, 0, addr, &cmd, 4); +} + +static void aspeed_master_release(struct device *dev) +{ + struct fsi_master_aspeed *aspeed = + to_fsi_master_aspeed(dev_to_fsi_master(dev)); + + kfree(aspeed); +} + +/* mmode encoders */ +static inline u32 fsi_mmode_crs0(u32 x) +{ + return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; +} + +static inline u32 fsi_mmode_crs1(u32 x) +{ + return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; +} + +static int aspeed_master_init(struct fsi_master_aspeed *aspeed) +{ + __be32 reg; + + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); + + /* Initialize the MFSI (hub master) engine */ + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); + + reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); + opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); + + reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA + | fsi_mmode_crs0(DEFAULT_DIVISOR) + | fsi_mmode_crs1(DEFAULT_DIVISOR) + | FSI_MMODE_P8_TO_LSB); + opb_writel(aspeed, ctrl_base + FSI_MMODE, reg); + + reg = cpu_to_be32(0xffff0000); + opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg); + + reg = cpu_to_be32(~0); + opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg); + + /* Leave enabled long enough for master logic to set up */ + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg); + + opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL); + + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); + + opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL); + + /* Reset the master bridge */ + reg = cpu_to_be32(FSI_MRESB_RST_GEN); + opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); + + reg = cpu_to_be32(FSI_MRESB_RST_ERR); + opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); + + return 0; +} + +static int fsi_master_aspeed_probe(struct platform_device *pdev) +{ + struct fsi_master_aspeed *aspeed; + struct resource *res; + int rc, links, reg; + __be32 raw; + + aspeed = devm_kzalloc(&pdev->dev, sizeof(*aspeed), GFP_KERNEL); + if (!aspeed) + return -ENOMEM; + + aspeed->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + aspeed->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(aspeed->base)) + return PTR_ERR(aspeed->base); + + aspeed->clk = devm_clk_get(aspeed->dev, NULL); + if (IS_ERR(aspeed->clk)) { + dev_err(aspeed->dev, "couldn't get clock\n"); + return PTR_ERR(aspeed->clk); + } + rc = clk_prepare_enable(aspeed->clk); + if (rc) { + dev_err(aspeed->dev, "couldn't enable clock\n"); + return rc; + } + + writel(0x1, aspeed->base + OPB_CLK_SYNC); + writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN, + aspeed->base + OPB_IRQ_MASK); + + /* TODO: determine an appropriate value */ + writel(0x10, aspeed->base + OPB_RETRY_COUNTER); + + writel(ctrl_base, aspeed->base + OPB_CTRL_BASE); + writel(fsi_base, aspeed->base + OPB_FSI_BASE); + + /* Set read data order */ + writel(0x0011bb1b, aspeed->base + OPB0_READ_ORDER1); + + /* Set write data order */ + writel(0x0011bb1b, aspeed->base + OPB0_WRITE_ORDER1); + writel(0xffaa5500, aspeed->base + OPB0_WRITE_ORDER2); + + /* + * Select OPB0 for all operations. + * Will need to be reworked when enabling DMA or anything that uses + * OPB1. + */ + writel(0x1, aspeed->base + OPB0_SELECT); + + rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw); + if (rc) { + dev_err(&pdev->dev, "failed to read hub version\n"); + return rc; + } + + reg = be32_to_cpu(raw); + links = (reg >> 8) & 0xff; + dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links); + + aspeed->master.dev.parent = &pdev->dev; + aspeed->master.dev.release = aspeed_master_release; + aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev)); + + aspeed->master.n_links = links; + aspeed->master.read = aspeed_master_read; + aspeed->master.write = aspeed_master_write; + aspeed->master.send_break = aspeed_master_break; + aspeed->master.term = aspeed_master_term; + aspeed->master.link_enable = aspeed_master_link_enable; + + dev_set_drvdata(&pdev->dev, aspeed); + + aspeed_master_init(aspeed); + + rc = fsi_master_register(&aspeed->master); + if (rc) + goto err_release; + + /* At this point, fsi_master_register performs the device_initialize(), + * and holds the sole reference on master.dev. This means the device + * will be freed (via ->release) during any subsequent call to + * fsi_master_unregister. We add our own reference to it here, so we + * can perform cleanup (in _remove()) without it being freed before + * we're ready. + */ + get_device(&aspeed->master.dev); + return 0; + +err_release: + clk_disable_unprepare(aspeed->clk); + return rc; +} + +static int fsi_master_aspeed_remove(struct platform_device *pdev) +{ + struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev); + + fsi_master_unregister(&aspeed->master); + clk_disable_unprepare(aspeed->clk); + + return 0; +} + +static const struct of_device_id fsi_master_aspeed_match[] = { + { .compatible = "aspeed,ast2600-fsi-master" }, + { }, +}; + +static struct platform_driver fsi_master_aspeed_driver = { + .driver = { + .name = "fsi-master-aspeed", + .of_match_table = fsi_master_aspeed_match, + }, + .probe = fsi_master_aspeed_probe, + .remove = fsi_master_aspeed_remove, +}; + +module_platform_driver(fsi_master_aspeed_driver); +MODULE_LICENSE("GPL"); From patchwork Fri Nov 8 05:19:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 178859 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp2159450ilf; Thu, 7 Nov 2019 21:21:03 -0800 (PST) X-Google-Smtp-Source: APXvYqwUt5JaMEazi4mnYW0nFH0aOYv10yWLZfLs0HL8OEoibHuEDPyewADHhaTHu5fWCTqFAa6Z X-Received: by 2002:aa7:c887:: with SMTP id p7mr8040940eds.268.1573190462996; Thu, 07 Nov 2019 21:21:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573190462; cv=none; d=google.com; s=arc-20160816; b=ZlMO5vFZ851MZTfjFypqaIRArrkHfOFzfWbVrt64IzpbwmfVlheCB2pO1LCqrV4k4n W7B0jxmCu0NYioDT+CLsNoiWTmpv/Wc99StlzPUg9ZJxrL3Hvffhj9szwQIlBpwKWv71 4/prPigaJQXIMxhPSEbeYUYZ4zTWEwMb8Ls/+AT3P54sSO3H6HxPGpbjeOIKSO5wMZwI rzqjblORW3t/AYy/mw6HVcUPyOoxAVyqD/PPJ9WIybJy4vZD0WQimgAjoy+UC1sMOtVl KXNexI+evqKK5GFhJJjGI5u1bmWfVDwxmjxdhRatZHkBwwmNwG6gneFVMksitw5NAkQP AoIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pGFx+amGu93F2A50py9iOALjdTJpw7/ItloLfCzH0sg=; b=umZmiNy2ukt1w9G5LWuC3CpmhiGfIuvuKLGCPc3cciMZfzCIIk0RSffSyYg5RuS1io TXePZKkf4k4H5uM48+fTkdYAXX2ocfVeGbFQdJr8IIodQiQUkYQ8VS/aaQtEz3RybBle Ft/TZ/b5/YEhJH6PNB5EIcJ6verHFTxPoCt9myuDA02l+OeF3zYrsNuUCQxNdEhYkuW7 gvnSycTWJttnDEm3NWhWBW25x5ccpnN7XkQXBWGEwMAFa+/hDOeK5ELzRHwoGD4xYzLZ YMKUtQY7xHVwJslwhZz0SKh+ER4oQsmhQYSjG9BtEWmfgydXN4711aqwPnnWozlLRdNE 7vPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=FxjdFP0W; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s7si3712478eds.215.2019.11.07.21.21.02; Thu, 07 Nov 2019 21:21:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=FxjdFP0W; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725877AbfKHFVC (ORCPT + 8 others); Fri, 8 Nov 2019 00:21:02 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34791 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725730AbfKHFVB (ORCPT ); Fri, 8 Nov 2019 00:21:01 -0500 Received: by mail-pf1-f195.google.com with SMTP id n13so3911965pff.1; Thu, 07 Nov 2019 21:20:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pGFx+amGu93F2A50py9iOALjdTJpw7/ItloLfCzH0sg=; b=FxjdFP0WXWrfIrLD+8gcWy/umEQbWOunx9yjkSz/LLLs4K/VyjyX0EgEYa5CMm5F6w SAUoch3awY5CzsHatHgtVRC9h1rmotllGqaN7eQVFoLIwA4Q7Zfr1e8Z2B18dGZ8xAu8 QoYbA/t5omu9u3U2icdTWcCYwlPbKzMHqD+IgJulOgosUZgxH5W3MHmYQI71tuBjOFFx BR8e64XCMSY5iGEB4Z+DLlWTaRinUpFPqPcq4EDdv7x59vVinY1VwRfkEjmIHzX0rDCi +62w0PF625kC9XHstmRDdqFR5vEHmEAF85ioDHVJZVjWR+jFhBb7oYGuTP7cAbiCvHCX TScg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pGFx+amGu93F2A50py9iOALjdTJpw7/ItloLfCzH0sg=; b=EdKyxzsWvPDMvN8XpZcmpbIcdgYO6f6rCRytxfyQWlAIeBjNpa4VvfHLvj8exCWAHI 3FyGZRKYrDIJOZGsL7XrfriftSDcXBVLOkCdkvtb6HW3aeHNHD4C0LmYfJ9DCQvzERvg 3Ex7zamrQv1XjxQh6NYU4cV9Dde+EMC8L9/Y7JwKnLS680vM0uFyxypKDi1Mh8Zm1Mbc stK2pR8HV7zC50ADaG+T2rV85yGxeEfHQ3HThHuWzg8AuaTbzN56kPBElSe1a3bWciXk 2LYZv1zvgapvmfsX7XcEu9r2Cw3tm9u3hx7v8s2N/ELjunUl73mPyR4itUWnlYfma6lN 5f6Q== X-Gm-Message-State: APjAAAUeEIjlls39I0r/5S5tj9x7QP6VN6mvN3BPmW/wu5a9FsXmbV9v ZbqylMuNPRIKnP1wYckKMKs= X-Received: by 2002:a63:234c:: with SMTP id u12mr9244517pgm.384.1573190458914; Thu, 07 Nov 2019 21:20:58 -0800 (PST) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id v19sm3798443pjr.14.2019.11.07.21.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2019 21:20:58 -0800 (PST) From: Joel Stanley To: Rob Herring , Greg KH , Jeremy Kerr Cc: Andrew Jeffery , Alistar Popple , Eddie James , Steven Rostedt , Ingo Molnar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 11/11] fsi: aspeed: Fix OPB0 byte order register values Date: Fri, 8 Nov 2019 15:49:45 +1030 Message-Id: <20191108051945.7109-12-joel@jms.id.au> X-Mailer: git-send-email 2.24.0.rc1 In-Reply-To: <20191108051945.7109-1-joel@jms.id.au> References: <20191108051945.7109-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andrew Jeffery The data byte order selection registers in the APB2OPB primarily expose some internal plumbing necessary to get correct write accesses onto the OPB. OPB write cycles require "data mirroring" across the 32-bit data bus to support variable data width slaves that don't implement "byte enables". For slaves that do implement byte enables the master can signal which bytes on the data bus the slave should consider valid. The data mirroring behaviour is specified by the following table: +-----------------+----------+-----------------------------------+ | | | 32-bit Data Bus | +---------+-------+----------+---------+---------+-------+-------+ | | | | | | | | | ABus | Mn_BE | Request | Dbus | Dbus | Dbus | Dbus | | (30:31) | (0:3) | Transfer | 0:7 | 8:15 | 16:23 | 24:31 | | | | Size | byte0 | byte1 | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1111 | fullword | byte0 | byte1 | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1110 | halfword | byte0 | byte1 | byte2 | | +---------+-------+----------+---------+---------+-------+-------+ | 01 | 0111 | byte | _byte1_ | byte1 | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1100 | halfword | byte0 | byte1 | | | +---------+-------+----------+---------+---------+-------+-------+ | 01 | 0110 | byte | _byte1_ | byte1 | byte2 | | +---------+-------+----------+---------+---------+-------+-------+ | 10 | 0011 | halfword | _byte2_ | _byte3_ | byte2 | byte3 | +---------+-------+----------+---------+---------+-------+-------+ | 00 | 1000 | byte | byte0 | | | | +---------+-------+----------+---------+---------+-------+-------+ | 01 | 0100 | byte | _byte1_ | byte1 | | | +---------+-------+----------+---------+---------+-------+-------+ | 10 | 0010 | byte | _byte2_ | | byte2 | | +---------+-------+----------+---------+---------+-------+-------+ | 11 | 0001 | byte | _byte3_ | _byte3_ | | byte3 | +---------+-------+----------+---------+---------+-------+-------+ Mirrored data values are highlighted by underscores in the Dbus columns. The values in the ABus and Request Transfer Size columns correspond to values in the field names listed in the write data order select register descriptions. Similar configuration registers are exposed for reads which enables the secondary purpose of configuring hardware endian conversions. It appears the data bus byte order is switched around in hardware so set the registers such that we can access the correct values for all widths. The values were determined by experimentation on hardware against fixed CFAM register values to configure the read data order, then in combination with the table above and the register layout documentation in the AST2600 datasheet performing write/read cycles to configure the write data order registers. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- drivers/fsi/fsi-master-aspeed.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.24.0.rc1 diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index 95e226ac78b9..f49742b310c2 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -459,11 +459,11 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev) writel(fsi_base, aspeed->base + OPB_FSI_BASE); /* Set read data order */ - writel(0x0011bb1b, aspeed->base + OPB0_READ_ORDER1); + writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1); /* Set write data order */ - writel(0x0011bb1b, aspeed->base + OPB0_WRITE_ORDER1); - writel(0xffaa5500, aspeed->base + OPB0_WRITE_ORDER2); + writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1); + writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2); /* * Select OPB0 for all operations.