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Sat, 3 Aug 2024 03:23:11 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:05 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:47 +0530 Subject: [PATCH v2 1/8] dt-bindings: PCI: Add binding for qps615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-1-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Signed-off-by: Krishna chaitanya chundru --- .../devicetree/bindings/pci/qcom,qps615.yaml | 191 +++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,qps615.yaml b/Documentation/devicetree/bindings/pci/qcom,qps615.yaml new file mode 100644 index 000000000000..ea0c953ee56f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,qps615.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,qps615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPS615 PCIe switch + +maintainers: + - Krishna chaitanya chundru + +description: | + Qualcomm QPS615 PCIe switch has one upstream and three downstream + ports. The 3rd downstream port has integrated endpoint device of + Ethernet MAC. Other two downstream ports are supposed to connect + to external device. + + The QPS615 PCIe switch can be configured through I2C interface before + PCIe link is established to change FTS, ASPM related entry delays, + tx amplitude etc for better power efficiency and functionality. + +properties: + compatible: + enum: + - pci1179,0623 + + reg: + maxItems: 1 + + qcom,qps615-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Reference to the I2C client used to do configure qps615 + + vdd18-supply: true + + vdd09-supply: true + + vddc-supply: true + + vddio1-supply: true + + vddio2-supply: true + + vddio18-supply: true + + reset-gpios: + maxItems: 1 + description: + GPIO controlling the RESX# pin. + + qps615,axi-clk-freq-hz: + description: + AXI clock which internal bus of the switch. + + qcom,l0s-entry-delay-ns: + description: Aspm l0s entry delay in nanoseconds. + + qcom,l1-entry-delay-ns: + description: Aspm l1 entry delay in nanoseconds. + + qcom,tx-amplitude-millivolt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Change Tx Margin setting for low power consumption. + + qcom,no-dfe: + type: boolean + description: Disables DFE (Decision Feedback Equalizer). + + qcom,nfts: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + Fast Training Sequence (FTS) is the mechanism that + is used for bit and Symbol lock. + +allOf: + - $ref: /schemas/pci/pci-bus-common.yaml# + - if: + properties: + compatible: + contains: + const: pci1179,0623 + required: + - compatible + then: + required: + - vdd18-supply + - vdd09-supply + - vddc-supply + - vddio1-supply + - vddio2-supply + - vddio18-supply + - qcom,qps615-controller + - reset-gpios + +patternProperties: + "@1?[0-9a-f](,[0-7])?$": + type: object + $ref: qcom,qps615.yaml# + additionalProperties: true + +additionalProperties: true + +examples: + - | + + #include + + pcie { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + qcom,qps615-controller = <&qps615_controller>; + + vdd18-supply = <&vdd>; + vdd09-supply = <&vdd>; + vddc-supply = <&vdd>; + vddio1-supply = <&vdd>; + vddio2-supply = <&vdd>; + vddio18-supply = <&vdd>; + + reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + qcom,no-dfe; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + qcom,nfts = /bits/ 8 <10>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + qcom,tx-amplitude-millivolt = <10>; + + pcie@0,0 { + reg = <0x40000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + qcom,l1-entry-delay-ns = <10>; + }; + + pcie@0,1 { + reg = <0x40100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + qcom,l0s-entry-delay-ns = <10>; + }; + }; + }; + }; + }; From patchwork Sat Aug 3 03:22:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816533 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5A0D322B; Sat, 3 Aug 2024 03:31:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Sat, 03 Aug 2024 03:23:18 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4733NG56027262 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 Aug 2024 03:23:16 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:11 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:48 +0530 Subject: [PATCH v2 2/8] dt-bindings: trivial-devices: Add qcom,qps615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-2-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 5d3dc952770d..7f44add21bf6 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -330,6 +330,8 @@ properties: - renesas,isl29501 # Rohm DH2228FV - rohm,dh2228fv + # Qualcomm QPS615 PCIe switch control + - qcom,qps615 # S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) - samsung,24ad0xd1 # Samsung Exynos SoC SATA PHY I2C device From patchwork Sat Aug 3 03:22:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816636 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38D82C8DF; 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Sat, 03 Aug 2024 03:23:23 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4733NM3C027280 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 Aug 2024 03:23:22 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:17 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:49 +0530 Subject: [PATCH v2 3/8] arm64: dts: qcom: qcs6490-rb3gen2: Add node for qps615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-3-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Power to the QPS615 is supplied through two LDO regulators, controlled by two GPIOs, these are added as fixed regulators. Add i2c device node which is used to configure the switch. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 +++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 0d45662b8028..59d209768636 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; }; &apps_rsc { @@ -595,6 +619,12 @@ lt9611_out: endpoint { }; }; }; + + qps615_switch: pcie-switch@77 { + compatible = "qcom,qps615"; + reg = <0x77>; + status = "okay"; + }; }; &i2c1 { @@ -688,6 +718,75 @@ &pmk8350_rtc { status = "okay"; }; +&pcie1 { + status = "okay"; +}; + +&pcieport { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + qcom,qps615-controller = <&qps615_switch>; + + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + + pcie@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pcie@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -812,6 +911,28 @@ lt9611_rst_pin: lt9611-rst-state { }; }; +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + &tlmm { lt9611_irq_pin: lt9611-irq-state { pins = "gpio24"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3d8410683402..3840f056b7f2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2279,7 +2279,7 @@ pcie1: pcie@1c08000 { status = "disabled"; - pcie@0 { + pcieport: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From patchwork Sat Aug 3 03:22:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816531 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B009415E89; 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Sat, 03 Aug 2024 03:23:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4733NSUu008572 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 Aug 2024 03:23:28 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:22 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:50 +0530 Subject: [PATCH v2 4/8] PCI: Change the parent to correctly represent pcie hierarchy Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-4-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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If the supply is removed to the endpoint in the power control driver then the config space access by the pci-pci bridge driver can cause issues like Timeouts. For this reason change the parent to controller from pci-pci bridge. Fixes: 4565d2652a37 ("PCI/pwrctl: Add PCI power control core code") Signed-off-by: Krishna chaitanya chundru Acked-by: Bartosz Golaszewski Tested-by: Bartosz Golaszewski --- drivers/pci/bus.c | 3 ++- drivers/pci/pwrctl/core.c | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 55c853686051..15b42f0f588f 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -328,6 +328,7 @@ void __weak pcibios_bus_add_device(struct pci_dev *pdev) { } */ void pci_bus_add_device(struct pci_dev *dev) { + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); struct device_node *dn = dev->dev.of_node; int retval; @@ -352,7 +353,7 @@ void pci_bus_add_device(struct pci_dev *dev) if (dev_of_node(&dev->dev) && pci_is_bridge(dev)) { retval = of_platform_populate(dev_of_node(&dev->dev), NULL, NULL, - &dev->dev); + host->dev.parent); if (retval) pci_err(dev, "failed to populate child OF nodes (%d)\n", retval); diff --git a/drivers/pci/pwrctl/core.c b/drivers/pci/pwrctl/core.c index feca26ad2f6a..4f2ffa0b0a5f 100644 --- a/drivers/pci/pwrctl/core.c +++ b/drivers/pci/pwrctl/core.c @@ -11,6 +11,8 @@ #include #include +#include "../pci.h" + static int pci_pwrctl_notify(struct notifier_block *nb, unsigned long action, void *data) { @@ -64,18 +66,23 @@ static int pci_pwrctl_notify(struct notifier_block *nb, unsigned long action, */ int pci_pwrctl_device_set_ready(struct pci_pwrctl *pwrctl) { + struct pci_bus *bus; int ret; if (!pwrctl->dev) return -ENODEV; + bus = pci_find_bus(of_get_pci_domain_nr(pwrctl->dev->parent->of_node), 0); + if (!bus) + return -ENODEV; + pwrctl->nb.notifier_call = pci_pwrctl_notify; ret = bus_register_notifier(&pci_bus_type, &pwrctl->nb); if (ret) return ret; pci_lock_rescan_remove(); - pci_rescan_bus(to_pci_dev(pwrctl->dev->parent)->bus); + pci_rescan_bus(bus); pci_unlock_rescan_remove(); return 0; From patchwork Sat Aug 3 03:22:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816532 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 773DBF9F5; Sat, 3 Aug 2024 03:31:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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Sat, 03 Aug 2024 03:23:35 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4733NXQ9021756 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 Aug 2024 03:23:33 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:28 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:51 +0530 Subject: [PATCH v2 5/8] PCI: Add new start_link() & stop_link function ops Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-5-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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If the controller driver already enables link training as part of its probe, after the device is powered on, controller and device participates in the link training and link can come up immediately and maynot have time to configure the device. So we need to stop the link training by using stop_link() and enable them back after device is configured by using start_link(). Signed-off-by: Krishna chaitanya chundru --- include/linux/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 4cf89a4b4cbc..0791d74951e9 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -802,6 +802,8 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + int (*start_link)(struct pci_bus *bus); + void (*stop_link)(struct pci_bus *bus); }; /* From patchwork Sat Aug 3 03:22:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816635 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2C61865A; 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Sat, 03 Aug 2024 03:23:40 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4733Ndk3018900 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 3 Aug 2024 03:23:39 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:34 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:52 +0530 Subject: [PATCH v2 6/8] PCI: dwc: Add support for new pci function op Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-6-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 18 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 16 ++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a0822d5371bc..a1d994334ca5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -697,10 +697,28 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); +static int dw_pcie_op_start_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + return dw_pcie_host_start_link(pci); +} + +static void dw_pcie_op_stop_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + dw_pcie_host_stop_link(pci); +} + static struct pci_ops dw_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, + .start_link = dw_pcie_op_start_link, + .stop_link = dw_pcie_op_stop_link, }; static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 53c4c8f399c8..1aa1f8be8bda 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -402,6 +402,8 @@ struct dw_pcie_ops { enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); + int (*host_start_link)(struct dw_pcie *pcie); + void (*host_stop_link)(struct dw_pcie *pcie); }; struct dw_pcie { @@ -632,6 +634,20 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) pci->ops->stop_link(pci); } +static inline int dw_pcie_host_start_link(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->host_start_link) + return pci->ops->host_start_link(pci); + + return 0; +} + +static inline void dw_pcie_host_stop_link(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->host_stop_link) + pci->ops->host_stop_link(pci); +} + static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) { u32 val; From patchwork Sat Aug 3 03:22:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816638 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EFD710A03; Sat, 3 Aug 2024 03:31:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722655861; cv=none; b=fNYdRp7VT/IBMl/2jnAXbb2cQmbXxO+56oyv7/LI09gcR6VRGTvA0TIgCCVKXxKLMFhGDRg/YHYvXr8qI8KqV/NNMT0DY1SC4NBTzw1V0ZfQmce8442KJeaKnSWd8bjI7OQ0L6sagU9fXj//AdeqgrvhffWTdGFMed1hNagDM/E= ARC-Message-Signature: i=1; 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Sat, 3 Aug 2024 03:23:45 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:39 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:53 +0530 Subject: [PATCH v2 7/8] PCI: qcom: Add support for host_stop_link() & host_start_link() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-7-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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De-assert the PERST# and enable LTSSM bit back in host_start_link(). Introduce ltssm_disable function op to stop the link training. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..f4a6df53139c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -233,6 +233,7 @@ struct qcom_pcie_ops { void (*host_post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); + void (*ltssm_disable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); }; @@ -555,6 +556,41 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_host_start_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + if (!dw_pcie_link_up(pcie->pci)) { + qcom_ep_reset_deassert(pcie); + + if (pcie->cfg->ops->ltssm_enable) + pcie->cfg->ops->ltssm_enable(pcie); + } + + return 0; +} + +static void qcom_pcie_host_stop_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + if (!dw_pcie_link_up(pcie->pci)) { + qcom_ep_reset_assert(pcie); + + if (pcie->cfg->ops->ltssm_disable) + pcie->cfg->ops->ltssm_disable(pcie); + } +} + +static void qcom_pcie_2_3_2_ltssm_disable(struct qcom_pcie *pcie) +{ + u32 val; + + val = readl(pcie->parf + PARF_LTSSM); + val &= ~LTSSM_EN; + writel(val, pcie->parf + PARF_LTSSM); +} + static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -1306,6 +1342,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .host_post_init = qcom_pcie_host_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .ltssm_disable = qcom_pcie_2_3_2_ltssm_disable, .config_sid = qcom_pcie_config_sid_1_9_0, }; @@ -1363,6 +1400,8 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, + .host_start_link = qcom_pcie_host_start_link, + .host_stop_link = qcom_pcie_host_stop_link, }; static int qcom_pcie_icc_init(struct qcom_pcie *pcie) From patchwork Sat Aug 3 03:22:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 816639 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D44AF6FC1; Sat, 3 Aug 2024 03:25:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722655561; cv=none; b=VwaPds/vsD7wdWCjVy2yRUWiL1Y3MIBDu4Z0v6CvQpLrsqfEK8eVVCM44L/Jtli2D/Pt/W1jLZbmFJq8SjJ0WvnZA6tUNArCKq30COyeRpsgRR8dY9qvNtt0wMn+944hfDXGx68qv+xkdeUy3qeV72yUtDqXrGlk1Io+OycVg7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722655561; 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Sat, 3 Aug 2024 03:23:50 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:45 -0700 From: Krishna chaitanya chundru Date: Sat, 3 Aug 2024 08:52:54 +0530 Subject: [PATCH v2 8/8] PCI: pwrctl: Add power control driver for qps615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240803-qps615-v2-8-9560b7c71369@quicinc.com> References: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> In-Reply-To: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1722655379; l=18789; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=HNYkkv+sXMm1J4kh7WdDJ3hcQrC7iseoPfzcI773leU=; b=knw6owNTQaPBqZi+allSxMXIZddxsRuwXfDR8qIXroDt3mdVopztk3AQQfz96Ttqm0CoZhWYP IhG+A7zWdPsCpf7dEZBc06pgieSxjTaLjZ8MOyRBQDYmppnJkoYezmi X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: bWI8Hq_eLqSRT0IjZRI88Hz0oSe5eDLj X-Proofpoint-GUID: bWI8Hq_eLqSRT0IjZRI88Hz0oSe5eDLj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-02_20,2024-08-02_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408030020 QPS615 switch needs to be configured after powering on and before PCIe link was up. As the PCIe controller driver already enables the PCIe link training at the host side, stop the link training. Otherwise the moment we turn on the switch it will participate in the link training and link may come up before switch is configured through i2c. The device tree properties are parsed per node under pci-pci bridge in the driver. Each node has unique bdf value in the reg property, driver uses this bdf to differentiate ports, as there are certain i2c writes to select particular port. Based up on dt property and port, qps615 is configured through i2c. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/pwrctl/Kconfig | 7 + drivers/pci/pwrctl/Makefile | 1 + drivers/pci/pwrctl/pci-pwrctl-qps615.c | 638 +++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) diff --git a/drivers/pci/pwrctl/Kconfig b/drivers/pci/pwrctl/Kconfig index 54589bb2403b..6a1352af918c 100644 --- a/drivers/pci/pwrctl/Kconfig +++ b/drivers/pci/pwrctl/Kconfig @@ -10,3 +10,10 @@ config PCI_PWRCTL_PWRSEQ tristate select POWER_SEQUENCING select PCI_PWRCTL + +config PCI_PWRCTL_QPS615 + tristate "PCI Power Control driver for QPS615" + select PCI_PWRCTL + help + Say Y here to enable the pwrctl driver for Qualcomm + QPS615 PCIe switch. diff --git a/drivers/pci/pwrctl/Makefile b/drivers/pci/pwrctl/Makefile index d308aae4800c..ac563a70c023 100644 --- a/drivers/pci/pwrctl/Makefile +++ b/drivers/pci/pwrctl/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_PWRCTL) += pci-pwrctl-core.o pci-pwrctl-core-y := core.o obj-$(CONFIG_PCI_PWRCTL_PWRSEQ) += pci-pwrctl-pwrseq.o +obj-$(CONFIG_PCI_PWRCTL_QPS615) += pci-pwrctl-qps615.o diff --git a/drivers/pci/pwrctl/pci-pwrctl-qps615.c b/drivers/pci/pwrctl/pci-pwrctl-qps615.c new file mode 100644 index 000000000000..9dabb82787d5 --- /dev/null +++ b/drivers/pci/pwrctl/pci-pwrctl-qps615.c @@ -0,0 +1,638 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +#define QPS615_GPIO_CONFIG 0x801208 +#define QPS615_RESET_GPIO 0x801210 + +#define QPS615_BUS_CONTROL 0x801014 + +#define QPS615_PORT_L0S_DELAY 0x82496c +#define QPS615_PORT_L1_DELAY 0x824970 + +#define QPS615_EMBEDDED_ETH_DELAY 0x8200d8 +#define QPS615_ETH_L1_DELAY_MASK GENMASK(27, 18) +#define QPS615_ETH_L1_DELAY_VALUE(x) FIELD_PREP(QPS615_ETH_L1_DELAY_MASK, x) +#define QPS615_ETH_L0S_DELAY_MASK GENMASK(17, 13) +#define QPS615_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(QPS615_ETH_L0S_DELAY_MASK, x) + +#define QPS615_NFTS_2_5_GT 0x824978 +#define QPS615_NFTS_5_GT 0x82497c + +#define QPS615_PORT_LANE_ACCESS_ENABLE 0x828000 + +#define QPS615_PHY_RATE_CHANGE_OVERRIDE 0x828040 +#define QPS615_PHY_RATE_CHANGE 0x828050 + +#define QPS615_TX_MARGIN 0x828234 + +#define QPS615_DFE_ENABLE 0x828a04 +#define QPS615_DFE_EQ0_MODE 0x828a08 +#define QPS615_DFE_EQ1_MODE 0x828a0c +#define QPS615_DFE_EQ2_MODE 0x828a14 +#define QPS615_DFE_PD_MASK 0x828254 + +#define QPS615_PORT_SELECT 0x82c02c +#define QPS615_PORT_ACCESS_ENABLE 0x82c030 + +#define QPS615_POWER_CONTROL 0x82b09c +#define QPS615_POWER_CONTROL_OVREN 0x82b2c8 + +#define QPS615_AXI_CLK_FREQ_MHZ 125 + +struct qps615_pwrctl_reg_setting { + unsigned int offset; + unsigned int val; +}; + +struct qps615_pwrctl_bdf_info { + u16 usp_bdf; + u16 dsp1_bdf; + u16 dsp2_bdf; + u16 dsp3_bdf; +}; + +enum qps615_pwrctl_ports { + QPS615_USP, + QPS615_DSP1, + QPS615_DSP2, + QPS615_DSP3, + QPS615_ETHERNET, + QPS615_MAX +}; + +struct qps615_pwrctl_cfg { + u32 l0s_delay; + u32 l1_delay; + u32 tx_amp; + u32 axi_freq; + u8 nfts; + bool disable_dfe; + bool disable_port; +}; + +#define QPS615_PWRCTL_MAX_SUPPLY 6 + +struct qps615_pwrctl_ctx { + struct regulator_bulk_data supplies[QPS615_PWRCTL_MAX_SUPPLY]; + const struct qps615_pwrctl_bdf_info *bdf; + struct qps615_pwrctl_cfg cfg[QPS615_MAX]; + struct gpio_desc *reset_gpio; + struct i2c_client *client; + struct pci_pwrctl pwrctl; + struct device_link *link; +}; + +/* + * downstream port power off sequence, hardcoding the address + * as we don't know register names for these register offsets. + */ +static const struct qps615_pwrctl_reg_setting common_pwroff_seq[] = { + {0x82900c, 0x1}, + {0x829010, 0x1}, + {0x829018, 0x0}, + {0x829020, 0x1}, + {0x82902c, 0x1}, + {0x829030, 0x1}, + {0x82903c, 0x1}, + {0x829058, 0x0}, + {0x82905c, 0x1}, + {0x829060, 0x1}, + {0x8290cc, 0x1}, + {0x8290d0, 0x1}, + {0x8290d8, 0x1}, + {0x8290e0, 0x1}, + {0x8290e8, 0x1}, + {0x8290ec, 0x1}, + {0x8290f4, 0x1}, + {0x82910c, 0x1}, + {0x829110, 0x1}, + {0x829114, 0x1}, +}; + +static const struct qps615_pwrctl_reg_setting dsp1_pwroff_seq[] = { + {QPS615_PORT_ACCESS_ENABLE, 0x2}, + {QPS615_PORT_LANE_ACCESS_ENABLE, 0x3}, + {QPS615_POWER_CONTROL, 0x014f4804}, + {QPS615_POWER_CONTROL_OVREN, 0x1}, + {QPS615_PORT_ACCESS_ENABLE, 0x4}, +}; + +static const struct qps615_pwrctl_reg_setting dsp2_pwroff_seq[] = { + {QPS615_PORT_ACCESS_ENABLE, 0x8}, + {QPS615_PORT_LANE_ACCESS_ENABLE, 0x1}, + {QPS615_POWER_CONTROL, 0x014f4804}, + {QPS615_POWER_CONTROL_OVREN, 0x1}, + {QPS615_PORT_ACCESS_ENABLE, 0x8}, +}; + +static int qps615_pwrctl_i2c_write(struct i2c_client *client, + u32 reg_addr, u32 reg_val) +{ + struct i2c_msg msg; + u8 msg_buf[7]; + int ret; + + msg.addr = client->addr; + msg.len = 7; + msg.flags = 0; + + /* Big Endian for reg addr */ + reg_addr = cpu_to_be32(reg_addr); + + msg_buf[0] = (u8)(reg_addr >> 8); + msg_buf[1] = (u8)(reg_addr >> 16); + msg_buf[2] = (u8)(reg_addr >> 24); + + /* Little Endian for reg val */ + reg_val = cpu_to_le32(reg_val); + + msg_buf[3] = (u8)(reg_val); + msg_buf[4] = (u8)(reg_val >> 8); + msg_buf[5] = (u8)(reg_val >> 16); + msg_buf[6] = (u8)(reg_val >> 24); + + msg.buf = msg_buf; + ret = i2c_transfer(client->adapter, &msg, 1); + return ret == 1 ? 0 : ret; +} + +static int qps615_pwrctl_i2c_read(struct i2c_client *client, + u32 reg_addr, u32 *reg_val) +{ + struct i2c_msg msg[2]; + u8 wr_data[3]; + u32 rd_data; + int ret; + + msg[0].addr = client->addr; + msg[0].len = 3; + msg[0].flags = 0; + + /* Big Endian for reg addr */ + reg_addr = cpu_to_be32(reg_addr); + + wr_data[0] = (u8)(reg_addr >> 8); + wr_data[1] = (u8)(reg_addr >> 16); + wr_data[2] = (u8)(reg_addr >> 24); + + msg[0].buf = wr_data; + + msg[1].addr = client->addr; + msg[1].len = 4; + msg[1].flags = I2C_M_RD; + + msg[1].buf = (u8 *)&rd_data; + + ret = i2c_transfer(client->adapter, &msg[0], 2); + if (ret == 2) { + *reg_val = le32_to_cpu(rd_data); + return 0; + } + + /* If only one message successfully completed, return -ENODEV */ + return ret == 1 ? -ENODEV : ret; +} + +static int qps615_pwrctl_i2c_bulk_write(struct i2c_client *client, + const struct qps615_pwrctl_reg_setting *seq, int len) +{ + int ret, i; + + for (i = 0; i < len; i++) { + ret = qps615_pwrctl_i2c_write(client, seq[i].offset, seq[i].val); + if (ret) + return ret; + } + + return 0; +} + +static int of_pci_get_bdf(struct device_node *np) +{ + u32 reg[5]; + int error; + + error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + return (reg[0] >> 8) & 0xffff; +} + +static int qps615_pwrctl_disable_port(struct qps615_pwrctl_ctx *ctx, + enum qps615_pwrctl_ports port) +{ + const struct qps615_pwrctl_reg_setting *seq; + int ret, len; + + seq = (port == QPS615_DSP1) ? dsp1_pwroff_seq : dsp2_pwroff_seq; + len = (port == QPS615_DSP1) ? ARRAY_SIZE(dsp1_pwroff_seq) : ARRAY_SIZE(dsp2_pwroff_seq); + + ret = qps615_pwrctl_i2c_bulk_write(ctx->client, seq, len); + if (ret) + return ret; + + return qps615_pwrctl_i2c_bulk_write(ctx->client, + common_pwroff_seq, ARRAY_SIZE(common_pwroff_seq)); +} + +static int qps615_pwrctl_set_l0s_l1_entry_delay(struct qps615_pwrctl_ctx *ctx, + enum qps615_pwrctl_ports port, bool is_l1, u32 ns) +{ + u32 rd_val, units; + int ret; + + /* convert to units of 256ns */ + units = ns / 256; + + if (port == QPS615_ETHERNET) { + ret = qps615_pwrctl_i2c_read(ctx->client, QPS615_EMBEDDED_ETH_DELAY, &rd_val); + if (ret) + return ret; + rd_val = u32_replace_bits(rd_val, units, + is_l1 ? + QPS615_ETH_L1_DELAY_MASK : QPS615_ETH_L0S_DELAY_MASK); + return qps615_pwrctl_i2c_write(ctx->client, QPS615_EMBEDDED_ETH_DELAY, rd_val); + } + + ret = qps615_pwrctl_i2c_write(ctx->client, QPS615_PORT_SELECT, BIT(port)); + if (ret) + return ret; + + return qps615_pwrctl_i2c_write(ctx->client, + is_l1 ? QPS615_PORT_L1_DELAY : QPS615_PORT_L0S_DELAY, units); +} + +static int qps615_pwrctl_set_tx_amplitude(struct qps615_pwrctl_ctx *ctx, + enum qps615_pwrctl_ports port, u32 amp) +{ + int port_access; + + switch (port) { + case QPS615_USP: + port_access = 0x1; + break; + case QPS615_DSP1: + port_access = 0x2; + break; + case QPS615_DSP2: + port_access = 0x8; + break; + default: + return -EINVAL; + }; + + struct qps615_pwrctl_reg_setting tx_amp_seq[] = { + {QPS615_PORT_ACCESS_ENABLE, port_access}, + {QPS615_PORT_LANE_ACCESS_ENABLE, 0x3}, + {QPS615_TX_MARGIN, amp}, + }; + + return qps615_pwrctl_i2c_bulk_write(ctx->client, tx_amp_seq, ARRAY_SIZE(tx_amp_seq)); +} + +static int qps615_pwrctl_disable_dfe(struct qps615_pwrctl_ctx *ctx, + enum qps615_pwrctl_ports port) +{ + int port_access, lane_access = 0x3; + u32 phy_rate = 0x21; + + switch (port) { + case QPS615_USP: + phy_rate = 0x1; + port_access = 0x1; + break; + case QPS615_DSP1: + port_access = 0x2; + break; + case QPS615_DSP2: + port_access = 0x8; + lane_access = 0x1; + break; + default: + return -EINVAL; + }; + + struct qps615_pwrctl_reg_setting disable_dfe_seq[] = { + {QPS615_PORT_ACCESS_ENABLE, port_access}, + {QPS615_PORT_LANE_ACCESS_ENABLE, lane_access}, + {QPS615_DFE_ENABLE, 0x0}, + {QPS615_DFE_EQ0_MODE, 0x411}, + {QPS615_DFE_EQ1_MODE, 0x11}, + {QPS615_DFE_EQ2_MODE, 0x11}, + {QPS615_DFE_PD_MASK, 0x7}, + {QPS615_PHY_RATE_CHANGE_OVERRIDE, 0x10}, + {QPS615_PHY_RATE_CHANGE, phy_rate}, + {QPS615_PHY_RATE_CHANGE, 0x0}, + {QPS615_PHY_RATE_CHANGE_OVERRIDE, 0x0}, + + }; + + return qps615_pwrctl_i2c_bulk_write(ctx->client, + disable_dfe_seq, ARRAY_SIZE(disable_dfe_seq)); +} + +static int qps615_pwrctl_set_nfts(struct qps615_pwrctl_ctx *ctx, + enum qps615_pwrctl_ports port, u32 nfts) +{ + int ret; + struct qps615_pwrctl_reg_setting nfts_seq[] = { + {QPS615_NFTS_2_5_GT, nfts}, + {QPS615_NFTS_5_GT, nfts}, + }; + + ret = qps615_pwrctl_i2c_write(ctx->client, QPS615_PORT_SELECT, BIT(port)); + if (ret) + return ret; + + return qps615_pwrctl_i2c_bulk_write(ctx->client, nfts_seq, ARRAY_SIZE(nfts_seq)); +} + +static int qps615_pwrctl_assert_deassert_reset(struct qps615_pwrctl_ctx *ctx, bool deassert) +{ + int ret, val = 0; + + if (deassert) + val = 0xc; + + ret = qps615_pwrctl_i2c_write(ctx->client, QPS615_GPIO_CONFIG, 0xfffffff3); + if (ret) + return ret; + + return qps615_pwrctl_i2c_write(ctx->client, QPS615_RESET_GPIO, val); +} + +static int qps615_pwrctl_parse_device_dt(struct qps615_pwrctl_ctx *ctx, struct device_node *node) +{ + enum qps615_pwrctl_ports port; + struct qps615_pwrctl_cfg *cfg; + struct device_node *np; + int bdf, fun_no; + + bdf = of_pci_get_bdf(node); + if (bdf < 0) { + dev_err(ctx->pwrctl.dev, "Getting BDF failed\n"); + return 0; + } + + fun_no = bdf & 0x7; + + /* In multi function node, ignore function 1 node */ + if (of_pci_get_bdf(of_get_parent(node)) == ctx->bdf->dsp3_bdf && !fun_no) + port = QPS615_ETHERNET; + else if (bdf == ctx->bdf->usp_bdf) + port = QPS615_USP; + else if (bdf == ctx->bdf->dsp1_bdf) + port = QPS615_DSP1; + else if (bdf == ctx->bdf->dsp2_bdf) + port = QPS615_DSP2; + else if (bdf == ctx->bdf->dsp3_bdf) + port = QPS615_DSP3; + else + return 0; + + cfg = &ctx->cfg[port]; + + if (!of_device_is_available(node)) { + cfg->disable_port = true; + return 0; + }; + + of_property_read_u32(node, "qcom,axi-clk-freq-hz", &cfg->axi_freq); + + of_property_read_u32(node, "qcom,l0s-entry-delay-ns", &cfg->l0s_delay); + + of_property_read_u32(node, "qcom,l1-entry-delay-ns", &cfg->l1_delay); + + of_property_read_u32(node, "qcom,tx-amplitude-millivolt", &cfg->tx_amp); + + cfg->disable_dfe = of_property_read_bool(node, "qcom,no-dfe"); + + of_property_read_u8(node, "qcom,nfts", &cfg->nfts); + + for_each_child_of_node(node, np) + qps615_pwrctl_parse_device_dt(ctx, np); + + of_node_put(np); + return 0; +} + +static void qps615_pwrctl_power_off(struct qps615_pwrctl_ctx *ctx) +{ + gpiod_set_value(ctx->reset_gpio, 1); + + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); +} + +static int qps615_pwrctl_power_on(struct qps615_pwrctl_ctx *ctx) +{ + struct qps615_pwrctl_cfg *cfg; + int ret, i; + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) + return dev_err_probe(ctx->pwrctl.dev, ret, "cannot enable regulators\n"); + + gpiod_set_value(ctx->reset_gpio, 0); + + if (!ctx->client) + return 0; + + /* + * Don't have a way to see if the reset has completed. + * Wait for some time. + */ + usleep_range(1000, 1001); + + ret = qps615_pwrctl_assert_deassert_reset(ctx, false); + if (ret) + goto out; + + if (ctx->cfg[QPS615_USP].axi_freq == QPS615_AXI_CLK_FREQ_MHZ) { + ret = qps615_pwrctl_i2c_write(ctx->client, QPS615_BUS_CONTROL, BIT(16)); + if (ret) + dev_err(ctx->pwrctl.dev, "Setting axi clk freq failed %d\n", ret); + } + + for (i = 0; i < QPS615_MAX; i++) { + cfg = &ctx->cfg[i]; + if (cfg->disable_port) { + ret = qps615_pwrctl_disable_port(ctx, i); + if (ret) { + dev_err(ctx->pwrctl.dev, "Disabling port failed\n"); + goto out; + } + } + + if (cfg->l0s_delay) { + ret = qps615_pwrctl_set_l0s_l1_entry_delay(ctx, i, false, cfg->l0s_delay); + if (ret) { + dev_err(ctx->pwrctl.dev, "Setting L0s entry delay failed\n"); + goto out; + } + } + + if (cfg->l1_delay) { + ret = qps615_pwrctl_set_l0s_l1_entry_delay(ctx, i, true, cfg->l1_delay); + if (ret) { + dev_err(ctx->pwrctl.dev, "Setting L1 entry delay failed\n"); + goto out; + } + } + + if (cfg->tx_amp) { + ret = qps615_pwrctl_set_tx_amplitude(ctx, i, cfg->tx_amp); + if (ret) { + dev_err(ctx->pwrctl.dev, "Setting Tx amplitube failed\n"); + goto out; + } + } + + if (cfg->nfts) { + ret = qps615_pwrctl_set_nfts(ctx, i, cfg->nfts); + if (ret) { + dev_err(ctx->pwrctl.dev, "Setting nfts failed\n"); + goto out; + } + } + + if (cfg->disable_dfe) { + ret = qps615_pwrctl_disable_dfe(ctx, i); + if (ret) { + dev_err(ctx->pwrctl.dev, "Disabling DFE failed\n"); + goto out; + } + } + } + + ret = qps615_pwrctl_assert_deassert_reset(ctx, true); + if (!ret) + return 0; + +out: + qps615_pwrctl_power_off(ctx); + return ret; +} + +static int qps615_pwrctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pci_host_bridge *bridge; + struct qps615_pwrctl_ctx *ctx; + struct device_node *node; + struct pci_bus *bus; + int ret; + + bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + if (!bus) + return -ENODEV; + + bridge = pci_find_host_bridge(bus); + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + node = of_parse_phandle(pdev->dev.of_node, "qcom,qps615-controller", 0); + if (node) { + ctx->client = of_find_i2c_device_by_node(node); + of_node_put(node); + if (!ctx->client) + return dev_err_probe(dev, -EPROBE_DEFER, + "failed to parse qcom,qps615-controller\n"); + } + + ctx->bdf = of_device_get_match_data(dev); + ctx->pwrctl.dev = dev; + + ctx->supplies[0].supply = "vddc"; + ctx->supplies[1].supply = "vdd18"; + ctx->supplies[2].supply = "vdd09"; + ctx->supplies[3].supply = "vddio1"; + ctx->supplies[4].supply = "vddio2"; + ctx->supplies[5].supply = "vddio18"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get supply regulator\n"); + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "failed to get reset GPIO\n"); + + ctx->link = device_link_add(&bridge->dev, dev, DL_FLAG_AUTOREMOVE_CONSUMER); + + platform_set_drvdata(pdev, ctx); + + qps615_pwrctl_parse_device_dt(ctx, pdev->dev.of_node); + + if (bridge->ops->stop_link) + bridge->ops->stop_link(bus); + + ret = qps615_pwrctl_power_on(ctx); + if (ret) + return ret; + + if (bridge->ops->start_link) { + ret = bridge->ops->start_link(bus); + if (ret) + return ret; + } + + return devm_pci_pwrctl_device_set_ready(dev, &ctx->pwrctl); +} + +static void qps615_pwrctl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + device_link_del(ctx->link); + qps615_pwrctl_power_off(ctx); +} + +static const struct qps615_pwrctl_bdf_info bdf_info = { + .usp_bdf = 0x100, + .dsp1_bdf = 0x208, + .dsp2_bdf = 0x210, + .dsp3_bdf = 0x218, +}; + +static const struct of_device_id qps615_pwrctl_of_match[] = { + { .compatible = "pci1179,0623", .data = &bdf_info }, + { } +}; +MODULE_DEVICE_TABLE(of, qps615_pwrctl_of_match); + +static struct platform_driver qps615_pwrctl_driver = { + .driver = { + .name = "pwrctl-qps615", + .of_match_table = qps615_pwrctl_of_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = qps615_pwrctl_probe, + .remove_new = qps615_pwrctl_remove, +}; +module_platform_driver(qps615_pwrctl_driver); + +MODULE_AUTHOR("Krishna chaitanya chundru "); +MODULE_DESCRIPTION("Qualcomm QPS615 power control driver"); +MODULE_LICENSE("GPL");