From patchwork Fri Aug 2 15:31:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 816683 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87D5E13632A; Fri, 2 Aug 2024 15:35:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722612910; cv=none; b=EJlog4ayWRIKM1va4bhHiblnRxPACC45IoVmTKHxRiNG7T9tQBYvreaRdxW05mbOV2KFXucLf0Zus/OJ5D3tNWHNAXwmuEd8Qb45TXoHWvUpGSmrz1pacUc0HcpsJATxF9aPx+R2oQE72fYeE4DR5gPbLOv0L6F4x1iVX5byy4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722612910; c=relaxed/simple; bh=jOKejuFSI0ocJibzterhxRI6kfUg7oPe9uQyDE1Jcuk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=akWNKz8CMg/7c/JzwwB4FKvRF8zTffoVQda0iO4fhS6dn87R1As7/xdQp+kDavQUak29aNc42iqlKNMHsPtD0Tz3kY2/beH7cx83d97SxMnc2GdCsRHXKEL6+OuzZF7jXuZB6BI0v6Usgd1KXBkiGabdmlZ2EN1TZiliG30Z0LM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=fU5f7jpH; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="fU5f7jpH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1722612906; bh=jOKejuFSI0ocJibzterhxRI6kfUg7oPe9uQyDE1Jcuk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fU5f7jpHZiCqmXKjm6eioVwx5zs6v6QO8kPVDatiedSdLlPC3BdGUo70zwDTXY3Ss 1rSch4obdF5cbuN/8mlP8dNWMPZBHNvwQjx/iHOiXI1GZRDSrJwxX6MctFNlF83xwx 7emxEu0uHmakYAMdmDpxXzCLScrv8SCcWgGNi6thRrLpDNjW06l9lgusXuuFGpbEkN OGiDYGfYJeBpJFtBM/sx361MZCeAJd1ZLsM14qCMIKUfPQWmAdacdgKEXx/RcdxU0y qL2AV1xVQ7qdrBQJAJKTmsTNj6H2LWzfmqLQgVJE92a/Txcrs/RCsBIJATk2TKwQcW gSWHKee63G86Q== Received: from trenzalore.hitronhub.home (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 21E823782219; Fri, 2 Aug 2024 15:35:05 +0000 (UTC) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jaehoon Chung , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Detlev Casanova Subject: [PATCH 1/3] dt-bindings: pinctrl: Add rk3576 dw-mshc bindings Date: Fri, 2 Aug 2024 11:31:27 -0400 Message-ID: <20240802153609.296197-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240802153609.296197-1-detlev.casanova@collabora.com> References: <20240802153609.296197-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the compatible string for rockchip,rk3576-dw-mshc and add support for the rockchip,use-v2-tuning flag, a new feature of this core. Signed-off-by: Detlev Casanova --- .../devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml index 211cd0b0bc5f3..dd8d1e773bb38 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml @@ -39,6 +39,7 @@ properties: - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc - rockchip,rk3568-dw-mshc + - rockchip,rk3576-dw-mshc - rockchip,rk3588-dw-mshc - rockchip,rv1108-dw-mshc - rockchip,rv1126-dw-mshc @@ -95,6 +96,16 @@ properties: If not specified, the host will do tuning for 360 times, namely tuning for each degree. + rockchip,use-v2-tuning: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present, use tuning version 2. + v2 tuning will inherit pre-stage loader's phase settings for the first + time, and do re-tune if necessary. + Re-tune will still try the rough degrees, for instance, 90, 180, 270, + 360 but continue to do the fine tuning if sample window isn't good + enough. + required: - compatible - reg From patchwork Fri Aug 2 15:31:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 816434 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD5C1537C5; Fri, 2 Aug 2024 15:35:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722612912; cv=none; b=QSq3gKomy2qrtCEfx0YKPdHbdFf6AT8Py9pftAubPSjHlFgQ2cy9d5JCMZQTG83B7jdRcLuw8GdJAhJsdxxpFKxiMbDZvfXmci5KFR5mpdwnAApcZawn5vrec9ctsiaxrcSu1zywUQHTDlLTB34gcEB/mav92llsb/cYXxfsOLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722612912; c=relaxed/simple; bh=6jXRBP+uzUiPE83cF/CLBHqxDVEBgCZETPVHDDmT6Vo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ksnCpQorNrIwc0Pqp0wOaH9OnhrMg0c+/s+uBs9OLIky7gXZDIs4M8HcncP+XeSUnwY7PRmlcMyae+6ruihpYfWAAxQpewvFEhF/3XultgeZcLpTUEuWhOMXIDRz23qMbn3ijB6nl5uR8snYPgdQs11uKQYK6+lHjKZzMVKCww4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=NA+GzsS7; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="NA+GzsS7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1722612909; bh=6jXRBP+uzUiPE83cF/CLBHqxDVEBgCZETPVHDDmT6Vo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NA+GzsS7EkJZFPoDTZSueWdyLWxvbfYRwjPzfR31XwOSViWFa+ZrxLHcePl2b7x8w Sh4gi+YgunY3lEnfKyLRyTHaGSgRwVcUKE00tRTNFc4OYuQP0R7iIL4QuVbAV5VGtg zOGbO3BiYyFgncRPbHAiABcglhv0jjwePaR76aAiiZeKzxmOGTsU07gtGSmE1xe1I9 S8mUKFqT2iIShwHl+/UKAQxs+KCG8yeF7+xT5ZAP5XYp5h9yHepMTMHYhgXh2u5v3e 5ozVWba7GT4GRie7c/akqbFFdnakD/LsNJBSv9JLvj2/qhhJTlcOT+gxUwIXOvXTbb s9oG/5fJYkl1A== Received: from trenzalore.hitronhub.home (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 31AC7378221A; Fri, 2 Aug 2024 15:35:07 +0000 (UTC) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jaehoon Chung , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Shawn Lin , Detlev Casanova Subject: [PATCH 2/3] mmc: dw_mmc-rockchip: Add v2 tuning support Date: Fri, 2 Aug 2024 11:31:28 -0400 Message-ID: <20240802153609.296197-3-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240802153609.296197-1-detlev.casanova@collabora.com> References: <20240802153609.296197-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Shawn Lin v2 tuning will inherit pre-stage loader's phase settings for the first time, and do re-tune if necessary. Re-tune will still try the rough degrees, for instance, 90, 180, 270, 360 but continue to do the fine tuning if sample window isn't good enough. Signed-off-by: Shawn Lin Signed-off-by: Detlev Casanova --- drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index b07190ba4b7ac..c47b93d99a1b3 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -24,6 +24,8 @@ struct dw_mci_rockchip_priv_data { struct clk *sample_clk; int default_sample_phase; int num_phases; + bool use_v2_tuning; + int last_degree; }; static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) @@ -134,6 +136,42 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) #define TUNING_ITERATION_TO_PHASE(i, num_phases) \ (DIV_ROUND_UP((i) * 360, num_phases)) +static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode) +{ + struct dw_mci *host = slot->host; + struct dw_mci_rockchip_priv_data *priv = host->priv; + struct mmc_host *mmc = slot->mmc; + u32 degrees[4] = {90, 180, 270, 360}; + int i; + static bool inherit = true; + + if (inherit) { + inherit = false; + i = clk_get_phase(priv->sample_clk) / 90 - 1; + goto done; + } + + /* v2 only support 4 degrees in theory */ + for (i = 0; i < ARRAY_SIZE(degrees); i++) { + if (degrees[i] == priv->last_degree) + continue; + + clk_set_phase(priv->sample_clk, degrees[i]); + if (!mmc_send_tuning(mmc, opcode, NULL)) + break; + } + + if (i == ARRAY_SIZE(degrees)) { + dev_warn(host->dev, "All phases bad!"); + return -EIO; + } + +done: + dev_info(host->dev, "Successfully tuned phase to %d\n", degrees[i]); + priv->last_degree = degrees[i]; + return 0; +} + static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) { struct dw_mci *host = slot->host; @@ -157,6 +195,13 @@ static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) return -EIO; } + if (priv->use_v2_tuning) { + ret = dw_mci_v2_execute_tuning(slot, opcode); + if (!ret) + return 0; + /* Otherwise we continue using fine tuning */ + } + ranges = kmalloc_array(priv->num_phases / 2 + 1, sizeof(*ranges), GFP_KERNEL); if (!ranges) @@ -277,6 +322,9 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host) &priv->default_sample_phase)) priv->default_sample_phase = 0; + if (of_property_read_bool(np, "rockchip,use-v2-tuning")) + priv->use_v2_tuning = true; + priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); if (IS_ERR(priv->drv_clk)) dev_dbg(host->dev, "ciu-drive not available\n"); From patchwork Fri Aug 2 15:31:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 816682 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCB6915C128; Fri, 2 Aug 2024 15:35:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 2 Aug 2024 15:35:09 +0000 (UTC) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jaehoon Chung , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Shawn Lin , Detlev Casanova Subject: [PATCH 3/3] mmc: dw_mmc-rockchip: Add internal phase support Date: Fri, 2 Aug 2024 11:31:29 -0400 Message-ID: <20240802153609.296197-4-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240802153609.296197-1-detlev.casanova@collabora.com> References: <20240802153609.296197-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Shawn Lin Some Rockchip devices put the phase settings into the dw_mmc controller. The feature is implemented in devices where the USRID register contains 0x20230002. Signed-off-by: Shawn Lin Signed-off-by: Detlev Casanova --- drivers/mmc/host/dw_mmc-rockchip.c | 180 +++++++++++++++++++++++++++-- 1 file changed, 169 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index c47b93d99a1b3..2f474e7eb21dc 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -16,6 +16,17 @@ #include "dw_mmc-pltfm.h" #define RK3288_CLKGEN_DIV 2 +#define USRID_INTER_PHASE 0x20230001 +#define SDMMC_TIMING_CON0 0x130 +#define SDMMC_TIMING_CON1 0x134 +#define ROCKCHIP_MMC_DELAY_SEL BIT(10) +#define ROCKCHIP_MMC_DEGREE_MASK 0x3 +#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 +#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) +#define PSECS_PER_SEC 1000000000000LL +#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; @@ -25,9 +36,121 @@ struct dw_mci_rockchip_priv_data { int default_sample_phase; int num_phases; bool use_v2_tuning; + int usrid; int last_degree; }; +/* + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. + */ +static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) +{ + unsigned long rate = clk_get_rate(host->ciu_clk); + u32 raw_value; + u16 degrees; + u32 delay_num = 0; + + /* Constant signal, no measurable phase shift */ + if (!rate) + return 0; + + if (sample) + raw_value = mci_readl(host, TIMING_CON1) >> 1; + else + raw_value = mci_readl(host, TIMING_CON0) >> 1; + + degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; + + if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { + /* degrees/delaynum * 1000000 */ + unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * + 36 * (rate / 10000); + + delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); + delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; + degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); + } + + return degrees % 360; +} + +static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) +{ + unsigned long rate = clk_get_rate(host->ciu_clk); + u8 nineties, remainder; + u8 delay_num; + u32 raw_value; + u32 delay; + + /* + * The below calculation is based on the output clock from + * MMC host to the card, which expects the phase clock inherits + * the clock rate from its parent, namely the output clock + * provider of MMC host. However, things may go wrong if + * (1) It is orphan. + * (2) It is assigned to the wrong parent. + * + * This check help debug the case (1), which seems to be the + * most likely problem we often face and which makes it difficult + * for people to debug unstable mmc tuning results. + */ + if (!rate) { + dev_err(host->dev, "%s: invalid clk rate\n", __func__); + return -EINVAL; + } + + nineties = degrees / 90; + remainder = (degrees % 90); + + /* + * Due to the inexact nature of the "fine" delay, we might + * actually go non-monotonic. We don't go _too_ monotonic + * though, so we should be OK. Here are options of how we may + * work: + * + * Ideally we end up with: + * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 + * + * On one extreme (if delay is actually 44ps): + * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 + * The other (if delay is actually 77ps): + * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 + * + * It's possible we might make a delay that is up to 25 + * degrees off from what we think we're making. That's OK + * though because we should be REALLY far from any bad range. + */ + + /* + * Convert to delay; do a little extra work to make sure we + * don't overflow 32-bit / 64-bit numbers. + */ + delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ + delay *= remainder; + delay = DIV_ROUND_CLOSEST(delay, + (rate / 1000) * 36 * + (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); + + delay_num = (u8) min_t(u32, delay, 255); + + raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; + raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; + raw_value |= nineties; + + if (sample) + mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); + else + mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); + + dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", + sample ? "sample" : "drv", degrees, delay_num, + rockchip_mmc_get_phase(host, sample) + ); + + return 0; +} + static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) { struct dw_mci_rockchip_priv_data *priv = host->priv; @@ -65,8 +188,12 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) } /* Make sure we use phases which we can enumerate with */ - if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS) - clk_set_phase(priv->sample_clk, priv->default_sample_phase); + if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS) { + if (priv->usrid == USRID_INTER_PHASE) + rockchip_mmc_set_phase(host, true, priv->default_sample_phase); + else + clk_set_phase(priv->sample_clk, priv->default_sample_phase); + } /* * Set the drive phase offset based on speed mode to achieve hold times. @@ -129,7 +256,10 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) break; } - clk_set_phase(priv->drv_clk, phase); + if (priv->usrid == USRID_INTER_PHASE) + rockchip_mmc_set_phase(host, false, phase); + else + clk_set_phase(priv->drv_clk, phase); } } @@ -147,7 +277,10 @@ static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode) if (inherit) { inherit = false; - i = clk_get_phase(priv->sample_clk) / 90 - 1; + if (priv->usrid == USRID_INTER_PHASE) + i = rockchip_mmc_get_phase(host, true) / 90; + else + i = clk_get_phase(priv->sample_clk) / 90 - 1; goto done; } @@ -156,7 +289,12 @@ static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode) if (degrees[i] == priv->last_degree) continue; - clk_set_phase(priv->sample_clk, degrees[i]); + u32 degree = degrees[i] + priv->last_degree + 90; + degree = degree % 360; + if (priv->usrid == USRID_INTER_PHASE) + rockchip_mmc_set_phase(host, true, degree); + else + clk_set_phase(priv->sample_clk, degree); if (!mmc_send_tuning(mmc, opcode, NULL)) break; } @@ -209,8 +347,15 @@ static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) /* Try each phase and extract good ranges */ for (i = 0; i < priv->num_phases; ) { - clk_set_phase(priv->sample_clk, - TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); + /* Cannot guarantee any phases larger than 270 would work well */ + if (TUNING_ITERATION_TO_PHASE(i, priv->num_phases) > 270) + break; + if (priv->usrid == USRID_INTER_PHASE) + rockchip_mmc_set_phase(host, true, + TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); + else + clk_set_phase(priv->sample_clk, + TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); v = !mmc_send_tuning(mmc, opcode, NULL); @@ -256,7 +401,10 @@ static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) } if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { - clk_set_phase(priv->sample_clk, priv->default_sample_phase); + if (priv->usrid == USRID_INTER_PHASE) + rockchip_mmc_set_phase(host, true, priv->default_sample_phase); + else + clk_set_phase(priv->sample_clk, priv->default_sample_phase); dev_info(host->dev, "All phases work, using default phase %d.", priv->default_sample_phase); goto free; @@ -296,9 +444,12 @@ static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) dev_info(host->dev, "Successfully tuned phase to %d\n", TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); - clk_set_phase(priv->sample_clk, - TUNING_ITERATION_TO_PHASE(middle_phase, - priv->num_phases)); + if (priv->usrid == USRID_INTER_PHASE) + rockchip_mmc_set_phase(host, true, TUNING_ITERATION_TO_PHASE(middle_phase, + priv->num_phases)); + else + clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(middle_phase, + priv->num_phases)); free: kfree(ranges); @@ -341,6 +492,7 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host) static int dw_mci_rockchip_init(struct dw_mci *host) { int ret, i; + struct dw_mci_rockchip_priv_data *priv = host->priv; /* It is slot 8 on Rockchip SoCs */ host->sdio_id0 = 8; @@ -364,6 +516,12 @@ static int dw_mci_rockchip_init(struct dw_mci *host) dev_warn(host->dev, "no valid minimum freq: %d\n", ret); } + priv->usrid = mci_readl(host, USRID); + if (priv->usrid == USRID_INTER_PHASE) { + priv->sample_clk = NULL; + priv->drv_clk = NULL; + } + return 0; }