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[176.184.49.210]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9ec8cd5sm118868966b.213.2024.08.02.10.10.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 02 Aug 2024 10:10:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S . Tsirkin" , BALATON Zoltan Subject: [PATCH-for-9.1 v4 1/2] hw/pci-host/gt64120: Set PCI base address register write mask Date: Fri, 2 Aug 2024 19:10:22 +0200 Message-ID: <20240802171023.85719-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240802171023.85719-1-philmd@linaro.org> References: <20240802171023.85719-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000fff] Since this device is only used by MIPS machines which aren't versioned, we don't need to update migration compat machinery. Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- hw/pci-host/gt64120.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..7df2855f32 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1213,17 +1215,27 @@ static void gt64120_realize(DeviceState *dev, Error **errp) static void gt64120_pci_realize(PCIDevice *d, Error **errp) { - /* FIXME: Malta specific hw assumptions ahead */ + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); } From patchwork Fri Aug 2 17:10:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 816274 Delivered-To: patch@linaro.org Received: by 2002:adf:e00d:0:b0:367:895a:4699 with SMTP id s13csp369602wrh; Fri, 2 Aug 2024 10:11:37 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV/sY49IQB/hHNo9WWOVUYUiiTvZzD3fkxQZDWMt9EKW5hmrEFuhIuX6GWe0HybMabS/m2e52iudm+hCEkbAt6F X-Google-Smtp-Source: AGHT+IF9bSFKFpmS/xvky4ss7bWQSkDgjqR29hYc1MMIMVrZSBGlaLz4epgDiU4hQcetbHum5lJN X-Received: by 2002:ad4:4429:0:b0:6bb:9a20:44a5 with SMTP id 6a1803df08f44-6bb9a204642mr34731516d6.17.1722618697601; Fri, 02 Aug 2024 10:11:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722618697; cv=none; d=google.com; s=arc-20160816; b=XTswdyJXuZilUwvPuHuLbdOV7yifIbcaDmn5UW6csGJ07lABaZxjfSwfrjLohghCXY BlAfFM8K+LFBTKed5dIoHe6q8VsNYlJBgqJJaAGYKOEk4BGYfQmUTA8PamFmyX9Vapp1 VOs7waBicXrRAsfRpnkxmKPfxHmgd/nO85AyKnPVX7jnpWnRPAKBGI37bExEvaJEsRA/ DfrcyJn9aM26AOmW14me1Gbee3Vs2HFtZ9FvzDnAdN07F/wZcCN7T3aGWVRFzMRVwYZT hxA2p/G+1K6Sy+WDBQiPQm+XmdqU9YQ9ekYze30dc7CZOV7VHI69Xm1oEyJt40OgSwLb dR7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TqUjxIdKSvsizFNHQdJuvAS4tLUxFNJv4u/cmIrhrNI=; fh=mcKaL/3nyZL5kAAKLAY4dCfokSjqtMUK8D0zZaOFtVA=; b=Xf8auvYWjpAGUaXgITdBO6M7bYd8cLhJweDZAHpVzuoH64TbE4Gx/TrD+4Bc7DfOUD JGRfI5SwaBhNfZay+1swqAvnZqQ3N9qNR7NmX2h1UY9Tbps1uz2y5is6KgGQ0LbIuxtF CLdErHwiYTAygOJh2pnBSFC+WcmVQaIPkFjS3nv095i6YxGa6QUvGpmEYPQWgRLy50kr a5W/xk/mHNen82C3ohYBIYKxogS2WzxxhsAMLeKYDX+zOwm70s4Rqp9Fxmu1maZuG5J8 DhdwVpjnUR23de8WR4/GI4+bVNbYMxQYOQNf714xpSbCObBtYN0CUgZD7a06MqOtZlqq 8anQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DuCGy1vl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.49.210]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d55ab8sm119274166b.131.2024.08.02.10.10.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 02 Aug 2024 10:10:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S . Tsirkin" , BALATON Zoltan Subject: [PATCH-for-9.1 v4 2/2] hw/pci-host/gt64120: Reset config registers during RESET phase Date: Fri, 2 Aug 2024 19:10:23 +0200 Message-ID: <20240802171023.85719-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240802171023.85719-1-philmd@linaro.org> References: <20240802171023.85719-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reset config values in the device RESET phase, not only once when the device is realized, because otherwise the device can use unknown values at reset. Since we are adding a new reset method, use the preferred Resettable API (for a simple leaf device reset, a DeviceClass::reset method and a ResettableClass::reset_hold method are essentially identical). Reported-by: Michael S. Tsirkin Reviewed-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/gt64120.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 7df2855f32..b0d05db577 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1217,17 +1217,24 @@ static void gt64120_pci_realize(PCIDevice *d, Error **errp) { /* Values from chapter 17.16 "PCI Configuration" */ - pci_set_word(d->config + PCI_COMMAND, 0); - pci_set_word(d->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); - pci_config_set_prog_interface(d->config, 0); - pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); +} + +static void gt64120_pci_reset_hold(Object *obj, ResetType type) +{ + PCIDevice *d = PCI_DEVICE(obj); + + /* Values from chapter 17.16 "PCI Configuration" */ + + pci_set_word(d->config + PCI_COMMAND, 0); + pci_set_word(d->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); + pci_config_set_prog_interface(d->config, 0); pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); @@ -1243,7 +1250,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.hold = gt64120_pci_reset_hold; k->realize = gt64120_pci_realize; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;