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Tsirkin" , BALATON Zoltan Subject: [PATCH-for-9.1 v3 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Date: Thu, 1 Aug 2024 17:00:20 +0200 Message-ID: <20240801150021.52977-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240801150021.52977-1-philmd@linaro.org> References: <20240801150021.52977-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reset config values in the device RESET phase, not only once when the device is realized, because otherwise the device can use unknown values at reset. Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Reported-by: Michael S. Tsirkin Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- hw/pci-host/gt64120.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..b68d647753 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1211,19 +1213,24 @@ static void gt64120_realize(DeviceState *dev, Error **errp) empty_slot_init("GT64120", 0, 0x20000000); } -static void gt64120_pci_realize(PCIDevice *d, Error **errp) +static void gt64120_pci_reset_hold(Object *obj, ResetType type) { - /* FIXME: Malta specific hw assumptions ahead */ + PCIDevice *d = PCI_DEVICE(obj); + + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); } @@ -1231,8 +1238,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - k->realize = gt64120_pci_realize; + rc->phases.hold = gt64120_pci_reset_hold; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; k->revision = 0x10; From patchwork Thu Aug 1 15:00:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 816046 Delivered-To: patch@linaro.org Received: by 2002:a5d:4acf:0:b0:367:895a:4699 with SMTP id y15csp1228039wrs; Thu, 1 Aug 2024 08:00:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1JpuU4KOL1ioMGI5FHrtQOiIOm04qy22mIqkORCxiogEmQZ7c8ZQ3VssshAkuep9VMzpV1dQgQoOi2FI6jFtm X-Google-Smtp-Source: AGHT+IFnAh0ABinzWoq+9fiYESUL2Z6k/o+BkpC+IJcDIRZuBimL+j4XMtwrdLsOYA8CcIzAql43 X-Received: by 2002:a05:6830:6515:b0:709:2721:ad44 with SMTP id 46e09a7af769-709b32183c6mr592516a34.12.1722524459048; Thu, 01 Aug 2024 08:00:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722524459; cv=none; d=google.com; s=arc-20160816; b=AcoY86RiRZb8H9CxZ7+CraROIVsjArSQKORdGnI3k4a3NZgFQptRiKYSjYWyWL2U9C yrW8VEn3SdSNRLfOrFWR9+f791/JaulnxXuyAH08JnJp7yfv5RS4+HQvCeJeUGT2bhNo ZimFYWTDOsApK4oGuII8TU/30PFfbXZ0s3i1ygGE90ilOzKVXWOe3u8GPVohqSCuNBuE Ks37PchUoCEOvdq2P85UaTHH6urKU2nyGAJd4tz6JWkwN8waHGmnE2ryjmc/jqDh5wPv z7a1NIshPf/iEs2ZhGh25XoSKOzQJsqm7JAaS+Rbax60aEhBKGorMNVb3adIzNEkHGxM TtOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=g3HJATsCsPCrOO9QF5DRAwhE7YAIM++c6LoE21bzlU0=; fh=mcKaL/3nyZL5kAAKLAY4dCfokSjqtMUK8D0zZaOFtVA=; b=Un1T04am2qTq1uX2w4aLH1Qpok3d6p6IwmgzN53VicDcw+D97cqLKHXDfvHdevXrPH cSg509sqHWMUvf4wcLDYKMS5j1RDA4khEf4Z97OwnfOALpezVjytG7CYiEC/O6UUteoJ AU5kP2q8yhUuVvACBKSzs1eDVOxQxC1eLQ4lkwCEyaT23toEVKUiMC49Oq0eOH+ut+C9 r4TLjJFK6yDcJVlLsSUA5NMquiUA+c4E7lNdFNIIJQXjJPYQCfHzmRx/uV+OeBttCHgN w+bzu/ZRrjq0+0XFJYroWgdUT17xRdIf7fb5ngHT/2piqkdfNzcDBnbTRabfnnObg0qh 93Ng==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P2GK3cHF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , BALATON Zoltan Subject: [PATCH-for-9.1 v3 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Date: Thu, 1 Aug 2024 17:00:21 +0200 Message-ID: <20240801150021.52977-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240801150021.52977-1-philmd@linaro.org> References: <20240801150021.52977-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000fff] Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/gt64120.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index b68d647753..344baf55db 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);