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Tsirkin" Subject: [PATCH-for-9.1 v2 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Date: Thu, 1 Aug 2024 16:56:29 +0200 Message-ID: <20240801145630.52680-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240801145630.52680-1-philmd@linaro.org> References: <20240801145630.52680-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reset config values in the device RESET phase, not only once when the device is realized, because otherwise the device can use unknown values at reset. Reported-by: Michael S. Tsirkin Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/gt64120.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index e02efc9e2e..b68d647753 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1,6 +1,8 @@ /* * QEMU GT64120 PCI host * + * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999) + * * Copyright (c) 2006,2007 Aurelien Jarno * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -1211,19 +1213,24 @@ static void gt64120_realize(DeviceState *dev, Error **errp) empty_slot_init("GT64120", 0, 0x20000000); } -static void gt64120_pci_realize(PCIDevice *d, Error **errp) +static void gt64120_pci_reset_hold(Object *obj, ResetType type) { - /* FIXME: Malta specific hw assumptions ahead */ + PCIDevice *d = PCI_DEVICE(obj); + + /* Values from chapter 17.16 "PCI Configuration" */ + pci_set_word(d->config + PCI_COMMAND, 0); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); + pci_set_byte(d->config + 0x3d, 0x01); } @@ -1231,8 +1238,9 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - k->realize = gt64120_pci_realize; + rc->phases.hold = gt64120_pci_reset_hold; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; k->revision = 0x10; From patchwork Thu Aug 1 14:56:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 816043 Delivered-To: patch@linaro.org Received: by 2002:a5d:4acf:0:b0:367:895a:4699 with SMTP id y15csp1226421wrs; Thu, 1 Aug 2024 07:57:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCURdAES2oUCwWYVpNPaPIOpuI9EBnjimQe1juQ1vodF5Msc/LgOVK4bZbt2ifaEBpdxL2PsYvnts/no/7CuJ2Ok X-Google-Smtp-Source: AGHT+IG/HiJB7Ox6shjo6f+KnMNDbjsmZbi9P28R7cHXHIVx7sZwO/FqECtPH1qe15+raNlI5OTo X-Received: by 2002:a05:620a:454b:b0:79c:130:452b with SMTP id af79cd13be357-7a34efd8362mr33250985a.47.1722524240734; Thu, 01 Aug 2024 07:57:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722524240; cv=none; d=google.com; s=arc-20160816; b=J/XGQ/TP9JkkEQRskyu6hrRDckFWlnCmYQ2qX0hFLRor5+pDw4SmAUMRCqpyTNp68c Fu7c2aVFQEbGMypwp5u0wJFT8tmP8hegfqcb8dblhzahtuD746IbQE+YML9UtEr5vix8 BRo6F+vnxQ6XJ51Akro62lxABe+vzvFNSTx4DmyWv+jxpL4Qirig9Kb/lCxZL3qXDeW/ 5uPJ2VPlpoA+73aav1iErlXXnLd1fSS/tL9cdWmx8RLWopZzm+Gj9QseHw0TU3JcrnDJ /pmTufI8CwuSUGiagQZjo1BYR8l85Tr5jLAqWwrcSdRCVNlxY2c2zONOODT7ov14G0fT 5tCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=McDzB/oHM/+Tt1V4WsDekmxT5WVMgu7zHufwqqju/fY=; fh=ONCulxPjYYJp3/W4zgS51SgFolXEDeCaTboklGFIL5Q=; b=l43wASE6W9ZdBas0AuyEVu5zbOyQAn/Hb5N3CrFkiQ2rBCs/+TR16TJ2HwobbnNq0o 7u8Ztx+/K3gbPGl8Cr9cW+JOgtb1rs6Du53Pwh+kxSLDnyCmjjcUc1XdXKAk7c9Uk9ca N+d+X/ci0oHE2A9iDjDTogxZIRNZvTiaBpZNrr1i4dktoZ10wxy3BRji/UK1ns1gURTf bkMZEW9ZcHc8BCDzu1mr0oIYdGS0iWx7vPjlsXZCVq9ORivt5oaPSzmhAqa8iBswtDje h8usTllez/uBCUYBpsm8lUiCupQyqM2C6Ih8ZKey/Q/x100qo8wfAFnI9QW2VJz+65um Hmxw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qAUTiFiS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" Subject: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Date: Thu, 1 Aug 2024 16:56:30 +0200 Message-ID: <20240801145630.52680-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240801145630.52680-1-philmd@linaro.org> References: <20240801145630.52680-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When booting Linux we see: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size) pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size) This is due to missing base address register write mask. Add it to get: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff] pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff] pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000 pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref] pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff] pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff] pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff] pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007] Mention the datasheet referenced. Remove the "Malta assumptions ahead" comment since the reset values from the datasheet are used. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/gt64120.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index b68d647753..344baf55db 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1224,6 +1224,13 @@ static void gt64120_pci_reset_hold(Object *obj, ResetType type) PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); pci_config_set_prog_interface(d->config, 0); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff009); + pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); + pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);