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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-428e08012d7sm29657435e9.22.2024.08.01.07.23.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 07:23:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/4] hw/arm/mps2-tz.c: fix RX/TX interrupts order Date: Thu, 1 Aug 2024 15:23:19 +0100 Message-Id: <20240801142322.3948866-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240801142322.3948866-1-peter.maydell@linaro.org> References: <20240801142322.3948866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Marco Palumbi The order of the RX and TX interrupts are swapped. This commit fixes the order as per the following documents: * https://developer.arm.com/documentation/dai0505/latest/ * https://developer.arm.com/documentation/dai0521/latest/ * https://developer.arm.com/documentation/dai0524/latest/ * https://developer.arm.com/documentation/dai0547/latest/ Cc: qemu-stable@nongnu.org Signed-off-by: Marco Palumbi Message-id: 20240730073123.72992-1-marco@palumbi.it Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index a2d18afd792..aec57c0d686 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -435,7 +435,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs, const PPCExtraData *extradata) { - /* The irq[] array is tx, rx, combined, in that order */ + /* The irq[] array is rx, tx, combined, in that order */ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; @@ -447,8 +447,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s = SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); From patchwork Thu Aug 1 14:23:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 816042 Delivered-To: patch@linaro.org Received: by 2002:a5d:4acf:0:b0:367:895a:4699 with SMTP id y15csp1212263wrs; Thu, 1 Aug 2024 07:24:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUM9Bkmz4zHk78VyMdqx+guo54jJsBXK1Z1K6j8o30s7izNxWFTCIqBTs90j9BV+wwEfRiHyAZ3WsDGRP0uLEaB X-Google-Smtp-Source: AGHT+IHAIlwxkPun786ru3O5TlQC/LgrmKbQI2qdJmEXzQFOI6fzyoyFJh/04XvmAkBw9saQ+AHq X-Received: by 2002:a05:6902:124a:b0:e0b:b162:ef78 with SMTP id 3f1490d57ef6-e0bdded8ccfmr349068276.0.1722522272949; Thu, 01 Aug 2024 07:24:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722522272; cv=none; d=google.com; s=arc-20160816; b=wF92wxjAQ/iq6P6NAVw0TnOyQ41HVhpsEddzOUkE4x26X4PYwOb5hI6A0YXBCDiJGT y/2UC8f1gYbAoVgQnQ8dPk/qsm7SgEeA9Lrg4hLIW+uPGLaOT1gAm9rhGJFWnXFy2Vr6 JkMYDQyDwDAIsFpWtr5wkZYG9ZfMMZvm4o9WeSkQzCh6j09YnghBNI3GFa+oUtGqHuzu Evg8Q610tyFJXB8aVG/YVKjs4+cbnJp+zUMCLcZLqd7WySKqO7d0vU+5vwCpOyTp0lnO Zuk105zPc7GgmZ6CdIrTxRvvL79aIGLccXRtSzDk8w+HmstCJ8fLyTr3SszNYwUlp/hL wnmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I/6CNtfkx/vK3/2m6asJcZw+ghBegtW4R7IRgfjVD4E=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QEOu74THlqXi0f+wEksyahN87Hma4R5jT+4DaBiBPIFmUiFJD7HgZlZTY9NSgtv+2+ J80y/uffYWeXcJ91qMkxGrxRAklZlIamVUdRGtuba5Pr5yTJTCX8PK3nqeUrCtMaePHZ g2KEKSTAd9WEL8HQlBoExkkEBOz3cZ/lnVkUc4Mu3BEUaZRcjf48Z33363dyKfpadWHL nf0Utlcxwu36d82raDVVLdNlwVdb/dwn8L83/rYt1iPl8iqA3s16p/IX/2MTAUAhVmxj WkAH44HQ4CBWRj9hIEKuJcllPBivCXrGluetdBhW/dKT3RBDtGXoQcMT/IoodJfx9A1j EUqg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ekt+TZyK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-428e08012d7sm29657435e9.22.2024.08.01.07.23.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 07:23:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/4] accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic Date: Thu, 1 Aug 2024 15:23:20 +0100 Message-Id: <20240801142322.3948866-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240801142322.3948866-1-peter.maydell@linaro.org> References: <20240801142322.3948866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Salil Mehta Loop should exit prematurely on successfully finding out the parked vCPU (struct KVMParkedVcpu) in the 'struct KVMState' maintained 'kvm_parked_vcpus' list of parked vCPUs. Fixes: Coverity CID 1558552 Fixes: 08c3286822 ("accel/kvm: Extract common KVM vCPU {creation,parking} code") Reported-by: Peter Maydell Signed-off-by: Salil Mehta Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan Reviewed-by: Zhao Liu Reviewed-by: Igor Mammedov Message-id: 20240725145132.99355-1-salil.mehta@huawei.com Suggested-by: Peter Maydell Message-ID: Signed-off-by: Salil Mehta Signed-off-by: Peter Maydell --- accel/kvm/kvm-all.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index e1d13863063..75d11a07b2b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -362,6 +362,7 @@ int kvm_unpark_vcpu(KVMState *s, unsigned long vcpu_id) QLIST_REMOVE(cpu, node); kvm_fd = cpu->kvm_fd; g_free(cpu); + break; } } From patchwork Thu Aug 1 14:23:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 816039 Delivered-To: patch@linaro.org Received: by 2002:a5d:4acf:0:b0:367:895a:4699 with SMTP id y15csp1212134wrs; Thu, 1 Aug 2024 07:24:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVYAp5scR/wXmF5Nywv8y25uqPAltWDKbMieudRQihPsHUIBW3J+dnQgeZwGIT9o0MAvb5wFURtxVhc1v2bDeeX X-Google-Smtp-Source: AGHT+IGtZdKhThnZtDfooU/V87qxDXHbLmpkdQMc+yrQAMRy/9NJhwP9PVCUo5cPfw2O1r0hxBdJ X-Received: by 2002:a05:622a:286:b0:447:f5d2:7c5f with SMTP id d75a77b69052e-451892c1097mr2908421cf.53.1722522257836; Thu, 01 Aug 2024 07:24:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722522257; cv=none; d=google.com; s=arc-20160816; b=OTfXLzF/zSsD7lI39UtS9YqnQsyGzQlQXvWjgKZ95Z/eYpHVZD/wanO2rwtA6BQstc RFzPozna2OyOzhontOk5McGStlJVwqiNwr6lQZ979AbjW3kcim3H8naxJcod/WEfUqpo /9ued04V0T36S8ckbS5IfUspCWnk3+o0ldZ8qtAq8U+1iSn1smEhsWHHF798kTKLwgdV 0CaKKf5tLEBLnDGMLYcHpQXS/k555cfW5jNz3vC4fWgpdexYtzEIyhybvL5z8QXsbG/I phXg73puogFvL8gJHAPgolKXuPN+b/LQ05qpzAQlBtOkJ6hRAujyzdUrMiYYmRVMjcNw MCdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=z0Rcx78XVil5biE/RI1myOYEZI1VSLw6RG7NHHvURqE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=uqNVddNPAWhgOmF+OCR4ewMtQCqtc3pj7jo97v4u9WVvFLJAUM2OP9q5MZc8ndpYCa Wqli5Ril2iYLB6n6/kXntA3KFXzsSsew8jj8Dn1eIIK3VO3TjDx1yyg6fcky2JMxxZ0x aMiH2lcUFtmY9nxAfw09C+KBVBGRKtfCpiUyYdxXpljsP+3kGMGCO5IsnWEPo1AUThln UgEeOFTjTR9/X3ZnUWd0BhAxuLu8wpn6lvbHQJOK6ksRIrujiU33wtgCcqGlBNDJQcss ajph3geTyoLuv0y3rn8gBy6A9ytSMemOkSD5DKCbOPFFQTM113JszeLShZeYslKWUAO/ ON8A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LLi6/PqJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-428e08012d7sm29657435e9.22.2024.08.01.07.23.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 07:23:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/4] target/arm: Handle denormals correctly for FMOPA (widening) Date: Thu, 1 Aug 2024 15:23:21 +0100 Message-Id: <20240801142322.3948866-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240801142322.3948866-1-peter.maydell@linaro.org> References: <20240801142322.3948866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The FMOPA (widening) SME instruction takes pairs of half-precision floating point values, widens them to single-precision, does a two-way dot product and accumulates the results into a single-precision destination. We don't quite correctly handle the FPCR bits FZ and FZ16 which control flushing of denormal inputs and outputs. This is because at the moment we pass a single float_status value to the helper function, which then uses that configuration for all the fp operations it does. However, because the inputs to this operation are float16 and the outputs are float32 we need to use the fp_status_f16 for the float16 input widening but the normal fp_status for everything else. Otherwise we will apply the flushing control FPCR.FZ16 to the 32-bit output rather than the FPCR.FZ control, and incorrectly flush a denormal output to zero when we should not (or vice-versa). (In commit 207d30b5fdb5b we tried to fix the FZ handling but didn't get it right, switching from "use FPCR.FZ for everything" to "use FPCR.FZ16 for everything".) Pass the CPU env to the sme_fmopa_h helper instead of an fp_status pointer, and have the helper pass an extra fp_status into the f16_dotadd() function so that we can use the right status for the right parts of this operation. Cc: qemu-stable@nongnu.org Fixes: 207d30b5fdb5 ("target/arm: Use FPST_F16 for SME FMOPA (widening)") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2373 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/helper-sme.h | 2 +- target/arm/tcg/sme_helper.c | 39 +++++++++++++++++++++++----------- target/arm/tcg/translate-sme.c | 25 ++++++++++++++++++++-- 3 files changed, 51 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h index 27eef49a11e..d22bf9d21b0 100644 --- a/target/arm/tcg/helper-sme.h +++ b/target/arm/tcg/helper-sme.h @@ -121,7 +121,7 @@ DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, ptr, ptr, i32) + void, ptr, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 3ba826a6ceb..02106809ce1 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -992,12 +992,23 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) } static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, - float_status *s_std, float_status *s_odd) + float_status *s_f16, float_status *s_std, + float_status *s_odd) { - float64 e1r = float16_to_float64(e1 & 0xffff, true, s_std); - float64 e1c = float16_to_float64(e1 >> 16, true, s_std); - float64 e2r = float16_to_float64(e2 & 0xffff, true, s_std); - float64 e2c = float16_to_float64(e2 >> 16, true, s_std); + /* + * We need three different float_status for different parts of this + * operation: + * - the input conversion of the float16 values must use the + * f16-specific float_status, so that the FPCR.FZ16 control is applied + * - operations on float32 including the final accumulation must use + * the normal float_status, so that FPCR.FZ is applied + * - we have pre-set-up copy of s_std which is set to round-to-odd, + * for the multiply (see below) + */ + float64 e1r = float16_to_float64(e1 & 0xffff, true, s_f16); + float64 e1c = float16_to_float64(e1 >> 16, true, s_f16); + float64 e2r = float16_to_float64(e2 & 0xffff, true, s_f16); + float64 e2c = float16_to_float64(e2 >> 16, true, s_f16); float64 t64; float32 t32; @@ -1019,20 +1030,23 @@ static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, } void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, - void *vpm, void *vst, uint32_t desc) + void *vpm, CPUARMState *env, uint32_t desc) { intptr_t row, col, oprsz = simd_maxsz(desc); uint32_t neg = simd_data(desc) * 0x80008000u; uint16_t *pn = vpn, *pm = vpm; - float_status fpst_odd, fpst_std; + float_status fpst_odd, fpst_std, fpst_f16; /* - * Make a copy of float_status because this operation does not - * update the cumulative fp exception status. It also produces - * default nans. Make a second copy with round-to-odd -- see above. + * Make copies of fp_status and fp_status_f16, because this operation + * does not update the cumulative fp exception status. It also + * produces default NaNs. We also need a second copy of fp_status with + * round-to-odd -- see above. */ - fpst_std = *(float_status *)vst; + fpst_f16 = env->vfp.fp_status_f16; + fpst_std = env->vfp.fp_status; set_default_nan_mode(true, &fpst_std); + set_default_nan_mode(true, &fpst_f16); fpst_odd = fpst_std; set_float_rounding_mode(float_round_to_odd, &fpst_odd); @@ -1052,7 +1066,8 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, uint32_t m = *(uint32_t *)(vzm + H1_4(col)); m = f16mop_adj_pair(m, pcol, 0); - *a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); + *a = f16_dotadd(*a, n, m, + &fpst_f16, &fpst_std, &fpst_odd); } col += 4; pcol >>= 4; diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index a50a419af27..ae42ddef7b3 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -334,8 +334,29 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, return true; } -TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, - MO_32, FPST_FPCR_F16, gen_helper_sme_fmopa_h) +static bool do_outprod_env(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + int svl = streaming_vec_reg_size(s); + uint32_t desc = simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + za = get_tile(s, esz, a->zad); + zn = vec_full_reg_ptr(s, a->zn); + zm = vec_full_reg_ptr(s, a->zm); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_env, tcg_constant_i32(desc)); + return true; +} + +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_env, a, + MO_32, gen_helper_sme_fmopa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, FPST_FPCR, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, From patchwork Thu Aug 1 14:23:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 816038 Delivered-To: patch@linaro.org Received: by 2002:a5d:4acf:0:b0:367:895a:4699 with SMTP id y15csp1212135wrs; Thu, 1 Aug 2024 07:24:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1kWnlsJBPNUkx68eBMQPeR3rVKK4g8aPj88e6eCELCKuYrkoF08YVG4JB48nPzGC0M6JwwRexgjKqflmiGtiN X-Google-Smtp-Source: AGHT+IEA7vOW0u+dbMCcvOTpqmb0x5T8+tw4EstnD834UWxcI9/+EQPfjj7X4wJcoGLwsDhHIXEm X-Received: by 2002:a05:6808:2110:b0:3db:42b2:ee28 with SMTP id 5614622812f47-3db5584dbc0mr229746b6e.51.1722522257940; Thu, 01 Aug 2024 07:24:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1722522257; cv=none; d=google.com; s=arc-20160816; b=GSqJOaEvVr8aT8oB/UsZbPZBkmkOzcduQnAl/ddduzYTDkCceY5BzgpvBUn8OZ7t2Q +gq2jHIxgU4rReqs3Epf2qStdIiei6bG9SoiOVbomWj1sKcP78GPUPVZGGE9n3LcHerS jCnbr8pngK6bYosogsVrGLJjGTbSZJCJFQlvfoXfDBtXDe8HdvnWrn7YoUzWR4ovGfhU FT64qLM2vBTo+sEuHlZrimWE+JXLTJFbSBmLsNMSvAu6juuY6gu5IeXRUXBKXgn7i+Tn rq+lJguwY796DfGSou+G+q413EIm5BJpiV5Y9d5noBOIQol3edwEH5uu3lcqtqX9vMNx tRFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bek6kRqgfRzW+L/s2A9z/Tq60M2bck1dCjbLVYSP28w=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=xG6Op1EuuCJGy0VwtEUgCdPFwIMGmpHMoOGXDrWJwYDBM99zZNsAFSUUfSWvIEOM2m +rgytZGMUf9+1wsLg76hMio2rm5bkkthOsA6pQrvSNB1gSZiYvrCSI55lYYQxSXMs917 9sYtovMWmsH5IQvte8vepaBIN4FmdgzSLDG+LvLDHdnaEjqv4dFQn9ZMP/ULRZrdRxcv EI7Pc5aUB0LjKWpTKv6NTL7DyJGodnTI3elM+2x1muLmu/XDXOQpkXdNcK4OMMXvo5Lp WxKRCCmZtl2J9BqsBsyz5Wt+//rTZIHnm3K0tvhE21dnoiyfOlE41RiRCT83QDMxoPbX IQwA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s8uVYjeP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-428e08012d7sm29657435e9.22.2024.08.01.07.23.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 07:23:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/4] target/xtensa: Correct assert condition in handle_interrupt() Date: Thu, 1 Aug 2024 15:23:22 +0100 Message-Id: <20240801142322.3948866-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240801142322.3948866-1-peter.maydell@linaro.org> References: <20240801142322.3948866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit ad18376b90c8101 we added an assert that the level value was in-bounds for the array we're about to index into. However, the assert condition is wrong -- env->config->interrupt_vector is an array of uint32_t, so we should bounds check the index against ARRAY_SIZE(...), not against sizeof(). Resolves: Coverity CID 1507131 Fixes: ad18376b90c8101 ("target/xtensa: Assert that interrupt level is within bounds") Signed-off-by: Peter Maydell Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240731172246.3682311-1-peter.maydell@linaro.org --- target/xtensa/exc_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 0514c2c1f32..ca629f071d1 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -171,7 +171,7 @@ static void handle_interrupt(CPUXtensaState *env) if (level > 1) { /* env->config->nlevel check should have ensured this */ - assert(level < sizeof(env->config->interrupt_vector)); + assert(level < ARRAY_SIZE(env->config->interrupt_vector)); env->sregs[EPC1 + level - 1] = env->pc; env->sregs[EPS2 + level - 2] = env->sregs[PS];