From patchwork Wed Jul 31 10:50:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 815726 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80C41A7F79; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; cv=none; b=qEv/sreyniTbRlFlJIkDqWRQoeIcuIJSHlDj/EJPkvPhgyvew+Tgkpz1pv+qqrcKLrizIVCU9s2TnLwCBFKR54sGJF1lDhPJZNYkza9vMVx2SBiNSnOqvDc5lDddclSvH6QdCrWyJ93vwXHyIL2tbM7WqjmDXrXxjxDzvhIHMjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; c=relaxed/simple; bh=+Tkqhar4vQYGZIgL28NlgG1tVNG3i9So+0zA8BWKYOU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WG5NB+IMjyH4csRZKvmWoo2lHr0qO+g5C+1giO3yD/rL/WnUonbs/zfeE1PzrXnr6rklchuhMblGcVpxrr8u3dwOreBIYs1Vg+VhvsuM1lrmyY+aGWc6h3ipRmOP7ca5gCLlRpfLQrsS9KbE/svfcI70kOmGzxClCJCkpjtJYTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sfAeW2Q3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sfAeW2Q3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4D40BC4AF0C; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=+Tkqhar4vQYGZIgL28NlgG1tVNG3i9So+0zA8BWKYOU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sfAeW2Q3INQ/Wgs52gQOY7e1a3f0KB5NN3Z5uAAYgjsrcr/iQLUhnkMZgy54B93Os fNQUSkgrA8JM5BFdcUwT6L+Hvqq2WLFosiEJ0+VWmuN/QXVEOMhFo0OJPQCpD3qsfl RvyZ2vJ2ULqzxWbw11R8if+NG6dotqI0h1ExnQW2lFnWYOrxNQJM2I+22bocDd3JvL 01o9NALX5HJXTdybl1UFZqwk1K9Q0Npp7DAHkUozkHjoU2PdkTtDSnjtEMuns1hIXF k7TW31csjRDJb1CWSvC5joQhApzn/Ig/laloVc+QbNdQiqtuZykfeyySTNbGRIL0eS 2/7BhJTg4KeFA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3687BC52D6D; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:05 +0530 Subject: [PATCH v3 02/13] PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-2-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1256; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=B8RUdvVv9QEg4h2fDtSWIh3luhRVOKTDULQMHpO/Rk0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbiPvlBYFkyQTm0FUkbIjHMH/+/ZAg11HCjV xz5OPlMCDyJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4gAKCRBVnxHm/pHO 9fAkB/9WOZ4Pm2vf1vP5hHdw6Ggj3kP1To3Upq1DZPNUvBuxAfX3SX7dC3Ec1cwU48Ig/RWN8fR 4mB7xUJOFQa+XKdRaAp4nH/I39Pfnze4V4UZuoPuTMvZ6186dX4gm3alkr3ElT1RbwkKXLmUfMt Ml7vht4ZW7OgGLMCWTsNQDRUaddRLqmlrmyhniidJYOYFV/mzfO8HSXDkgwLh23sgVmLoqQ+zWI 5ttBWDYgVU55MHsvjIbhRaG3VJaSRo3CtuxjytmhZu5yJ7EoSDLBQSPzQNVXsPOcj0jLcqVD9uJ 2XmiqdsNSDOyUwy8/85yTfrnuvIoN1yGMptRMN+npS3NWfdc X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Current error message just prints the contents of PARF_INT_ALL_STATUS register as if like the IRQ event number. It could mislead the users. Reword it to make it clear that the error message is actually showing the interrupt status register to help debug spurious IRQ events. While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ storm won't flood the kernel log buffer. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 972a90eba494..0bb0a056dd8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -679,7 +679,8 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dw_pcie_ep_linkup(&pci->ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; } else { - dev_err(dev, "Received unknown event: %d\n", status); + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); } return IRQ_HANDLED; From patchwork Wed Jul 31 10:50:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 815725 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D17F81AC44F; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; cv=none; b=FJJujanlLEc2F6a90LXu/3GZe9RwsxfruJUgcYZR2uAUjXupbkCaa2sh7ompVTc+8dnbln3fYXRlfP5rjcIrlGVsk/IDacdUCzn1NdQEH7x93nX+cYXJmkkex7CpbIZAW4h3H5BiSLCdgasTUFLawguIW4Ww1JBF6lAQn8AEgE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; c=relaxed/simple; bh=lzIKtgPAyTFqAhhNBnr2RiOhErj0a7AEhzCZTqA8TS4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ER74B4t8ME5IlZfxFs5pZr4ZToS+KMiYYT9pCECAzyrYizBtW2UM6d7LoU7+r6Jgq0cogPbj80J6xAch/MN/Itj8tbFfAEfCJ4GEd+Ibhq4Weuqfx4C3Jk5w126vvjF1V1EyIjhKI6WyHUTaf5Xrp5shO7qJEJ+rq5RWfdOcvtU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZEgozGST; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZEgozGST" Received: by smtp.kernel.org (Postfix) with ESMTPS id 61E53C4AF16; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=lzIKtgPAyTFqAhhNBnr2RiOhErj0a7AEhzCZTqA8TS4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZEgozGSTxf5hjpf6pil+qz69VCUhJrWF4Sv1tsCH8q4LhEsUQgVTXKN7Q2zShN/8z pzO1SeE03HWA5ZVnwkBm/sKwgFaI6KRpC7Te/TYh1av0DqXr3qEf5SFILtwy6YlShd 20pm5dwnlYP7n529ngU2MxfzzStBdbeM01XHJqCsaONwksuj4Hd/+Yh3UVdLzeUaen dIDE8SM0JcJ5EYVFT6Kl+qLpgWErVnjahGMlwTs/Y2QWiv1faEEevaufiExM/fBKrT +atCHkvIZI1mxs+Uy0e/qI8VrQiTm6s8tS25x4Kdf30ReEX6TqL0xMRNTVTsMMwAJI 6w7cEty/AIQmA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55D37C3DA7F; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:07 +0530 Subject: [PATCH v3 04/13] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-4-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2076; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=gFM57NfjI22HI5zO2G4ZyvVdTIrBmxWoCkDYpg/zh4Q=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbiAb7YQ78WmQL+3pg/asHYaUv2cb/2l//Pm jyYj96EdqiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4gAKCRBVnxHm/pHO 9WmQB/9si9S+OmgvS+y51lNqf3cu9EerZUXmpMp9BQPH2G/MbNfuM5P1TnLhFhuNHIDsykyo6kf TSKZDjpNjKUtwUKI8/6fVP4laVkYCwd11+WzWiAigELfLKB+3whUNPxIcqxeRXWNFIkGvAHhuW5 oNTVEpq1kZdGX3LVsVX5QLw+c19f8RLzW3/vOnHzernLgouZFW/RT/Pt+ZAm3APCnE34rMIP4a5 2qErJkVovUD40tPkIjPs8tm/Xmj0mVhF4rzufUqkbgiVqSedMqVddEeo+Ro3TCNBK3uO+jD7qsp YbvEvOq0n3LUQ1jVGxkBdTrrxEwOG5Qy1pC3128GwI+Bk4Td X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 11 +++++++++++ Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index 0b5456ee21eb..f75000e3093d 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -42,6 +42,17 @@ properties: default: 1 maximum: 16 + linux,pci-domain: + description: + If present this property assigns a fixed PCI domain number to a PCI + Endpoint Controller, otherwise an unstable (across boots) unique number + will be assigned. It is required to either not set this property at all + or set it for all PCI endpoint controllers in the system, otherwise + potentially conflicting domain numbers may be assigned to endpoint + controllers. The domain number for each endpoint controller in the system + must be unique. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..1226ee5d08d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -280,4 +280,5 @@ examples: phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; }; From patchwork Wed Jul 31 10:50:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 815724 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F20E11AD3FD; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tADzGTzL" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7E618C4AF55; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=Q0K9d834m1CQs7L6nrAh8i7+sVcfqEywtcVG4UQJkH8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tADzGTzL2PY4PO3jGpgBwqKvvBdwToY/m496qAKPpASdKugGWKnPsmuMx/qEZbs8M zwCF4w9vUjYhdFtReNXpuwCqheBi1ufHeQMaIFn1R2TdTPsrfa9c/m/fWTW3Jr2wYQ GqqrPx7c77RglLXsY63t+ZLSLLfLOPL/AjpiG4gOrWmuBT/W/uhNNluibjXlhcEWah hkJlqw2JwUZgtRTnR4BGNY6WPzBrZKw6a3DRyBvXdIC28/SzCTaK+17fiVswOfEsZ0 YaGwbwWIhDcF6mp6vPU7S2T1uMaBYv6bBJF+VP0sJ6cX4G7olkNVQVMKt3EfuBrhxJ PZ52/zg+7v0Uw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72B07C52D6D; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:09 +0530 Subject: [PATCH v3 06/13] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-6-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2506; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=XIcVOnjgniiauSeztC2lx8OOqKBgQWPfU4mlz79I8zw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbjGGaJwKyTvqkljnvL/tqJQd7uQOxHG/eYT WrBEXYQUN2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4wAKCRBVnxHm/pHO 9WXwB/9aBNdScpakeH3ElJt0m4uB42SoSv/w09HA2ygZJIMQokLZ/4NylCvJKLQZXESG8sTXEwy ITY1NFLtltXxVWFExWLPkHqS5fr9r3ImF5/s6M0mRF/+gQYDytgWia3UkiHsBAYPvinFYU9010r aTYBuGk40rxSFqQie513l6Oc/fwGtDg5lGLHoMM8CtnLyeLOxYZihW3gBWBgVvaBrUxMxDcS2+e Vxaga9S1XfQ+ZuWn6xJKICujexiTeNyN6w2Cq/YNvnDJgARFPWW0TNXUsF5si7ANp8I+ETlzqpW +T5r6DvqlEXJiIbsvW9L2TdEJyNFSb3MKJfQjFTdHDtkdIk+ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Currently, the IRQ device name for both of these IRQs doesn't have Qcom specific prefix and PCIe domain number. This causes 2 issues: 1. Pollutes the global IRQ namespace since 'global' is a common name. 2. When more than one EP controller instance is present in the SoC, naming conflict will occur. Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ names to uniquely identify the IRQs and also to fix the above mentioned issues. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0bb0a056dd8f..d0a27fa6fdc8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -711,8 +711,15 @@ static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { + struct device *dev = pcie_ep->pci.dev; + char *name; int ret; + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); if (pcie_ep->global_irq < 0) return pcie_ep->global_irq; @@ -720,18 +727,23 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, qcom_pcie_ep_global_irq_thread, IRQF_ONESHOT, - "global_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request Global IRQ\n"); return ret; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "perst_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); disable_irq(pcie_ep->global_irq); From patchwork Wed Jul 31 10:50:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 815722 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195C31AD9C8; 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a=openpgp-sha256; l=1289; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=YKSy5vPklQvLJA99UbdPy4mFyoiPQChYvArhByAGkpA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbkM82d8e+WMgMaI3vqUmCsTncdYX2eiPFOn D6P6KY6mfCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW5AAKCRBVnxHm/pHO 9YEMB/96o/GgxfmiCVskdaEk9lPriojnKoJwUFGZq0mTGD5vspGq5yt7OLqRTc/vStU7UIJY+a9 3yHXH8lmdrhtjcvwvOlWDCzgwgxFOgh6MvqlWoyYVnJrXyOFy+F0eNMsiC0BoqfZOJsem28kgWT hP2l+54I7J/ulzCMjKc+rrRE3ffQq6YyPEheNyKoG3bZ/jWNpoHqodHXUqXXvLA5BUzWBjG0KRZ sWb9TNcPiz3rjPG53KFicTsoUTDDKbNS7CKp7kimQV8lwYrVqYRU66gVPePhCAn6ncejK+a4d1G cjpR1PG1aN2a1ISPBJYeZO3F/zor/dTi4OMRp/uLoEy4S+dS X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SA8775P SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..198b39abde97 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4618,6 +4618,7 @@ pcie0_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -4775,6 +4776,7 @@ pcie1_ep: pcie-ep@1c10000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; + linux,pci-domain = <1>; status = "disabled"; }; From patchwork Wed Jul 31 10:50:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 815723 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 005371AD3FE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gFW3TRwL" Received: by smtp.kernel.org (Postfix) with ESMTPS id C5A46C4DE03; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=FDAyuVhiZfadF2+raswbfNBa/0aOcWVYQKsBdgtWLgs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gFW3TRwLRi6dvDK10BKiOU9WO6I3foMmtFaUvMylpGyhbBdU8XHCG5sLfuDxVXxRL GXPXojC9e0xvu2xyUIE83Of/VXU4Aa5mjD9upw9ON4gHGNvstKdWJPAzaQB4sqGyTd 6SHqn/WSCvF6tufSYzDojmW8ymloB+lUPkHjFFzRAgzZC1thP4SKfU7dmC0E3F0aHz ZSNIQRFIxRvxiJwArMmbb+1pkXM/mKPwdVdB56GxuEkVK8nWHaD20w3fnz+Vc/OveE RBq8QX/ckrky5R562BHXgDD3XFbWhNWF1JyTFS/JoZXVQ/R6KkhNbkwsY4qWrraiFU GRSo2YJrsvzAg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD052C52D54; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:14 +0530 Subject: [PATCH v3 11/13] dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-11-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Though adding a new interrupt will break the ABI, it is required to accurately describe the hardware. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index d8c0afaa4b19..46bd59eefadb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -55,8 +55,8 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 interrupt-names: items: @@ -68,6 +68,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global operating-points-v2: true opp-table: @@ -149,9 +150,10 @@ examples: , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; 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Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:16 +0530 Subject: [PATCH v3 13/13] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-13-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2085; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; 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This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..564b071eb77c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1787,7 +1787,8 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1795,7 +1796,8 @@ pcie0: pcie@1c00000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1949,7 +1951,8 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1957,7 +1960,8 @@ pcie1: pcie@1c08000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */