From patchwork Thu Jul 25 01:42:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814445 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFCFA8480; Thu, 25 Jul 2024 01:43:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871795; cv=none; b=t0zJCSLXhxzFoAMJAlMFQrD871pIs/qm/+0rtkrD9Dt7/hnP3KSJ2bCSRPLLDHMCVRoHrtE1DvpPHKXMoCqiDPuYdZvGqyTcLzUUQjc6l0iXd1jhVr5R9IZwwcA/u4CaXuoP93HAyTm47PgjLy8wFZdml6pfeRRfOFmKaQqChQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871795; c=relaxed/simple; bh=5LcLgw7tpjDDLHX6hP4In6SOOPwrOgqloDQ0UOQXJ+w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hb8so8i7ONZvdPclFtzmbgH8DoCyXP4PSztmSmOW0BeMwNxq1vxrjJJxslOm8tc5McIbn/gt7A3LCmVk2/RbNMSOk71FlwJOiXuM/6ApKVwRtfVXowX/DFrJRo1FKzIuX9buoAlDP6/5GqUJXUijbJjRjJFLESF7jneiXbAtD9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=LQhh0VcE; arc=none smtp.client-ip=198.252.153.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="LQhh0VcE" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx1.riseup.net (Postfix) with ESMTPS id 4WTtv44nLLzDq89; Thu, 25 Jul 2024 01:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871793; bh=5LcLgw7tpjDDLHX6hP4In6SOOPwrOgqloDQ0UOQXJ+w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LQhh0VcEQSWEoazu7zyqlvtv9B3ceJfUg7u2hpblDKpsedUiBptbhyCZAZBUprZV+ mm64c3wOX0oNHkyHgfx1KyVBFpIMPS+M8AIQ1KaqEsMPKYclGUgZyaDh1jg6G6VqvL zgjgPYiCCkbew7waLF80g/F/iswi9/n7nwkQmlBk= X-Riseup-User-ID: 3D213ADC9C650FD7D9A045BE216F0204E78E125B85D784CA931FBEB526D74BA9 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtv16JB6zJrWZ; Thu, 25 Jul 2024 01:43:09 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:10 +0700 Subject: [PATCH v2 01/11] arm64: dts: qcom: sm6115-pro1x: Add Hall Switch and Camera Button Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-1-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh The Pro1X has a flip keyboard and a single-state camera button. Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 34 +++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 4a30024aa48f..3eecdc76bcac 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2023, Dang Huynh + * Copyright (c) 2023 - 2024, Dang Huynh */ /dts-v1/; @@ -35,9 +35,25 @@ framebuffer0: framebuffer@5c000000 { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&vol_up_n>; + pinctrl-0 = <&hall_sensor_n>, <&key_camera_n>, <&vol_up_n>; pinctrl-names = "default"; + hall-switch { + label = "Hall Switch"; + linux,input-type = ; + linux,code = ; + gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + debounce-interval = <90>; + wakeup-source; + }; + + key-camera { + label = "Camera Button"; + linux,code = ; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + key-volume-up { label = "Volume Up"; linux,code = ; @@ -212,6 +228,20 @@ &sleep_clk { &tlmm { gpio-reserved-ranges = <0 4>, <14 4>; + + hall_sensor_n: hall-sensor-n { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + key_camera_n: key-camera-n { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &ufs_mem_hc { From patchwork Thu Jul 25 01:42:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814631 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FD79134DE; Thu, 25 Jul 2024 01:43:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.129 ARC-Seal: i=1; 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Thu, 25 Jul 2024 01:43:12 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:11 +0700 Subject: [PATCH v2 02/11] arm64: dts: qcom: sm6115-pro1x: Add PCA9534 IO Expander Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-2-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh F(x)tec Pro1X comes with PCA9534 IO Expander, it is used for enabling touch screen VDD/VDDIO and keyboard's caps lock LED. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 3eecdc76bcac..993e7cfffae2 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -70,6 +70,23 @@ &dispcc { status = "disabled"; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + pca9534: gpio@21 { + compatible = "nxp,pca9534"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &pm6125_gpios { vol_up_n: vol-up-n-state { pins = "gpio5"; @@ -89,6 +106,10 @@ &pon_resin { status = "okay"; }; +&qupv3_id_0 { + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm6125-regulators"; From patchwork Thu Jul 25 01:42:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814444 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29BE518633; Thu, 25 Jul 2024 01:43:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.6 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871800; cv=none; b=t0IKsUZouaBx1MTgkUVqwp5SQwnZE8OCqKiGUK7yC7Kqrei2i3xLI6c2Jlt8R683/P9iVD8D5oFEBVs7tt+jmFqQa69nz5wjqPJZT4HS03Krvr5ppyY3pgUyEUPZt7ORUAKCcaYS9G9sHvW/bQxfVxMR8LH0uaMQylIsIJethPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871800; c=relaxed/simple; bh=6lCJaPJ40pomLk/cYW5r7d9xZfOrojS5vHQnJusUVQo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NykSOuft32JiaOLWWqskslUmPqZci/hGkeVF6EYtTii6wE7dXOs+oqnwKUZED4wmURPvXf4mfSoRnvf6Vicd46B92jqR8W9PEV8F+xQuKdACWQmofubJRDQMOOI5u0d6e326zBa3WP20D/GEGl/AVOf1+hP4Pit9lE4YMfJQwTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=JBfugMC6; arc=none smtp.client-ip=198.252.153.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="JBfugMC6" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx0.riseup.net (Postfix) with ESMTPS id 4WTtvB46l2z9t9m; Thu, 25 Jul 2024 01:43:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871798; bh=6lCJaPJ40pomLk/cYW5r7d9xZfOrojS5vHQnJusUVQo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JBfugMC6AE07fWqda1QSTjmINBTc9/L00XHnaG45o2zwwtypS2A5yWU/jZfSSWgw5 TYg1x3STMk47RpwiNuiQYw/jRWdFwEl0qEg2h6bGBk/kCd4qGH+CesJiZzpe+uV57k 0AnN4n+8fh3Ie+OsPyMyiw9J1nE+y5CVhRp3uALU= X-Riseup-User-ID: 14AF3757B28CCC9951E09770AF72B1EF77C32B91F2A84FCF600013BD49F64F47 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtv75mxZzJrWZ; Thu, 25 Jul 2024 01:43:15 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:12 +0700 Subject: [PATCH v2 03/11] arm64: dts: qcom: sm6115-pro1x: Add Goodix Touchscreen Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-3-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh The Fxtec Pro1X touchscreen uses Goodix GT9286 chip. Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 993e7cfffae2..3be70beb9562 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -63,6 +63,20 @@ key-volume-up { wakeup-source; }; }; + + ts_vdd_supply: ts-vdd-supply { + compatible = "regulator-fixed"; + regulator-name = "ts_vdd_supply"; + gpio = <&pca9534 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + ts_vddio_supply: ts-vddio-supply { + compatible = "regulator-fixed"; + regulator-name = "ts_vddio_supply"; + gpio = <&pca9534 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &dispcc { @@ -87,6 +101,27 @@ pca9534: gpio@21 { }; }; +&i2c2 { + status = "okay"; + /* Clock frequency was not specified downstream, let's park it to 100 KHz */ + clock-frequency = <100000>; + + touchscreen@14 { + compatible = "goodix,gt9286"; + reg = <0x14>; + + interrupts-extended = <&tlmm 80 IRQ_TYPE_LEVEL_LOW>; + + irq-gpios = <&tlmm 80 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&ts_vdd_supply>; + VDDIO-supply = <&ts_vddio_supply>; + + pinctrl-0 = <&ts_int_n>, <&ts_rst_n>; + pinctrl-names = "default"; + }; +}; + &pm6125_gpios { vol_up_n: vol-up-n-state { pins = "gpio5"; @@ -263,6 +298,20 @@ key_camera_n: key-camera-n { drive-strength = <2>; bias-pull-up; }; + + ts_int_n: ts-int-n { + pins = "gpio80"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_rst_n: ts-rst-n { + pins = "gpio71"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; }; &ufs_mem_hc { From patchwork Thu Jul 25 01:42:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814442 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C452B9C3; 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Thu, 25 Jul 2024 01:43:18 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:13 +0700 Subject: [PATCH v2 04/11] arm64: dts: qcom: sm6115-pro1x: Add Caps Lock LED Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-4-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh The Pro1X has a caps lock LED on the keyboard. Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 3be70beb9562..7c3a7bb8df8f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -8,6 +8,7 @@ #include "sm6115.dtsi" #include "pm6125.dtsi" #include +#include / { model = "F(x)tec Pro1X (QX1050)"; @@ -64,6 +65,19 @@ key-volume-up { }; }; + gpio-leds { + compatible = "gpio-leds"; + + capslock-led { + label = "green:capslock"; + function = LED_FUNCTION_CAPSLOCK; + color = ; + gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "kbd-capslock"; + default-state = "off"; + }; + }; + ts_vdd_supply: ts-vdd-supply { compatible = "regulator-fixed"; regulator-name = "ts_vdd_supply"; From patchwork Thu Jul 25 01:42:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814630 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 646061CF9A; Thu, 25 Jul 2024 01:43:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871806; cv=none; b=i5ByF7aRsn/NJISa7eXJ54nM8UEI+1XuJWBTfQ4qUjCIeZHsFOHKRlid/VXCpKWsCelCiuU62abcWo6cHnmZnBPyRrublJHT1dQRV2GoJN3X/1sVhAjApMdF19Padw8+J+KLZISth/TrU7KqRYx+s2Z6JwflHICMVReJuVPrqnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871806; c=relaxed/simple; bh=PccZUTUe6JRfO9ocLzaxjzP7vmL8w4z7Skt6kmQdqXQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QUE77roTsgIVZHIauezqdFKIr9/fkK8YEuegF2HMs6CFcQHmyck4ovo3bW194aUkiNla/mOK82aMuZcgbivKI5R3efZlBVqQqZkBmkJchoxnHL4DEDrHNDvofK3GMdXlsVJZuohFx4fuh7ZHlTQzAyoRgKV+WRAkfW+gyxurqJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=V7jXnT8e; arc=none smtp.client-ip=198.252.153.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="V7jXnT8e" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx1.riseup.net (Postfix) with ESMTPS id 4WTtvJ3xZ6zDq89; Thu, 25 Jul 2024 01:43:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871804; bh=PccZUTUe6JRfO9ocLzaxjzP7vmL8w4z7Skt6kmQdqXQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=V7jXnT8e4+F7L1f7nOMHhxhDAQ6fTpTWWZ3wk+Sdf0YBHzjj33tl/ol5dmfscwRir B5WunAFn9Imne1uBiV+8R1UbjzYHlZTUznY5tcjy18VmTNc3iiSzrl1EwXDjhUK1fL pxzyr+FZIo8YaZetYawUrvrhvezIxX3ptLdIwjM0= X-Riseup-User-ID: BA3AA2819FE32626E6C46F28E41A02872E12059AE7C2C178AF29F63269CA7707 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtvF5HkXzJrWZ; Thu, 25 Jul 2024 01:43:21 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:14 +0700 Subject: [PATCH v2 05/11] arm64: dts: qcom: sm6115-pro1x: Enable SD card slot Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-5-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh Fxtec Pro1X has two card slots and allow either 2xSIM cards or 1xSIM, 1xSD Card configuration. Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 7c3a7bb8df8f..e1e66fe54295 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -191,6 +191,7 @@ pm6125_l4a: l4 { pm6125_l5a: l5 { regulator-min-microvolt = <1648000>; regulator-max-microvolt = <3056000>; + regulator-allow-set-load; }; pm6125_l6a: l6 { @@ -292,6 +293,37 @@ pm6125_l24a: l24 { }; }; +&sdc2_state_off { + cd-pins { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&sdc2_state_on { + cd-pins { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&pm6125_l22a>; + vqmmc-supply = <&pm6125_l5a>; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; From patchwork Thu Jul 25 01:42:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814443 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12DE91D530; Thu, 25 Jul 2024 01:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871809; cv=none; b=IncZbzXbUXTZdpqcW+PpyzrCYONS4bfODkTcEINxVsAKoq84eCjyUHqelT0m0m291KLE8Ycmq6HAoaJuplkBlAbbBLj6npvJVb7YHAasWsqO+R4oDIldnZ4fL1xu/XRyJwY3PVllO12RqG4VQYdo2NggVmhHzgPvZMVEpOiHRn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871809; c=relaxed/simple; bh=UTXwbecjWZcA/crNsy6yoLPgwzEQmmBGb1D8AMOiggU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p8XY6xFccfR+yumulfJyD8aPgHhyY5O/NLJxF0/MLQkulDDBtytDh9YKDvPfVuX7N+CmQN0L3psDAKGbwZC79mHBLELcx7Gx0p76WkFl5fZt0fg32EVz2LwX6h2BCF4L9BUd9D1vwsXo6zRHx1u18sth7aDn5FS05gu2SFSJ24Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=m1ou21kh; arc=none smtp.client-ip=198.252.153.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="m1ou21kh" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx1.riseup.net (Postfix) with ESMTPS id 4WTtvM3CnHzDq89; Thu, 25 Jul 2024 01:43:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871807; bh=UTXwbecjWZcA/crNsy6yoLPgwzEQmmBGb1D8AMOiggU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=m1ou21khwtKccyymhTPcRqPNm0L46f5BnqzZ9nxXH0eLapJo0SMs+8WZ1LnzN6z8i f7zztJKE7N/PTsMEDcHs3EqNo5Ikim7H0OrDXq+V48SWFAMbfi2a7B7RMytp/aO3Yh hhN2hymWH0oJ14Z97enTcKhbE3Ip3y2nhttEs3i4= X-Riseup-User-ID: FEE392A72BEBE4B5A8EB0635CA82BB0AEC84CA703F9C0B82E4246D96C1AE37BF Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtvJ54CHzJrmm; Thu, 25 Jul 2024 01:43:24 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:15 +0700 Subject: [PATCH v2 06/11] arm64: dts: qcom: sm6115-pro1x: Enable MDSS and GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-6-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh Fxtec Pro1x uses the same display (BOE BF060Y8M-AJ0) as Pro1. Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 60 +++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index e1e66fe54295..69ef404d9de6 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -93,13 +93,16 @@ ts_vddio_supply: ts-vddio-supply { }; }; -&dispcc { - /* HACK: disable until a panel driver is ready to retain simplefb */ - status = "disabled"; +&gpi_dma0 { + status = "okay"; }; -&gpi_dma0 { +&gpu { status = "okay"; + + zap-shader { + firmware-name = "qcom/sm6115/Fxtec/QX1050/a610_zap.mbn"; + }; }; &i2c1 { @@ -136,6 +139,42 @@ touchscreen@14 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm6125_l18a>; + status = "okay"; + + panel: panel@0 { + compatible = "boe,bf060y8m-aj0"; + reg = <0>; + + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + + vddio-supply = <&pm6125_l9a>; + + pinctrl-0 = <&mdss_dsi_n &panel_en_n>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &pm6125_gpios { vol_up_n: vol-up-n-state { pins = "gpio5"; @@ -345,6 +384,19 @@ key_camera_n: key-camera-n { bias-pull-up; }; + mdss_dsi_n: mdss-dsi-n { + pins = "gpio82"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_en_n: panel-en-n { + pins = "gpio65"; + function = "gpio"; + bias-disable; + }; + ts_int_n: ts-int-n { pins = "gpio80"; function = "gpio"; From patchwork Thu Jul 25 01:42:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814629 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4CB022638; 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Thu, 25 Jul 2024 01:43:27 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:16 +0700 Subject: [PATCH v2 07/11] arm64: dts: qcom: sm6115-pro1x: Hook up USB3 SS Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-7-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh The F(x)tec Pro1X supports USB 3.0 through it's USB-C port. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 69ef404d9de6..5dd70dc87328 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -433,7 +433,6 @@ &usb { &usb_dwc3 { /delete-property/ usb-role-switch; - maximum-speed = "high-speed"; dr_mode = "peripheral"; }; @@ -444,6 +443,12 @@ &usb_hsphy { status = "okay"; }; +&usb_qmpphy { + vdda-phy-supply = <&pm6125_l4a>; + vdda-pll-supply = <&pm6125_l12a>; + status = "okay"; +}; + &xo_board { clock-frequency = <19200000>; }; From patchwork Thu Jul 25 01:42:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814628 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3CE82B9CE; Thu, 25 Jul 2024 01:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.6 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871815; cv=none; b=jrabKnh4jb2rptHtQPwLAZOfzUhRyNllVsGInP2+7JbAOPj9mHpCAY5dEzeAzJVnRAmPRiaaaj4szU0/7ehWduVgJuAvuTxJo8jo+lSzpJk9DXe9ip1IyJuI/Ln54ofPEVzrKhZCnm9qZDb7ybxHSDYez4KHI3ylrvpyRyLi7MA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871815; c=relaxed/simple; bh=blYdFhbMB8e9xhr5CuWD6k3VpgztU4sMQ8uHYVCPIaM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Eyhp9/M/D3Jz/aowgqZwZ6Sgoo3GqFJ+PocDpp8e4f3yI+LKRZkpoYvgGbPeRuYybqpD1op8dLG+no/+rx0/KBNYb/IPza/9KVEhlW+8PjuTCMXDPwODRYHmdCh9ppnOLitkeZMMTeryRDqqE66R99atPPWJABgATq8/UXgt/wc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=RQMiV3y1; arc=none smtp.client-ip=198.252.153.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="RQMiV3y1" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx0.riseup.net (Postfix) with ESMTPS id 4WTtvT2XwPz9t9m; Thu, 25 Jul 2024 01:43:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871813; bh=blYdFhbMB8e9xhr5CuWD6k3VpgztU4sMQ8uHYVCPIaM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RQMiV3y1RUc09vKL8jCaZFDN5DjNnQ2C0ig870K509FUe1P3SPbZLuW5u4G28fK49 T5cfNyPsgfNl0fCcUyocC72fegmEJqQkzSTeNGrnYmSp5ViFjfOH+1vCoGsE+TYaUm V/AAHXV56IPbMyFI5YyA4mtkyS6ND7tYHo0iTUa0= X-Riseup-User-ID: 7FB22837E71FD33E0101349E1E8A2100F9E204DF5704093C7586343082BFDF83 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtvQ4SgfzJrWZ; Thu, 25 Jul 2024 01:43:30 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:17 +0700 Subject: [PATCH v2 08/11] arm64: dts: qcom: sm6115-pro1x: Add PMI632 Type-C property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-8-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh The USB-C port is used for powering external devices and transfer data from/to them. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 51 +++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 5dd70dc87328..17f40125cb29 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -7,8 +7,10 @@ #include "sm6115.dtsi" #include "pm6125.dtsi" +#include "pmi632.dtsi" #include #include +#include / { model = "F(x)tec Pro1X (QX1050)"; @@ -185,6 +187,46 @@ vol_up_n: vol-up-n-state { }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pmi632_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1000000>; + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; @@ -431,9 +473,8 @@ &usb { status = "okay"; }; -&usb_dwc3 { - /delete-property/ usb-role-switch; - dr_mode = "peripheral"; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; }; &usb_hsphy { @@ -449,6 +490,10 @@ &usb_qmpphy { status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&pmi632_ss_in>; +}; + &xo_board { clock-frequency = <19200000>; }; From patchwork Thu Jul 25 01:42:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814441 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB0F53BBD7; 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Thu, 25 Jul 2024 01:43:33 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:18 +0700 Subject: [PATCH v2 09/11] arm64: dts: qcom: sm6115-pro1x: Enable RGB LED Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-9-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh This device has an RGB LED. It is used for notifications. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 17f40125cb29..7ea9ecf37ae9 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -187,6 +187,33 @@ vol_up_n: vol-up-n-state { }; }; +&pmi632_lpg { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &pmi632_typec { status = "okay"; From patchwork Thu Jul 25 01:42:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814627 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B118849650; Thu, 25 Jul 2024 01:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871821; cv=none; b=QV3e6cH99PjPDabQDl2g+BlueMR6T8Vk8LlZZFV+Vwm2tJEk014GjM3KwoHYnjU4S8uijF9NY5H7BqhMYr+v7u1lZgk20a/9Ls18hW/8vneSkfr7KYvI3lRTE9YzkXbsUc6UJGAnnMlSb5dK4hKzDD8B2ph1fp+M07mp4QFPNnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871821; c=relaxed/simple; bh=lteP0SIsrAxo0YgAYKR5hVbza7krYALkdzfiD401IAk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OyYsE7X7eMh6UdIcKOAv9wqn33k9D3A8sN2zNlcvLEyyFJV7f9c0PkjA0NyhFkI+5kwgNCyikONFtdWtZORPH2/0runmD/Cqw/EB0OxwTRUkIVPIYXXE2lFc8ss9ovgpgN9v53urRL/tIw08bhQg7MR9DhdIXT4iW7ZzvgkDLzI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=ZKRD3pB3; arc=none smtp.client-ip=198.252.153.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="ZKRD3pB3" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx1.riseup.net (Postfix) with ESMTPS id 4WTtvb22LgzDqWn; Thu, 25 Jul 2024 01:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871819; bh=lteP0SIsrAxo0YgAYKR5hVbza7krYALkdzfiD401IAk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZKRD3pB3EaLx3wi52hWes+sqoG9AK5kjY9UxiRK5MtQ7mBeIZ5wHuqQ0BsR4dWOKx zEiCzQKM/tY8+KCrcByDc8hJ7mAHcm00wL7oh9xZTaFZ+kHJHNSt49xcGSl5HH4S/B tSe5b+BCLMW38FjxZuV8d8SzAMpdggRqhSMEbDGw= X-Riseup-User-ID: FD1B2DAFFE46AFC601800322658448DDCBA7F63B917BDCC0474E0A378875FF11 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtvX3rPbzJrWZ; Thu, 25 Jul 2024 01:43:36 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:19 +0700 Subject: [PATCH v2 10/11] arm64: dts: qcom: sm6115-pro1x: Enable remoteprocs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-10-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh Enable [A,C]DSP and MPSS remote processor on this device. Reviewed-by: Konrad Dybcio Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 7ea9ecf37ae9..3f6676edc9a7 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -267,6 +267,21 @@ &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sm6115/Fxtec/QX1050/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm6115/Fxtec/QX1050/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm6115/Fxtec/QX1050/modem.mbn"; + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm6125-regulators"; From patchwork Thu Jul 25 01:42:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dang Huynh X-Patchwork-Id: 814440 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E41DF63A9; Thu, 25 Jul 2024 01:43:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.252.153.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871824; cv=none; b=oElfWBUiiOldcIOpTrEaYljyNrsa+6eMdZlDDLqAUTNnEXeJz0nmf1dsdTQE5KHf3eKI/GXSgyc1/GwLbHn4ChMgz+1QePL8gpKsnp1F5p4h37FMtBk030JysMK4GVxAdmohbmK07MLy3VpswSwuWviH42DOBGLkfB74Gv1+4Mk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721871824; c=relaxed/simple; bh=W27i8GsddWkkGbO43nNSrNo7kUCmHrqjkxKShFt8uBE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DPkk2ngVE41UFy0E4VT4YYLs7x1hcOrtLwErzX8mRgjSxSvHkOB06xStl15ITxvnaX1ADXjUvVe/gGi8lFu63J0emDnS1sOEoCPSWXXIVYfzHN+5s+mrmp34o7nPQJ7yqe+a/35e4L9yCPhGMqNY+lRPazItiZ1QLEu3QCqkVdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net; spf=pass smtp.mailfrom=riseup.net; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b=srn4n+kJ; arc=none smtp.client-ip=198.252.153.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riseup.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riseup.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=riseup.net header.i=@riseup.net header.b="srn4n+kJ" Received: from fews01-sea.riseup.net (fews01-sea-pn.riseup.net [10.0.1.109]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx1.riseup.net (Postfix) with ESMTPS id 4WTtvf1skBzDqWn; Thu, 25 Jul 2024 01:43:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1721871822; bh=W27i8GsddWkkGbO43nNSrNo7kUCmHrqjkxKShFt8uBE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=srn4n+kJrmAxuGdPRwpNbOq2jilBzgpNuAvZJZnYe7CiyjSxKuXgj0P0qZCapmGjB RGo/XBnpo5X2H/muUWMTWptuOAOutG5r1M5Bi9rZCHMqxahnWvn1E9RDC4PMHXXk0k xdVmimIbC2BfY6lD/vLj8bN47AVtiosREPKW6g9w= X-Riseup-User-ID: 3C13B24D9ADA5A948DEBA86D6218C0230D81CB46BC5330AC4AE95BA046F5E57E Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews01-sea.riseup.net (Postfix) with ESMTPSA id 4WTtvb3YpXzJrRJ; Thu, 25 Jul 2024 01:43:39 +0000 (UTC) From: Dang Huynh Date: Thu, 25 Jul 2024 08:42:20 +0700 Subject: [PATCH v2 11/11] arm64: dts: qcom: sm6115-pro1x: Enable ATH10K WLAN Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240725-qx1050-feature-expansion-v2-11-5fac4bbd946f@riseup.net> References: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> In-Reply-To: <20240725-qx1050-feature-expansion-v2-0-5fac4bbd946f@riseup.net> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dang Huynh Enable onboard Wi-Fi on the F(x)tec Pro1X. For reference, HW/SW identifies as: qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 qmi fw_version 0x324103d6 fw_build_timestamp 2021-12-02 08:20 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.2.4-00982-QCAHLSWMTPLZ-1 Signed-off-by: Dang Huynh Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 3f6676edc9a7..2ef2733bff48 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -536,6 +536,17 @@ &usb_qmpphy_out { remote-endpoint = <&pmi632_ss_in>; }; +&wifi { + vdd-0.8-cx-mx-supply = <&pm6125_l8a>; + vdd-1.8-xo-supply = <&pm6125_l16a>; + vdd-1.3-rfa-supply = <&pm6125_l17a>; + vdd-3.3-ch0-supply = <&pm6125_l23a>; + + qcom,ath10k-calibration-variant = "Fxtec_QX1050"; + + status = "okay"; +}; + &xo_board { clock-frequency = <19200000>; };