From patchwork Mon Nov 4 18:12:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178466 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389590ocf; Mon, 4 Nov 2019 10:13:35 -0800 (PST) X-Google-Smtp-Source: APXvYqzOOJbrnRYKj6I8jKMLFVdTdoSXlO2IPbQR/0TiFtgjrNlb8aKHFAPGTkcgnlsKXQpFntqh X-Received: by 2002:a17:906:351b:: with SMTP id r27mr3792630eja.120.1572891215170; Mon, 04 Nov 2019 10:13:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891215; cv=none; d=google.com; s=arc-20160816; b=stARUkJPPw419w5krnPaBr+in5uQTebWxGmhm9TSmZ8j/NE7CxJ29XEmbBE72Oz9/W roqA/rZb3uwvW9nTQu5hKCaO7Eqqyt6jfSEJ3L1aa83yxIfL3sX/j+OgKln6lz3CLYWz 8ynqHu1p+OhZ3V1a8U92AFqyAe/yapowc1lsH8K6cvz4ifa8LAgWbqeOP3oNs4oEWMFi 7vzB4BqGnCHNX6iZ5Z/43qD63ERe31DPKvd5OYlr/AbBJ/WS8TzIvfmGreNvoez9pc4c O1yteNaSZTgKCpeeRo76AZdAHHHE/YEpdxnPyO12fP3FbwWo8UZAza2s9r7hM/38xS/f GJIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=iAETIV/C9sg4KLCBqiaJG6OHWMKAU50pvVJM5wi76QU=; b=xOECSjiaXGEUWw2Y//lbwvUIbpK4DrPqYU5SuDfhERFpFtXWYzVPspoBOqpeS5FGtW iceMEwyiz+uKh4t37qcIZmqZ9NFT1kFQTtsV7WGs5ZIbnIyXNFHW87TxKkaQ+236Afg5 WRDZTMVSq3fjFl8XGiYOlOm8wdPmmFVCiORTBJBny5obJExchLPL+spT5Ndq1aF5u9Mo ddwKYxMs0TEnd+BTlyR3rZ6ogb5wcgrymK4V49ONaxb8i8shbV+ybDK7eUngrp5ck3CO J1oxJ77C59pCCU9X/0JJT6bQEX+F9rsDGFUfRicZY4lb8KUQeWV530xGS0pH86tQTPEI Nyhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qOUjgkAU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v20si8362293edc.69.2019.11.04.10.13.34; Mon, 04 Nov 2019 10:13:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qOUjgkAU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729568AbfKDSND (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:03 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:43751 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727998AbfKDSMz (ORCPT ); Mon, 4 Nov 2019 13:12:55 -0500 Received: by mail-pf1-f193.google.com with SMTP id 3so12827837pfb.10 for ; Mon, 04 Nov 2019 10:12:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iAETIV/C9sg4KLCBqiaJG6OHWMKAU50pvVJM5wi76QU=; b=qOUjgkAUemZU5+ewgf9hgxF7ZQbvesSw5+oh7f/XKYjUePFaZHo1fhvm1J+JSR49LD LjSj49WIqxRvnBX4yzYee3wnmBQJsk1RzpOot2Mfnx98TtLJokOAAUW1kDSi7aFtQxs9 56R6rm9HShw5FqQnSAiHeWZEp9eTr7HlHbzUTres8qvqgb1EObdy2vcQnrucn3Vxdf8h ZiGpdhdw+IMdCmrsYtSEfC+/4T+zF9izHJ+WhRRCpQNWbgdLpF8hIY827LEah+H/8qcJ +K/jt6kgZ9HFAJS3HhC+5lGKOoVCIjBgsmQ0PuC1u6RsEVcUs2q6gtIv3m2X8Fw8IBci ZZZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iAETIV/C9sg4KLCBqiaJG6OHWMKAU50pvVJM5wi76QU=; b=HRykmxfnwi06XFB7JLVKwh2oR1EtTRT7KuHMssXZx3tCNMlRR75VyRnNZJDyxP7r2/ aN7Q3Sbg4MiOtlluT4SJlVMrcPyMRlVfYq7f6QEpRV83WdF9CciV9nMQwo9OaZobPF97 ebkOBTZs577iryENztOtNwGVzntd5J3goeOcDctc2Bizj+CgrwfLLv98d5AnXOzOKzhz tHQKYDd2ZUSWbLNz6pSeuy32i9RLWMcoe5rIsHqwpgWBSYo75/4mukldTJ8b7+zJEf04 OFX4LQ+Jjrfl4hw4431Wd4VKRX0vbyKiVVS59KQTLlkG119yZm9KQFUNWkoJb5ISEZNH X0LQ== X-Gm-Message-State: APjAAAWjCtUV15V8i2p8tRU3jnnrE6MoC2vq7gxd06eFC3JtbtuqfmOX huFUeGcq9AHZQFY8Eue4pDi+X/mefig= X-Received: by 2002:a63:f849:: with SMTP id v9mr9963539pgj.99.1572891174393; Mon, 04 Nov 2019 10:12:54 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:12:53 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] coresight: etm4x: Save/restore state across CPU low power states Date: Mon, 4 Nov 2019 11:12:38 -0700 Message-Id: <20191104181251.26732-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Murray Some hardware will ignore bit TRCPDCR.PU which is used to signal to hardware that power should not be removed from the trace unit. Let's mitigate against this by conditionally saving and restoring the trace unit state when the CPU enters low power states. This patchset introduces a firmware property named 'arm,coresight-loses-context-with-cpu' - when this is present the hardware state will be conditionally saved and restored. A module parameter 'pm_save_enable' is also introduced which can be configured to override the firmware property. This can be set to never allow save/restore or to conditionally allow it (only for self-hosted). The default value is determined by firmware. We avoid saving the hardware state when self-hosted coresight isn't in use to reduce PM latency - we can't determine this by reading the claim tags (TRCCLAIMCLR) as these are 'trace' registers which need power and clocking, something we can't easily provide in the PM context. Therefore we rely on the existing drvdata->mode internal state that is set when self-hosted coresight is used (and powered). Signed-off-by: Andrew Murray Reviewed-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 318 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 64 ++++ drivers/hwtracing/coresight/coresight.c | 6 + include/linux/coresight.h | 6 + 4 files changed, 394 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index a128b5063f46..4cecabdd051b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -37,6 +39,15 @@ static int boot_enable; module_param(boot_enable, int, 0444); MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); +#define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */ +#define PARAM_PM_SAVE_NEVER 1 /* never save any state */ +#define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ + +static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; +module_param(pm_save_enable, int, 0444); +MODULE_PARM_DESC(pm_save_enable, + "Save/restore state on power down: 1 = never, 2 = self-hosted"); + /* The number of ETMv4 currently registered */ static int etm4_count; static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; @@ -54,6 +65,14 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_os_lock(struct etmv4_drvdata *drvdata) +{ + /* Writing 0x1 to TRCOSLAR locks the trace registers */ + writel_relaxed(0x1, drvdata->base + TRCOSLAR); + drvdata->os_unlock = false; + isb(); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -1085,6 +1104,288 @@ static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) drvdata->trcid = coresight_get_trace_id(drvdata->cpu); } +#ifdef CONFIG_CPU_PM +static int etm4_cpu_save(struct etmv4_drvdata *drvdata) +{ + int i, ret = 0; + struct etmv4_save_state *state; + struct device *etm_dev = &drvdata->csdev->dev; + + /* + * As recommended by 3.4.1 ("The procedure when powering down the PE") + * of ARM IHI 0064D + */ + dsb(sy); + isb(); + + CS_UNLOCK(drvdata->base); + + /* Lock the OS lock to disable trace and external debugger access */ + etm4_os_lock(drvdata); + + /* wait for TRCSTATR.PMSTABLE to go up */ + if (coresight_timeout(drvdata->base, TRCSTATR, + TRCSTATR_PMSTABLE_BIT, 1)) { + dev_err(etm_dev, + "timeout while waiting for PM Stable Status\n"); + etm4_os_unlock(drvdata); + ret = -EBUSY; + goto out; + } + + state = drvdata->save_state; + + state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR); + state->trcprocselr = readl(drvdata->base + TRCPROCSELR); + state->trcconfigr = readl(drvdata->base + TRCCONFIGR); + state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR); + state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R); + state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R); + state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR); + state->trctsctlr = readl(drvdata->base + TRCTSCTLR); + state->trcsyncpr = readl(drvdata->base + TRCSYNCPR); + state->trcccctlr = readl(drvdata->base + TRCCCCTLR); + state->trcbbctlr = readl(drvdata->base + TRCBBCTLR); + state->trctraceidr = readl(drvdata->base + TRCTRACEIDR); + state->trcqctlr = readl(drvdata->base + TRCQCTLR); + + state->trcvictlr = readl(drvdata->base + TRCVICTLR); + state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR); + state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR); + state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR); + state->trcvdctlr = readl(drvdata->base + TRCVDCTLR); + state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR); + state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR); + + for (i = 0; i < drvdata->nrseqstate; i++) + state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i)); + + state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR); + state->trcseqstr = readl(drvdata->base + TRCSEQSTR); + state->trcextinselr = readl(drvdata->base + TRCEXTINSELR); + + for (i = 0; i < drvdata->nr_cntr; i++) { + state->trccntrldvr[i] = readl(drvdata->base + TRCCNTRLDVRn(i)); + state->trccntctlr[i] = readl(drvdata->base + TRCCNTCTLRn(i)); + state->trccntvr[i] = readl(drvdata->base + TRCCNTVRn(i)); + } + + for (i = 0; i < drvdata->nr_resource * 2; i++) + state->trcrsctlr[i] = readl(drvdata->base + TRCRSCTLRn(i)); + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i)); + state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i)); + state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i)); + } + + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i)); + state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i)); + } + + /* + * Data trace stream is architecturally prohibited for A profile cores + * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per + * section 1.3.4 ("Possible functional configurations of an ETMv4 trace + * unit") of ARM IHI 0064D. + */ + + for (i = 0; i < drvdata->numcidc; i++) + state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i)); + + for (i = 0; i < drvdata->numvmidc; i++) + state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i)); + + state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0); + state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); + + state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0); + state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1); + + state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); + + state->trcpdcr = readl(drvdata->base + TRCPDCR); + + /* wait for TRCSTATR.IDLE to go up */ + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { + dev_err(etm_dev, + "timeout while waiting for Idle Trace Status\n"); + etm4_os_unlock(drvdata); + ret = -EBUSY; + goto out; + } + + drvdata->state_needs_restore = true; + + /* + * Power can be removed from the trace unit now. We do this to + * potentially save power on systems that respect the TRCPDCR_PU + * despite requesting software to save/restore state. + */ + writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), + drvdata->base + TRCPDCR); + +out: + CS_LOCK(drvdata->base); + return ret; +} + +static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) +{ + int i; + struct etmv4_save_state *state = drvdata->save_state; + + CS_UNLOCK(drvdata->base); + + writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); + + writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR); + writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR); + writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR); + writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR); + writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R); + writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R); + writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR); + writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR); + writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR); + writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR); + writel_relaxed(state->trcbbctlr, drvdata->base + TRCBBCTLR); + writel_relaxed(state->trctraceidr, drvdata->base + TRCTRACEIDR); + writel_relaxed(state->trcqctlr, drvdata->base + TRCQCTLR); + + writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR); + writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR); + writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR); + writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR); + writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR); + writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR); + writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR); + + for (i = 0; i < drvdata->nrseqstate; i++) + writel_relaxed(state->trcseqevr[i], + drvdata->base + TRCSEQEVRn(i)); + + writel_relaxed(state->trcseqrstevr, drvdata->base + TRCSEQRSTEVR); + writel_relaxed(state->trcseqstr, drvdata->base + TRCSEQSTR); + writel_relaxed(state->trcextinselr, drvdata->base + TRCEXTINSELR); + + for (i = 0; i < drvdata->nr_cntr; i++) { + writel_relaxed(state->trccntrldvr[i], + drvdata->base + TRCCNTRLDVRn(i)); + writel_relaxed(state->trccntctlr[i], + drvdata->base + TRCCNTCTLRn(i)); + writel_relaxed(state->trccntvr[i], + drvdata->base + TRCCNTVRn(i)); + } + + for (i = 0; i < drvdata->nr_resource * 2; i++) + writel_relaxed(state->trcrsctlr[i], + drvdata->base + TRCRSCTLRn(i)); + + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + writel_relaxed(state->trcssccr[i], + drvdata->base + TRCSSCCRn(i)); + writel_relaxed(state->trcsscsr[i], + drvdata->base + TRCSSCSRn(i)); + writel_relaxed(state->trcsspcicr[i], + drvdata->base + TRCSSPCICRn(i)); + } + + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + writel_relaxed(state->trcacvr[i], + drvdata->base + TRCACVRn(i)); + writel_relaxed(state->trcacatr[i], + drvdata->base + TRCACATRn(i)); + } + + for (i = 0; i < drvdata->numcidc; i++) + writel_relaxed(state->trccidcvr[i], + drvdata->base + TRCCIDCVRn(i)); + + for (i = 0; i < drvdata->numvmidc; i++) + writel_relaxed(state->trcvmidcvr[i], + drvdata->base + TRCVMIDCVRn(i)); + + writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0); + writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1); + + writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0); + writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1); + + writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); + + writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); + + drvdata->state_needs_restore = false; + + /* + * As recommended by section 4.3.7 ("Synchronization when using the + * memory-mapped interface") of ARM IHI 0064D + */ + dsb(sy); + isb(); + + /* Unlock the OS lock to re-enable trace and external debug access */ + etm4_os_unlock(drvdata); + CS_LOCK(drvdata->base); +} + +static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, + void *v) +{ + struct etmv4_drvdata *drvdata; + unsigned int cpu = smp_processor_id(); + + if (!etmdrvdata[cpu]) + return NOTIFY_OK; + + drvdata = etmdrvdata[cpu]; + + if (!drvdata->save_state) + return NOTIFY_OK; + + if (WARN_ON_ONCE(drvdata->cpu != cpu)) + return NOTIFY_BAD; + + switch (cmd) { + case CPU_PM_ENTER: + /* save the state if self-hosted coresight is in use */ + if (local_read(&drvdata->mode)) + if (etm4_cpu_save(drvdata)) + return NOTIFY_BAD; + break; + case CPU_PM_EXIT: + /* fallthrough */ + case CPU_PM_ENTER_FAILED: + if (drvdata->state_needs_restore) + etm4_cpu_restore(drvdata); + break; + default: + return NOTIFY_DONE; + } + + return NOTIFY_OK; +} + +static struct notifier_block etm4_cpu_pm_nb = { + .notifier_call = etm4_cpu_pm_notify, +}; + +static int etm4_cpu_pm_register(void) +{ + return cpu_pm_register_notifier(&etm4_cpu_pm_nb); +} + +static void etm4_cpu_pm_unregister(void) +{ + cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); +} +#else +static int etm4_cpu_pm_register(void) { return 0; } +static void etm4_cpu_pm_unregister(void) { } +#endif + static int etm4_probe(struct amba_device *adev, const struct amba_id *id) { int ret; @@ -1101,6 +1402,17 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) dev_set_drvdata(dev, drvdata); + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) + pm_save_enable = coresight_loses_context_with_cpu(dev) ? + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; + + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { + drvdata->save_state = devm_kmalloc(dev, + sizeof(struct etmv4_save_state), GFP_KERNEL); + if (!drvdata->save_state) + return -ENOMEM; + } + /* Validity for the resource is already checked by the AMBA core */ base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) @@ -1135,6 +1447,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (ret < 0) goto err_arch_supported; hp_online = ret; + + ret = etm4_cpu_pm_register(); + if (ret) + goto err_arch_supported; } cpus_read_unlock(); @@ -1185,6 +1501,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) err_arch_supported: if (--etm4_count == 0) { + etm4_cpu_pm_unregister(); + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); if (hp_online) cpuhp_remove_state_nocalls(hp_online); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4523f10ddd0f..546d790cb01b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -175,6 +175,7 @@ ETM_MODE_EXCL_USER) #define TRCSTATR_IDLE_BIT 0 +#define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 /* PowerDown Control Register bits */ @@ -281,6 +282,65 @@ struct etmv4_config { u32 ext_inp; }; +/** + * struct etm4_save_state - state to be preserved when ETM is without power + */ +struct etmv4_save_state { + u32 trcprgctlr; + u32 trcprocselr; + u32 trcconfigr; + u32 trcauxctlr; + u32 trceventctl0r; + u32 trceventctl1r; + u32 trcstallctlr; + u32 trctsctlr; + u32 trcsyncpr; + u32 trcccctlr; + u32 trcbbctlr; + u32 trctraceidr; + u32 trcqctlr; + + u32 trcvictlr; + u32 trcviiectlr; + u32 trcvissctlr; + u32 trcvipcssctlr; + u32 trcvdctlr; + u32 trcvdsacctlr; + u32 trcvdarcctlr; + + u32 trcseqevr[ETM_MAX_SEQ_STATES]; + u32 trcseqrstevr; + u32 trcseqstr; + u32 trcextinselr; + u32 trccntrldvr[ETMv4_MAX_CNTR]; + u32 trccntctlr[ETMv4_MAX_CNTR]; + u32 trccntvr[ETMv4_MAX_CNTR]; + + u32 trcrsctlr[ETM_MAX_RES_SEL * 2]; + + u32 trcssccr[ETM_MAX_SS_CMP]; + u32 trcsscsr[ETM_MAX_SS_CMP]; + u32 trcsspcicr[ETM_MAX_SS_CMP]; + + u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; + u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; + u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; + u32 trcvmidcvr[ETM_MAX_VMID_CMP]; + u32 trccidcctlr0; + u32 trccidcctlr1; + u32 trcvmidcctlr0; + u32 trcvmidcctlr1; + + u32 trcclaimset; + + u32 cntr_val[ETMv4_MAX_CNTR]; + u32 seq_state; + u32 vinst_ctrl; + u32 ss_status[ETM_MAX_SS_CMP]; + + u32 trcpdcr; +}; + /** * struct etm4_drvdata - specifics associated to an ETM component * @base: Memory mapped base address for this component. @@ -336,6 +396,8 @@ struct etmv4_config { * @atbtrig: If the implementation can support ATB triggers * @lpoverride: If the implementation can support low-power state over. * @config: structure holding configuration parameters. + * @save_state: State to be preserved across power loss + * @state_needs_restore: True when there is context to restore after PM exit */ struct etmv4_drvdata { void __iomem *base; @@ -381,6 +443,8 @@ struct etmv4_drvdata { bool atbtrig; bool lpoverride; struct etmv4_config config; + struct etmv4_save_state *save_state; + bool state_needs_restore; }; /* Address comparator access types */ diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 6453c67a4d01..e6ca899fea4e 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -1308,6 +1308,12 @@ static inline int coresight_search_device_idx(struct coresight_dev_list *dict, return -ENOENT; } +bool coresight_loses_context_with_cpu(struct device *dev) +{ + return fwnode_property_present(dev_fwnode(dev), + "arm,coresight-loses-context-with-cpu"); +} + /* * coresight_alloc_device_name - Get an index for a given device in the * device index list specific to a driver. An index is allocated for a diff --git a/include/linux/coresight.h b/include/linux/coresight.h index a2b68823717b..44e552de419c 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -285,6 +285,8 @@ extern void coresight_disclaim_device(void __iomem *base); extern void coresight_disclaim_device_unlocked(void __iomem *base); extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev); + +extern bool coresight_loses_context_with_cpu(struct device *dev); #else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } @@ -307,6 +309,10 @@ static inline int coresight_claim_device(void __iomem *base) static inline void coresight_disclaim_device(void __iomem *base) {} static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} +static inline bool coresight_loses_context_with_cpu(struct device *dev) +{ + return false; +} #endif extern int coresight_get_cpu(struct device *dev); From patchwork Mon Nov 4 18:12:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178456 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4388962ocf; Mon, 4 Nov 2019 10:13:03 -0800 (PST) X-Google-Smtp-Source: APXvYqxOkp2gYJX1AImHDnRghtLZbuWC9rA+QaHopTkuV7MGZKXQZBGqMCrsTvx7GKQ0wngVHVaQ X-Received: by 2002:a50:a697:: with SMTP id e23mr16855725edc.264.1572891183335; Mon, 04 Nov 2019 10:13:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891183; cv=none; d=google.com; s=arc-20160816; b=CaKbj9IEviBtCFqxdQc9HqP4KS56plv1pKiSUK+7Y07LiyzcrkbI30UW+Ua51SzpCv c51VnqYmfWjHa/F3KZeP8j4GINnBDmm3BrYBiywsHpWJ0MaEIa3/nU1iLON8d3o/221r FdbDlntw6ZZm8Ao2LixGJpGDmDJlCoH55VEzvOb6fZeJ8iYaUaJFv1h9faxOxA5jvHcD FhhXBgQ06KpnUfGTuzkw7U4hzCKxhojY2oSFRud80gX2nUywXHcmWli/K047Hv9PopBm 89AHUIw6Z+PUq5Wn23e/KwGydwYky0eJdoNsHgnH3M9f9ZdbemJmUs1UDrGb1DzGXnDI jKmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ciXUSjrJzeNJ7x1YqUH63bTMmxfwRBsuiu2kMzOf67g=; b=KzHMRB7HkwKedtCBGeL9rLTIKF/OCeT9DdPuLroUBSI6WSYJDVjhtZeQ1xxgo/ixaF SKkXfZOgYD48F8+hrUMTs56vKsM6O2W2+jyALcPH2BM6Kr4Goi7UiL6zq6fYO0F2+e72 gbyP+qwXlTydKnz1ph2vmtTlj6wI3dHkn7udt8bTlj7jiadYzQ1VcNlEAFZrG3XPenht bz2Dh5kFhTZquabqYd1AOnaIbUh2Tyqq8svG8hkQYGpU0br96aoYBTVG8t2WQKyHpEjF CwN2ZMLJTrdeE0OU4wFQ+9LCSlhQ5PVmwmEkKcJRmG+PviGg4wUH84a4IVbmOvhhAx5c DFcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H3BBaQmV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p23si7395797ejx.366.2019.11.04.10.13.03; Mon, 04 Nov 2019 10:13:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H3BBaQmV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729537AbfKDSM7 (ORCPT + 26 others); Mon, 4 Nov 2019 13:12:59 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:40063 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729513AbfKDSM4 (ORCPT ); Mon, 4 Nov 2019 13:12:56 -0500 Received: by mail-pf1-f194.google.com with SMTP id r4so12834639pfl.7 for ; Mon, 04 Nov 2019 10:12:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ciXUSjrJzeNJ7x1YqUH63bTMmxfwRBsuiu2kMzOf67g=; b=H3BBaQmVJVl+8T39kKh3UPdS/XpJ9Q2VTPAOpfckdFx1bb9wba7xd/QD+BgQM/9Ah6 9cC/e1iwKmsTGx3zd6x5oC19ft2PPIQuqXTJ93j/EISnxE+eT1tGGclEZ+uL3BzD06++ +K7DYbObU4N+OJQyaBWGMMEg8oWlgwmtmXnNZgeFfFLDTeVnv3I73ibQd3LGkL6CCadO bN2+DYrqCKMeKZK2ugj04lS6vydLyGVv/RMfpSOlVeUE1TCSJH03TdKrVOob2mLH19By Zdlw/wbFj2imiInrA3rrueUMzjeMJvRLmBIRf9t8BeFnmiDUgpC0X1jZWnPCCGR8b8b1 mT4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ciXUSjrJzeNJ7x1YqUH63bTMmxfwRBsuiu2kMzOf67g=; b=LKyvK/rVHrIuzEWsJbUEsGjKQHo3XtOcnnlgGBYMI/7ATCd/AQ/6jlw91zEF4PQF6L 8xIYXHpG5r7UE/Eznk4jTltr0bb0SbPeKyunJoLoa7wFNVmVQAWBXmYz0cQPFhXp5vqb fNecFBrw08lmsG4hWmvUwcq1n/crkaaXRZfbbv4XEcyXYxDIiIpUkx35G1WkCExFMAKH p7Hvr4OFz2c5ZRIF8XemocRoPpqeo11uh3D/npllYVYI6G2SUQtHh8ckXUBxx3xmo/V7 kWY2CqlEjosOdxmQHQATnhp33dBSRfivFMBuoM9WSfiuiiSkoDlzquzD5MVX9Strqi1n kiVw== X-Gm-Message-State: APjAAAUJ5nGkexUkuHbYEPAeJPtnB/rzFosMUzYM1wpl75CQYwYx+SrK Pk+cnS6rMar+ELftVofq3iYvDA== X-Received: by 2002:a63:3e0b:: with SMTP id l11mr28009360pga.448.1572891175644; Mon, 04 Nov 2019 10:12:55 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:12:54 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] dt-bindings: arm: coresight: Add support for coresight-loses-context-with-cpu Date: Mon, 4 Nov 2019 11:12:39 -0700 Message-Id: <20191104181251.26732-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Murray Some coresight components, because of choices made during hardware integration, require their state to be saved and restored across CPU low power states. The software has no reliable method of detecting when save/restore is required thus let's add a binding to inform the kernel. Signed-off-by: Andrew Murray Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Reviewed-by: Rob Herring Signed-off-by: Mathieu Poirier --- Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..d02c42d21f2f 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -87,6 +87,15 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Optional properties for all components: + + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the + hardware will lose register context on CPU power down (e.g. CPUIdle). + An example of where this may be needed are systems which contain a + coresight component and CPU in the same power domain. When the CPU + powers down the coresight component also powers down and loses its + context. This property is currently only used for the ETM 4.x driver. + * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management From patchwork Mon Nov 4 18:12:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178457 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4388974ocf; Mon, 4 Nov 2019 10:13:04 -0800 (PST) X-Google-Smtp-Source: APXvYqxD/rrG2r9V4KpCwfF+P/6u3HIiVTe06G+KxW1t+iYvJQpS2iUJ9B/+Yx/q9jInke78AV6J X-Received: by 2002:a17:906:b74c:: with SMTP id fx12mr17310493ejb.324.1572891183803; Mon, 04 Nov 2019 10:13:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891183; cv=none; d=google.com; s=arc-20160816; b=RczZS+Dz0TJCQuGGw/QCaT7eM4Z5FDoB2dFdN1Xey2yNMJxoxy1tEDet4v7pQSbFlB WdXuG3zSMz75+3Xq6VOZG5AtKfjB9vCK1NoWZXuaLxs5t+qyxW81oZGBOUDqNzR7hB6R iTCqOVmzczeNeCX1z2+FkewG+6DKZq+yXXUi6y3vVL7fYqgsLOxBpH3Dn6AnWB7SVT65 v1cfph3YFal2iNCybkX4d5rbSUAtca7ONpcb0rMqXDRhsWsGNUtyj8OXdHYQ4a+n3Y1O k4OnqBahD3QNn1phWfdm0lqIbl/HZ07BInRhLnhY0ZJG+PinBlPlE6x6dG5bL17PpAVf Am1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=6tmVV51SnSk2HYvVHQW3Mgj1F0ShkbzQvD8YUBsAymU=; b=mM27k3x35wYDKGds/TN2IKFkkDf7a6BleM0huAHFMgwP6B8xgFgfKm++TDedZHyxq7 dYwUW9b/lRpQFE0f6uc63Vrv8l2YlUuSsfjAtWgpMcY+lcs0z9jqW2vTUxLH4RQNxkhP iudIygVA/4NLBkQh/YDV9yPnJC90nX5+8O1n1czAv6iEQrt5EhJuCRhJOXqFeizAnFj1 XtS5w19LxrZxW86aSbccl4o007GtE2JVpFCvPNd3hXbhyaHv4KZPzw3ylbwocYnC2Ldb ytULM7V8UHtYXFNoSgK5nOCs9cuQ+ZLUbD/ezFG0uR94fu9ABWVkj0rSw2rWn9RNMaJF mVUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sCW7KUGI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p23si7395797ejx.366.2019.11.04.10.13.03; Mon, 04 Nov 2019 10:13:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sCW7KUGI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729552AbfKDSNA (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:00 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:43546 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729312AbfKDSM5 (ORCPT ); Mon, 4 Nov 2019 13:12:57 -0500 Received: by mail-pg1-f193.google.com with SMTP id l24so11849503pgh.10 for ; Mon, 04 Nov 2019 10:12:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6tmVV51SnSk2HYvVHQW3Mgj1F0ShkbzQvD8YUBsAymU=; b=sCW7KUGIc3HUE/GqsL9BzjnT6sINFkDABF3L4NVTNMpCiVH7pENhwh6OKQKYZB2MbO CjMf6NICEFUuCou6SNeKlkeuiqvshvVGcVvFrIxz1zL3M/LRrF1+XVQDIzmxjh1YS3MT B43VjLhL7ZiuVqm9Gm+zPezFN+24EEBjkweQ0MKJgSIhhLvVFoumq5DQeSxf7ymH6HNW FdzJPcQ2hjawP9UTYMeFbbQCUpztJHek3Hyd0ryyG3j65Qt4BH2RYCzlbO+fXpqSFcv5 ZVOAyNlYSLQo7tztXFvQj/SS9f/Bq8P9d+//OYRZQUY9wyJfqoiJJomD73hO1OySYycI RBSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6tmVV51SnSk2HYvVHQW3Mgj1F0ShkbzQvD8YUBsAymU=; b=IUtPXu5DXGPkiqiNFcDkcTFfj2uo+onzOj0jhe4QQczrpKVUobBtUZbD95QtZ6ejEv Ftr9fsluUIXJY6/yOWyqZUdy5tiPjKk9KcJ13mz/+M7CFL64nK5zu9eePReAPIqQRuVT ri51s6EbLHsCP/gGxFnduz+FDbuwS3TE28TQpepr2ICnmDrqwaYApfWiAKX9ROaPsYyN wkd2NC+XBCL9lnvhhD7S/rRPASikNbhJI8ezf80j29FEfN9QA5Uyir55qbsRvIyiAHtH oEPLG+cy8VFuHxJupdLG6mkOEeTwnJwH2Jkm9QAz83vcgB0JWvq5CtIQAm2kcOHDcLbu jy4A== X-Gm-Message-State: APjAAAUY0gaFOa0Cd7Zh5aBEX+LlCxjG1kdm4bSuGIPeSJDl8BJCsvio cboVSiSSNCmqUowvhzUQN1PMGg== X-Received: by 2002:a63:5f44:: with SMTP id t65mr23902892pgb.124.1572891176673; Mon, 04 Nov 2019 10:12:56 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:12:56 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] coresight: etm4x: Add support for ThunderX2 Date: Mon, 4 Nov 2019 11:12:40 -0700 Message-Id: <20191104181251.26732-4-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tanmay Vilas Kumar Jagdale Add ETMv4 periperhal ID for Marvell's ThunderX2 chip. This chip contains ETMv4.1 version. Signed-off-by: Tanmay Vilas Kumar Jagdale Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4cecabdd051b..8f98701cadc5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1529,6 +1529,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385 Cortex-A55 */ CS_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385 Cortex-A75 */ + CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ {}, }; From patchwork Mon Nov 4 18:12:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178468 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389844ocf; Mon, 4 Nov 2019 10:13:47 -0800 (PST) X-Google-Smtp-Source: APXvYqy/yyLB2L4Rba/+9PG2npw8//rlv0sXEl0+G4JdHhLmQuqP/j3aI2oKnZFlABHJM1pqbDV9 X-Received: by 2002:a17:906:4096:: with SMTP id u22mr25274310ejj.264.1572891227449; Mon, 04 Nov 2019 10:13:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891227; cv=none; d=google.com; s=arc-20160816; b=qCx+w7ttEucc3Q9c50udznCfIFpvZbPkTHwnX1cKgOUiAAjjjOP6/w+ECZeusXXVVY KuDUXpQAWh+jb1F2YfdHn7jXrXYKsdVphLGWelTJZjLL7owWshyIgxIyaw5YJFijyNrT QGydtEcZbGgjiOiWkLKMrfBWkcN35CkC/8wwzq4t9Z9Ml3wliJGJFfX8V9a4uQNMAJzi 0yZkhUfwFCH0oGNQ86a2HoHHdTkyiAURuZYFxR9+faTSOTY5clUwKwYPuT9yHPN7b7Hy EiqOxgx/PrQwbJz8ktgJ5V6RkRg5z0YPOsfo8gJmxJIBky/wJZY4eJhyF6McmdkCPqXr aSLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=E7xoCkAyGg4KqS2Ca2Cuf8W57nTUINvwg1saSjj42+s=; b=bVerV1XHHDjEFqEB8ZLgBEkEzHr8pay8Rd0uCVLWDTa9EXr+ddvAwwZ+B2Cb3HemK6 xwQmp67ZfYMG0RX2wx18C1ax+RGL6XaANgk7oWxJfJTSCrIAQcNonkzY/s+FKBi9L20n /TgjykI4ZRgVAsDHmIaH+aSU+b/79h0GL20TpYJ63YDTTzcii7K3AOUlGhSGbcC70drm aDumENUgR6die70Lnp+25XgjlbB5Rg0ZdlIpEZY8z8PH4687RRGEqxXU8GUGDHU2Cu0F 0PV8ICkk/l9h0PuORohyQ4BI7+K50e7zDXBCJDkNK60vnJZr3UhpvUan0+uO8yASd8Fj MMgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t89AyvOo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d14si8315180ejc.72.2019.11.04.10.13.47; Mon, 04 Nov 2019 10:13:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t89AyvOo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729699AbfKDSNo (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:44 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:35741 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729526AbfKDSM6 (ORCPT ); Mon, 4 Nov 2019 13:12:58 -0500 Received: by mail-pf1-f196.google.com with SMTP id d13so12853882pfq.2 for ; Mon, 04 Nov 2019 10:12:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E7xoCkAyGg4KqS2Ca2Cuf8W57nTUINvwg1saSjj42+s=; b=t89AyvOodQkb3twtjsFgSrZd8FgcOetjbiOQ84duI9GVheJ9U0qt3iAnoJfBxQTDfJ ahllcKMiGVLGwIxd+SRZDCtJXr1WBTkyoBnlx1EonNGUSz14J0Xpj4Sug1Gj66ATHKIZ JzhWCne3Clv0SvPpC12oY1rnr40auKmTCaFvnFjmMap12BnQLvziRTQhJFikJqmkwODP b1kRyi8dIf/J9QOgqQDwTEiPjE0pEsJzBbIr2FXEUu0eIL6XpIIH85IfgxOGfvUrd7A4 FWep+bpxecWoIWutk31xfro5mihAIDRGOYodSgE5qYWNqmDrKYiYrWbDz2Ed6QNWWcvN QlqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E7xoCkAyGg4KqS2Ca2Cuf8W57nTUINvwg1saSjj42+s=; b=p4gTok1MrfaupCzZdwdLyDodPE4Dsmkmew1Xmh5mWguH74WAy4qqQBPFvZ/F+rK57U XlQPi4qzNHM3uJVJo1sOamLckRdFDCFSMqKj0g+/MjkOlz7Sm55XrXcY2BwJH26FOv89 CryLBUhYE0pKDOtPceplrfVOIJvzXAv1frAXGo0VPIw21IgSmn542fcQIu23NoPGK7I8 3Ydfd/x+vHJKxp04+750S4zUsLW0HRJj2pW+HgbrDJXV0VgmKvzTYky4iK8tBdO0SVgQ ScAEdvRa6sl8gjNF2cOSsmBv2mzriJ2f1kq9krcp/UQ4mjLi0ISlF7zU++ZxYYM2GOZZ I48A== X-Gm-Message-State: APjAAAUznkQ/Ftx/nkwnUIZb31EbPWuljh4mI+Ie+Tkaa0LIstLV5pu3 ZQIxlAYDsuMhPEUKPoa5DvsUyQ== X-Received: by 2002:a63:eb52:: with SMTP id b18mr30588652pgk.205.1572891177665; Mon, 04 Nov 2019 10:12:57 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:12:57 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] coresight: etm4x: Fixes for ETM v4.4 architecture updates. Date: Mon, 4 Nov 2019 11:12:41 -0700 Message-Id: <20191104181251.26732-5-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates). Patch accounts for this new capability. Signed-off-by: Mike Leach Reviewed-by: Leo Yan Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ drivers/hwtracing/coresight/coresight-etm4x.c | 5 ++++- drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++++++---- 3 files changed, 21 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 219c10eb752c..b6984be0c515 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; - val = BMVAL(config->vinst_ctrl, 16, 19); + val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear all EXLEVEL_S bits (bit[18] is never implemented) */ - config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19)); + /* clear all EXLEVEL_S bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->s_ex_level; config->vinst_ctrl |= (val << 16); @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, struct etmv4_config *config = &drvdata->config; /* EXLEVEL_NS, bits[23:20] */ - val = BMVAL(config->vinst_ctrl, 20, 23); + val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, return -EINVAL; spin_lock(&drvdata->spinlock); - /* clear EXLEVEL_NS bits (bit[23] is never implemented */ - config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22)); + /* clear EXLEVEL_NS bits */ + config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; config->vinst_ctrl |= (val << 20); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 8f98701cadc5..efe120925f9d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -648,6 +648,7 @@ static void etm4_init_arch_data(void *info) * TRCARCHMAJ, bits[11:8] architecture major versin number */ drvdata->arch = BMVAL(etmidr1, 4, 11); + drvdata->config.arch = drvdata->arch; /* maximum size of resources */ etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); @@ -799,6 +800,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config); + u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; /* * EXLEVEL_S, bits[11:8], don't trace anything happening @@ -806,7 +808,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config) */ access_type |= (ETM_EXLEVEL_S_APP | ETM_EXLEVEL_S_OS | - ETM_EXLEVEL_S_HYP); + s_hyp | + ETM_EXLEVEL_S_MON); return access_type; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 546d790cb01b..b873df38e7d8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -181,17 +181,22 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) -/* secure state access levels */ +/* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9) -#define ETM_EXLEVEL_S_NA BIT(10) -#define ETM_EXLEVEL_S_HYP BIT(11) -/* non-secure state access levels */ +#define ETM_EXLEVEL_S_HYP BIT(10) +#define ETM_EXLEVEL_S_MON BIT(11) +/* non-secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_NS_APP BIT(12) #define ETM_EXLEVEL_NS_OS BIT(13) #define ETM_EXLEVEL_NS_HYP BIT(14) #define ETM_EXLEVEL_NS_NA BIT(15) +/* secure / non secure masks - TRCVICTLR, IDR3 */ +#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) +/* NS MON (EL3) mode never implemented */ +#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. @@ -238,6 +243,7 @@ * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection. + * @arch: ETM architecture version (for arch dependent config). */ struct etmv4_config { u32 mode; @@ -280,6 +286,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp; + u8 arch; }; /** From patchwork Mon Nov 4 18:12:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178469 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389857ocf; Mon, 4 Nov 2019 10:13:48 -0800 (PST) X-Google-Smtp-Source: APXvYqyI7Jt3u9Za7f8pgIF2qSYWOlo2r0fF+Xqep/yIY19MOQXRIdEgRNiXFFVdss6maBVIqCJO X-Received: by 2002:a17:906:780e:: with SMTP id u14mr24629104ejm.97.1572891227994; Mon, 04 Nov 2019 10:13:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891227; cv=none; d=google.com; s=arc-20160816; b=ReCQk06+Bhg1kr3UO4W/BC/suxGOce+Jkcxw9ELjxlEr6bU4WoExWIehCmvITJgfNO hXmW4QbqENSEFpSLDNrZsrCsc/S33SrHhF28OdJiOViFj7NYvYdyDkCsJZRi44MR2u6H nRh0fGnH2TDig4D+NYbqiHn4qwWH0mJUVu5Qt38fE5SfvLD1dzvXIhv43SWhYbNLCVx7 n4l22Uirokl+xReD8rqgEQD5v7/iK4of+dWjfWITkRdGhhvx1p6sWxl3RgvLcoxqgrbO UHE9EkRFiWMBaHVq/p2FtFe0dL/MeDk4C7Ly6pPBsHxBEVfQLx6iF7TR0sIu4PGC8/gd 0mkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=my27JHtSw35YmWWmHWoHmAi4DXJc+0VoUXAKN5Q83qQ=; b=f2jyGj1i/bxoodZvfzRGFgwyybVeuSqenecNV6bbqW4Hu4ydroT2rXDY/jpAiumfue IfFV52bCqLbj1PTiHlMttBHi6TbYcEblXOQQDj49Bklbt6uBDrRAEjAEFOju3Hdan39m bN+lHLQ5daX1RcEOou4WdE/qaTjRkm3GPDGL8bc0gSoklD6Od3NT6VvH7E2WmobZqdNx 9Tw+3fKvT0Zhh9cn+eaCV+YERAbldFUzyjp/BBqzIvNN6WEgEKJBb+I/LAmTTPhrsM7z R6qqtAg3AC4fw9iyS8E9hMPRB3Mpl4s8/BsWaKLaqVxtf2x/0DByEjaXUKIZUJYcKa6G s+fA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z04j7Z2+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d14si8315180ejc.72.2019.11.04.10.13.47; Mon, 04 Nov 2019 10:13:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z04j7Z2+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729685AbfKDSNm (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:42 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:35745 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729546AbfKDSM7 (ORCPT ); Mon, 4 Nov 2019 13:12:59 -0500 Received: by mail-pf1-f194.google.com with SMTP id d13so12853950pfq.2 for ; Mon, 04 Nov 2019 10:12:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=my27JHtSw35YmWWmHWoHmAi4DXJc+0VoUXAKN5Q83qQ=; b=z04j7Z2+8CJTt3LDDdW0VKHsNjM427ulg1Fso6sALQXW8v87GYdFumTZ7klLVibxEO u3G+y2NH9jFQMLEt7KsjCEQA4m8ae69T56BnjtQLjDD6o24drb+6r7tkLlJcCvxPI6o8 VnUTGyZhug8t2LgkcTeeOZ+M1/3nFrEg0G7+1G2edZVz0UCTAWywDjC5fb79COINfgmo qAoLnJx3CQxoKGvRs8t9dFVwThrdoa7bRgJ2rAoZzuqiYu7izvP0JuLduGhaDzKWWMzG 8swo521Or6HZH3IbMWHAfwHUsrf5P3Lj9OdeSbipMpLXruapJlUzqDlhg8qLeRWdY/l9 4jGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=my27JHtSw35YmWWmHWoHmAi4DXJc+0VoUXAKN5Q83qQ=; b=D323UOt1ctWQVOzLzY7yGArA2rjcM4eS8EAJybNzSL8VBOePTdE914K/REv1WK+o23 UQMZS5ozQTnPOHp4Ij753zdp5Ncpzbr87OMEqQcPdIQDpwO0SLaaRlU0rlJ7DO4C4XZs wKLnhIqzNqjmIxWuKNXKhac2CWmhZ2M9QKa1pq6m6m8i3WuU88rHNZkaMxg/NRKeF6gd BiZ9x3pNE77JnNDs16mmz/mlY1sDbnwIS1tbHsudPoFLsBI12MGrKoUy4x0k3fgWgSfk 3DCOsT357nELT8xubl9lWZ2dJ6OLqIAwmjQPJ5e4v39Hs55dFimzfjl+So6hbDBdhZTu fcFQ== X-Gm-Message-State: APjAAAUHG4jII0hQCSx2BP88UmttcLfyYq1oN3BmlwuwG+Fs3ol7UJzi +gY//V6/5MIvVcUq0L+C7rsrHg== X-Received: by 2002:a63:1e08:: with SMTP id e8mr10948373pge.336.1572891178635; Mon, 04 Nov 2019 10:12:58 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:12:58 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/14] coresight: etm4x: Fix input validation for sysfs. Date: Mon, 4 Nov 2019 11:12:42 -0700 Message-Id: <20191104181251.26732-6-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach A number of issues are fixed relating to sysfs input validation:- 1) bb_ctrl_store() - incorrect compare of bit select field to absolute value. Reworked per ETMv4 specification. 2) seq_event_store() - incorrect mask value - register has two event values. 3) cyc_threshold_store() - must mask with max before checking min otherwise wrapped values can set illegal value below min. 4) res_ctrl_store() - update to mask off all res0 bits. Reviewed-by: Leo Yan Reviewed-by: Mathieu Poirier Signed-off-by: Mike Leach Fixes: a77de2637c9eb ("coresight: etm4x: moving sysFS entries to a dedicated file") Cc: stable # 4.9+ Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index b6984be0c515..cc8156318018 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev, if (kstrtoul(buf, 16, &val)) return -EINVAL; + + /* mask off max threshold before checking min value */ + val &= ETM_CYC_THRESHOLD_MASK; if (val < drvdata->ccitmin) return -EINVAL; - config->ccctlr = val & ETM_CYC_THRESHOLD_MASK; + config->ccctlr = val; return size; } static DEVICE_ATTR_RW(cyc_threshold); @@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev, return -EINVAL; if (!drvdata->nr_addr_cmp) return -EINVAL; + /* - * Bit[7:0] selects which address range comparator is used for - * branch broadcast control. + * Bit[8] controls include(1) / exclude(0), bits[0-7] select + * individual range comparators. If include then at least 1 + * range must be selected. */ - if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp) + if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) return -EINVAL; - config->bb_ctrl = val; + config->bb_ctrl = val & GENMASK(8, 0); return size; } static DEVICE_ATTR_RW(bb_ctrl); @@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->seq_idx; - /* RST, bits[7:0] */ - config->seq_ctrl[idx] = val & 0xFF; + /* Seq control has two masks B[15:8] F[7:0] */ + config->seq_ctrl[idx] = val & 0xFFFF; spin_unlock(&drvdata->spinlock); return size; } @@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev, if (idx % 2 != 0) /* PAIRINV, bit[21] */ val &= ~BIT(21); - config->res_ctrl[idx] = val; + config->res_ctrl[idx] = val & GENMASK(21, 0); spin_unlock(&drvdata->spinlock); return size; } From patchwork Mon Nov 4 18:12:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178458 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389105ocf; Mon, 4 Nov 2019 10:13:09 -0800 (PST) X-Google-Smtp-Source: APXvYqyh/PZls+t3ak4JDwBM1qiG7+bqGsHVqgKGSQ9DCKGqY258+fGrT/zxXbzE3xl8m7Odtc9+ X-Received: by 2002:a17:906:d96e:: with SMTP id rp14mr6435285ejb.14.1572891189551; Mon, 04 Nov 2019 10:13:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891189; cv=none; d=google.com; s=arc-20160816; b=pi9GBPkFQ36MSDZH9KDyzp96dv5grI9O7MkZ9q19kfAbzj6MYQRo4/gqHSJWXpQOrO r79cQRncE8Dj8eichB7hoOQ/TwwLYim7HNIz2NIoH3xj/cyzx+aVZOJXGn8SJbsexlxL PY20CClGZejK8ARFZa8oCw6IQtg4q0X5hRJKrstaR8uXHSGszXIIHe5Xqbv2zCyhHLWj H2yJuaJYm2uFpGiT9uxuKCOqQDpyEsm9f9YUDNA/9A9qLv9MrWx6rQEwUTwUwhdGTIXA Y13jX18w0OFMqoGFJltxM0Yl7tqWVNHbyvn12RcsejWdebTfqG2HKvwHE5O6MubdjIwA TqGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=y7fhR2xIT71DtVa1uCjsmuyALGEUbfwLZ/uWrAtc5Ds=; b=j+SMz+r3/GuilEIDuCpUibZjQsUCZ0KQqUWvoWIojsB4gVQ4BBEceoiJp/vbVRqBms jRWMBmhF74i02EHlSg2vkd0g5IGB2tHK5dknRSpP3sduZP3FOZfghsQDEpOJ7I869Szr FR5aZYiFBLOh7+7KbT92nDDZq8d7PXKK/vJ8qkirHlFamJ50vM2ZweQkH0haJj5iJeSZ jRE36PdL3u4VurLvuhpZASCEZY7Oz2KZZOpZn4VXHq+cWItVinoLE878SHrinwhE59/Q aIHNdAQqj076dZ5YZ2Ssna+nrSGHKdBOzqNoU9YG9CuFJULUWL5qelVKO1i8e15wyjDR L8Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ncL1xXHW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n5si11869911ejb.67.2019.11.04.10.13.09; Mon, 04 Nov 2019 10:13:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ncL1xXHW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729585AbfKDSNF (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:05 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:44685 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729551AbfKDSNA (ORCPT ); Mon, 4 Nov 2019 13:13:00 -0500 Received: by mail-pf1-f196.google.com with SMTP id q26so12824108pfn.11 for ; Mon, 04 Nov 2019 10:13:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y7fhR2xIT71DtVa1uCjsmuyALGEUbfwLZ/uWrAtc5Ds=; b=ncL1xXHW8P5PY1KFS4fr2rCjeF2sMk7iCiCvP5ewN58vIqpf6Rk7KIPwWJ4UL8t5YD YYnfOLoEGsFqg7qgmY4p8cERoL3Uj+k3kbnmUKhvlr9kQFM3wojFfN3ZM65dBok06MfV wSXhWlJmSdmEquXZz/Ly5hdUm4ZKvCxsJrnfuM4hTXRBPA9aMaHGfUG9CCweujtLSB5D Z0PyiIe36Z3vKEgKByN+KrWgLj4Fw1J2XjbHNts9//oUwu4rn8VpybUEkPpVVhRSAEsk 5V9EOoMUphNsDxdm2mQ0yF1JDGS6ULnV94+Qv8m7pCID4hQ9DBBNFeUoG2qB/siHWBdL nKcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y7fhR2xIT71DtVa1uCjsmuyALGEUbfwLZ/uWrAtc5Ds=; b=MCG935es5SkdSatzpNe16/6hGlvxBuDo2TnIgDsA1MvYI2dB3AqHtT5qugFWNQGNOu DTGMSt8FM38T4Tdt97HC3LaJ6hAn5BVo+zW6mYBNHUWtH2UZAZ8A6Se7w1oF5xnW/kFK 4cM5eh9Lv+Z7gBVha3s89riy02LJr9VZX4aQyD0BFhvdDD6Y1frZSIcDKFYxgb+qqmZR rC0DBXc6cclR7ojVezKEAsL/B3T1iVqPOu/n8e6L+7AqrQSMwCA8i5WXjicdFCy0qTiV Wnoo3j4NhxhL2V5KYjLMD97W9LrIgVW/oyEF5Cu5l5vQKtdpE2zGXrPVm2MOwi53tOuH GE/g== X-Gm-Message-State: APjAAAUxOVvr0UZDFISdk451QdiTCFGkFWfd5Rp/KTlV89sd51CfeHVQ 64Verw6mKj+Z1nAb7lzTkFgNKl5NpcI= X-Received: by 2002:a63:2d81:: with SMTP id t123mr31539251pgt.306.1572891179732; Mon, 04 Nov 2019 10:12:59 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:12:59 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] coresight: etm4x: Add missing API to set EL match on address filters Date: Mon, 4 Nov 2019 11:12:43 -0700 Message-Id: <20191104181251.26732-7-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach TRCACATRn registers have match bits for secure and non-secure exception levels which are not accessible by the sysfs API. This adds a new sysfs parameter to enable this - addr_exlevel_s_ns. Signed-off-by: Mike Leach Reviewed-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index cc8156318018..97a33cf98797 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1233,6 +1233,47 @@ static ssize_t addr_context_store(struct device *dev, } static DEVICE_ATTR_RW(addr_context); +static ssize_t addr_exlevel_s_ns_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + val = BMVAL(config->addr_acc[idx], 14, 8); + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t addr_exlevel_s_ns_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val & ~((GENMASK(14, 8) >> 8))) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8], bit[15] is res0 */ + config->addr_acc[idx] &= ~(GENMASK(14, 8)); + config->addr_acc[idx] |= (val << 8); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(addr_exlevel_s_ns); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2038,6 +2079,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_stop.attr, &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, + &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, From patchwork Mon Nov 4 18:12:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178464 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389490ocf; Mon, 4 Nov 2019 10:13:29 -0800 (PST) X-Google-Smtp-Source: APXvYqz7O+wSUdEDa9x6DajQ8K05x8T/uuaaiy5RDqq8bSWl/ja9PVsMp4AMMF9B5XGkb205btxc X-Received: by 2002:a05:6402:b02:: with SMTP id bm2mr8799185edb.130.1572891209721; Mon, 04 Nov 2019 10:13:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891209; cv=none; d=google.com; s=arc-20160816; b=cEZ9ZjVI3zqWDZ0hs76Evyt95imXCfHGLaothJHIm9Z0K9Bqbalt3E6ajS5SLIEo5j yZB2yxYd5fjTcuR0mJ3QGX3K0fuEqS2SSc8axkqumNTyXhiSfur9mMBoW4vwLDiuU+4I xqP68Q+tlOxzzaKySicfbp8wbWmp4zw2ztKFelv4hHPvzQ9K9UOX6PWiG8QezAsk+v0B VWmjQ7ZNaczAyZHIMMhgyy8ZA9ZrvsziAcKnK0WL6eDhOTU/fAxUoK0JgbSOMTzm36Sx J0R2C3ohprsiSUVb+KRTLVVeQkR5oNnZbo5gRSvavkeyexbXgof965NaCew7vD7qL42o MwMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=UoBtG+nF16UHzafLtrzcMC8PlFDrifr/5EvMb5ijQAs=; b=B8vSLM6+Z2QUo3rCOh8PIj/w/sKQBFOtFGu0b82GVl3hC+nkx58G/2qdl+lwXGcyxO xZ1Asdxw0pF+mwqh7oqrFIfQFhYjeZCvrN/ywR1ZN4ZXFT8LKqvL/wYBU2JVQYs6Q6Un cB0+LXE6iTceOMvMztuDRlGwbSdBmk7EGhzMr6HNbSAVI+fqSb7HVzGQVIG+aIxDCsCe uJyuI3A8d+Z1ogzGZiqs+mh1i4R0dZo7gS4y0AznknnsMdSRG56vZBvyAg5nbWJT+Th/ osZdoeH3QD1oj4nyMm2Bu8aVwuU2yHmEpb1vUiTG4Z8Ryeqd+Etn4Owfaxa5PpEF7rCA TFZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jVYwJFxe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v5si4722268ejr.30.2019.11.04.10.13.29; Mon, 04 Nov 2019 10:13:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jVYwJFxe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729601AbfKDSNH (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:07 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:43768 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729560AbfKDSNC (ORCPT ); Mon, 4 Nov 2019 13:13:02 -0500 Received: by mail-pf1-f194.google.com with SMTP id 3so12828302pfb.10 for ; Mon, 04 Nov 2019 10:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UoBtG+nF16UHzafLtrzcMC8PlFDrifr/5EvMb5ijQAs=; b=jVYwJFxeB6vT5IGMoonP3YF6fOpjwXCdfVOS/7OpSJX4cc4wXAj962jWkdB9GsBCxY bjHhNgBeA2Wm7EGhnkcZXmP62Jt4Uo6WmftW4ZmaPG9Xoq3lKYwZwI3+BAKuCuxz1IGu B6rbpe7+yCnDIM3QCEx8zpAxF+vB0bURB+tKN4patZAPNoZfFHHvtTZJsMVfcgxjAMq9 WWCAZGyCSkc0BoG2GUS+qmk7k46nvqAE+KEAydo59RoC8UPRfp4OthjYV+v3tiW4rN4N 8YQuDnqeOKhMqkwx5pxBv37c6L6CGZUs/tVRDIahaJl5bYHJGjWBGbi7CNKcvFpQqFdW SPwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UoBtG+nF16UHzafLtrzcMC8PlFDrifr/5EvMb5ijQAs=; b=LWzDIhgHq6M7e4RqWSS57Mq1b8EBsK3Anx0yc1juz8sjyA/0RMLAygd7lK+pBub+Z1 +1HSZTeseNA1MH/CeV8d2V4Huerz0udnGYHYyYp9n1gKYbx7pFa/qFee8qK5P1mTtgXG 1Z52IiFdqBxe/OW/7MADNu1DNoXZLDd3qxy14IEF5NckqIeARilwU7whrOtSBN+fOOTA 4a8yXRSbIQ7PgaVqGOSUarMQ1qccMhUIka+oSDfMDhmu4mGfSG3BPK3WjJdctlTdqM3D bfhFkoPyqwOVKjnLoNqkwKvuNvWwFtLxK6C9J2V3gwG1f+M81/zhudhGBJOuYV/PtVO4 7vJg== X-Gm-Message-State: APjAAAX/xzkEj3HCe+AGU8/lxmoOqMnBHuY4sEzDBhjSi9FEz2F2c+fL IgJOOQILLQYXp7GiLS2kpZ9wxdxtcQc= X-Received: by 2002:a63:e009:: with SMTP id e9mr24399463pgh.222.1572891180912; Mon, 04 Nov 2019 10:13:00 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:00 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] coresight: etm4x: Fix issues with start-stop logic. Date: Mon, 4 Nov 2019 11:12:44 -0700 Message-Id: <20191104181251.26732-8-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach Fixes the following issues when using the ETMv4 start-stop logic. 1) Setting a start or a stop address should not automatically set the start-stop status to 'on'. The value set by the user in 'mode' must be respected or start instances could be missed. 2) Missing API for controlling TRCVIPCSSCTLR - start stop control by PE comparators. 3) Default ETM configuration sets a trace all range, and correctly sets the start-stop status bit. This was not being correctly reflected in the 'mode' parameter. Signed-off-by: Mike Leach Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++-- drivers/hwtracing/coresight/coresight-etm4x.c | 1 + 2 files changed, 36 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 97a33cf98797..ea1e034809a0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev, /* No start-stop filtering for ViewInst */ config->vissctlr = 0x0; + config->vipcssctlr = 0x0; /* Disable seq events */ for (i = 0; i < drvdata->nrseqstate-1; i++) @@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev, config->addr_val[idx] = (u64)val; config->addr_type[idx] = ETM_ADDR_TYPE_START; config->vissctlr |= BIT(idx); - /* SSSTATUS, bit[9] - turn on start/stop logic */ - config->vinst_ctrl |= BIT(9); spin_unlock(&drvdata->spinlock); return size; } @@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev, config->addr_val[idx] = (u64)val; config->addr_type[idx] = ETM_ADDR_TYPE_STOP; config->vissctlr |= BIT(idx + 16); - /* SSSTATUS, bit[9] - turn on start/stop logic */ - config->vinst_ctrl |= BIT(9); spin_unlock(&drvdata->spinlock); return size; } @@ -1274,6 +1271,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, } static DEVICE_ATTR_RW(addr_exlevel_s_ns); +static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (!drvdata->nr_pe_cmp) + return -EINVAL; + val = config->vipcssctlr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (!drvdata->nr_pe_cmp) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + config->vipcssctlr = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop); + static ssize_t seq_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2080,6 +2110,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, &dev_attr_addr_exlevel_s_ns.attr, + &dev_attr_vinst_pe_cmp_start_stop.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index efe120925f9d..d5148afdbe80 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -887,6 +887,7 @@ static void etm4_set_default_filter(struct etmv4_config *config) * in the started state */ config->vinst_ctrl |= BIT(9); + config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* No start-stop filtering for ViewInst */ config->vissctlr = 0x0; From patchwork Mon Nov 4 18:12:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178463 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389444ocf; Mon, 4 Nov 2019 10:13:27 -0800 (PST) X-Google-Smtp-Source: APXvYqzQ9w7yBUo5YNwYvdmiZRpDFZjG2fXfhoA9iJL5fNb7CJWLoLANK9wdfvUSbRjK8Ng37xQv X-Received: by 2002:a50:cc07:: with SMTP id m7mr3933211edi.34.1572891206977; Mon, 04 Nov 2019 10:13:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891206; cv=none; d=google.com; s=arc-20160816; b=vT8OBNjm2rt9fw3QNsGsWjPoEGXsC1ZB9/U2G3PhiXn6Wo0FD0f8Kc80GvpcDkFg8z 9qPiSyI5Be1fw3HRI1EmzW8U8kTBM78mV3akbPWRkziv8HuOW5c5AbjCji9dgM4s30V0 t53EqaHYloD8W06UBfT/54To4aSPbLcYU+mjMo3TPk8t0QMR4JuFQx1rBGD7w58Hogss rSMo4EDPTJn/OgTGltr/QjQRV8Vl9nxWSz/7e2OjGlkm6xLPGkYzLuyadPHmYmX16xpd eR1xq9CtR15cPlYk6HSJLreICYfW5iVKBl5TXSMFGL7w0kmaetjLH9RGZNqDrod13bBf XujA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=U+l5F417FgwxWcTtFu32EwI1EYbG0FhwLJDw4Yrt6Kk=; b=nYlDsPAQmHkhGTJkTQI6W5kPTgwmmitq+Kj+hLeR3QdXa4dZ0sOVJil5hyhczCjcWB +tUXmKO7xOGl8L4zZ49moAKBBfIsKvNzfEq1mY8PLOOK8kg+Ke8tqSekgeBkMXGayPhg u4s1kC8uAl6qL1Kec4LW2l3vPRrn7rTjXqNBBcg4ECXWIdEiEbTDoBsqprgiWtIeC7UX oaxfYDvakrnWd+dEQ637tEK217Wm+7Fj4oI12UypMlWuOHcqc6/XYqdPM1FyE9R578xP ycrztYnRnGkSc5IBdMQHVX1Kv2Z7mXRQK0XfJHUQKNNNrTpLK/D9c3OE2OYu1rgw/zyk p8MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a1jb8Ocw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o14si1259472ejr.14.2019.11.04.10.13.26; Mon, 04 Nov 2019 10:13:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a1jb8Ocw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729613AbfKDSNJ (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:09 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:42085 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729575AbfKDSNE (ORCPT ); Mon, 4 Nov 2019 13:13:04 -0500 Received: by mail-pf1-f196.google.com with SMTP id s5so4591253pfh.9 for ; Mon, 04 Nov 2019 10:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U+l5F417FgwxWcTtFu32EwI1EYbG0FhwLJDw4Yrt6Kk=; b=a1jb8OcwTE5t6kokOfUIYVmLkWL2FZZgFIN/0R5uVkBpmKKDWvJfCvPfJ9u8yB8Kf8 NTYF3XWmVTiaxaNVI32u9UZmU5S+IS08LieUsFQCNBRqlL9X8OJqF/sARnquhMvO75/Y u5RXCedd4ox1Jw6PcwNFBSW6IQXUOSYq/74z0p/hT6/d2jnWw9niOxQVdYx9gHNJ1evp U5GRkytFxc9LurRnKgxfZU8Nh1B+6qqbkdCPXF0puBUkhJdlYIWgdJQqoMmIY5O494AJ zycuKZEwFVUJwV3QkUlpeRJpzomlzAhsRU5TuINBJeTDcM+2v1UbRJQFYB6bSImL5fH7 WBKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U+l5F417FgwxWcTtFu32EwI1EYbG0FhwLJDw4Yrt6Kk=; b=FUtJgCiCEQaK+AYq26AlUQOo1xIDi8xQb/scMH/IPS/OfMlnYjM1zQYtphY4kIHnvV U6/+AwG6vd1JdyBJ+aqinao0fStfMRE2+lprtvLKTN4FdIHaPyEqMFrRw2cW6kHkhwy4 TbiB7KVVTYYRLl3jwK0g6M4vRC2QsS2Cbh0ys5lNKSaWoUvQ39QXo4epqMwZ60AiZdJZ Ajl96ZtsGcQ0gmqB6uqRa/xX6g6Hy6Wl0SrS3SALgmUyJlW2UGfBuxVMMdQyB7VIZvFI E/UkbOxtWnAO3kqjRxYEZ59lo91TVLXCgudMig2WN4ZCuOuWAKtgEheHBYdokixETk89 j4ww== X-Gm-Message-State: APjAAAXOeyzhueIJfkx4bkZ1U//CQ+h/dVyKXtwYdQbfcfg11IYISzsr GoNuGfONdbvXoUul+gGm3NaQtEUmEcM= X-Received: by 2002:a17:90a:7188:: with SMTP id i8mr601428pjk.54.1572891181785; Mon, 04 Nov 2019 10:13:01 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:01 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] coresight: etm4x: Improve usability of sysfs - include/exclude addr. Date: Mon, 4 Nov 2019 11:12:45 -0700 Message-Id: <20191104181251.26732-9-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach Setting include / exclude on a range had to be done by setting the bit in 'mode' before setting the range. However, setting this bit also had the effect of altering the current range as well. Changed to only set include / exclude setting of a range at the point of setting that range. Either use a 3rd input parameter as the include exclude value, or if not present use the current value of 'mode'. Do not change current range when 'mode' changes. Signed-off-by: Mike Leach Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index ea1e034809a0..8c056dd1a55e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev, spin_lock(&drvdata->spinlock); config->mode = val & ETMv4_MODE_ALL; - etm4_set_mode_exclude(drvdata, - config->mode & ETM_MODE_EXCLUDE ? true : false); if (drvdata->instrp0 == true) { /* start by clearing instruction P0 field */ @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev, unsigned long val1, val2; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int elements, exclude; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude); + + /* exclude is optional, but need at least two parameter */ + if (elements < 2) return -EINVAL; /* lower address comparator cannot have a higher address value */ if (val1 > val2) @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev, /* * Program include or exclude control bits for vinst or vdata * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE + * use supplied value, or default to bit set in 'mode' */ - etm4_set_mode_exclude(drvdata, - config->mode & ETM_MODE_EXCLUDE ? true : false); + if (elements != 3) + exclude = config->mode & ETM_MODE_EXCLUDE; + etm4_set_mode_exclude(drvdata, exclude ? true : false); spin_unlock(&drvdata->spinlock); return size; From patchwork Mon Nov 4 18:12:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178467 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389621ocf; Mon, 4 Nov 2019 10:13:36 -0800 (PST) X-Google-Smtp-Source: APXvYqwgsLDRiciQNuV5Cvl5pZgFirOawoiUejry39xPPcPR45tWWjlzDsmaDtvxnT0waKG89FIl X-Received: by 2002:a17:906:c836:: with SMTP id dd22mr25521259ejb.178.1572891216801; Mon, 04 Nov 2019 10:13:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891216; cv=none; d=google.com; s=arc-20160816; b=zLDFVzzgVkWwgZYnzmatQdRWjTjA4hrKfEbxBZmSwtAlqN71dgjw659N+hgJoO/e5R qxqIXDrxXZB9P8ybLaDw3nRF/NNzy0dJvkkLLpCMnRTsAvOAOaNmzuTbRg902yeE0bUQ ZqbZeTv8Er/TZMk93gh/59t0Qq7iXVm7QDF8+cE5mBggucZkXVwbRp1rvP/EietXzALm FsHYLEabTJ1TQhgU5qa2TJnMVQrB6QENhKOg4tAupkgqNR5WyD+WOxhKZPw9WxXY74fG xeh0qZ+41scKwg4Cn4+CiD/90Lq5CMB1O7Hy3QRKFSXy28f7mEHgcL3hECGsdnWCS2Au Mw+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=7stn5BvcqloAoNFXBRjk24YnQtbNG8jrtuNQJLNGPFg=; b=buwWvb/O7M5ceDaOyzfhv9Rn2hUIKTP3Jdc34UG4JGMc5ZUf0ULeE+2anAOyDl1MaD T9ZVT5IjzMKpr7HfwYLri4/0Jk4yHrwrk6mue5kwJ0OYp3HjSp4YTbg+SVjLTALTU46V S145trm9m0BzJH1AzKG+Sb1J6qk5tbI5fWMSSSxVWvM2i2ZuOzCox44SGIwk4LVns8ej ISkIrAd6HawXUXvheRQI1Qs9Ixye9/qnu6BvKb11d7VSjRDo+cISGq6JLBTazjs4HEBW KX8f4k1XmZ58dnC9262oJKsQqZLxQ71rg7fnrKuSk6OFVOHdr9vYi6d8dJO4rih9mNUc 1MJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMQbpOtI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v20si8362293edc.69.2019.11.04.10.13.36; Mon, 04 Nov 2019 10:13:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMQbpOtI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729675AbfKDSNf (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:35 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:34649 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729573AbfKDSND (ORCPT ); Mon, 4 Nov 2019 13:13:03 -0500 Received: by mail-pg1-f195.google.com with SMTP id e4so11880994pgs.1 for ; Mon, 04 Nov 2019 10:13:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7stn5BvcqloAoNFXBRjk24YnQtbNG8jrtuNQJLNGPFg=; b=EMQbpOtI2YNym5gI75LlpBcBp14xUt5R7POgwM7ZPd9UULrfsWzvLsBIy0RkRVMprw vLnspaQOxFB1BYjNjYrhC6eSCyqdMOlvaosK530wtsApKQVKpRieKHKJFahv6E9avbXD vtAFBxBriElcz+PI689voveZ014HXJbT74mdK6zrubEhk3UJjIKRT9AyKaHGiJhXn13x c2k/omTkcmBzJsJMLJhM+28dBfx7G0QAwbI6KY1N2Ml536/XZ3pRUDLnnhuZld/KO/zB xGyEFN+3GcnMsF6BWXu3wNquc5Tkj7h47UE2r+t1roOHuxrUVdTzVy+OWQmbUubOXvtT iqzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7stn5BvcqloAoNFXBRjk24YnQtbNG8jrtuNQJLNGPFg=; b=R7gEY84Fn1UprcMDA3XQzKqCz8W09eR6AQUEty3j/rt/2NJsAtSyl6zgP1xEByIvfA U2MOA17IFByCXLb6CXwQD4uJow6vPaPYpzn3KjFgvGsjr2WlUWWRkPbQ2+NBKSmh9A6V LvX3OnMni5iPLOEfBinszc6QbuT+REWm93soHcKc5w98xAmKiWzYIRFiFux9m0VK74Bh IbolwlvUZEjizsT5HvDBI6qGuvpk+Y751n+jaV2/fyAMcvjxgHzxeusGGivjaO8OBvPh nuRrq1gk6aznfiHtSDzXXNGf1vt/HxGPlcWgiuOVX7H4w8ybB2zJHXf0KD8iTtyCN1kC Cvxg== X-Gm-Message-State: APjAAAU76+7RNYdRi3u7Bvq5osdkkQqwx00UNa0TsLNZqjECZA4imlEK +s5KDtH0nT2Ib1UbcGPdC0kouQ== X-Received: by 2002:a63:1c03:: with SMTP id c3mr30491255pgc.198.1572891182711; Mon, 04 Nov 2019 10:13:02 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:02 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] coresight: etm4x: Improve usability of sysfs - CID and VMID masks. Date: Mon, 4 Nov 2019 11:12:46 -0700 Message-Id: <20191104181251.26732-10-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach Context ID and VM ID masks required 2 value inputs, even when the second value is ignored as insufficient CID / VMID comparators are implemented. Permit a single value to be used if that is sufficient to cover all implemented comparators. Signed-off-by: Mike Leach Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 8c056dd1a55e..1cfbddda0b4d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1794,6 +1794,7 @@ static ssize_t ctxid_masks_store(struct device *dev, unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int nr_inputs; /* * Don't use contextID tracing if coming from a PID namespace. See @@ -1809,7 +1810,9 @@ static ssize_t ctxid_masks_store(struct device *dev, */ if (!drvdata->ctxid_size || !drvdata->numcidc) return -EINVAL; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + /* one mask if <= 4 comparators, two for up to 8 */ + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); + if ((drvdata->numcidc > 4) && (nr_inputs != 2)) return -EINVAL; spin_lock(&drvdata->spinlock); @@ -1983,6 +1986,7 @@ static ssize_t vmid_masks_store(struct device *dev, unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + int nr_inputs; /* * only implemented when vmid tracing is enabled, i.e. at least one @@ -1990,7 +1994,9 @@ static ssize_t vmid_masks_store(struct device *dev, */ if (!drvdata->vmid_size || !drvdata->numvmidc) return -EINVAL; - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + /* one mask if <= 4 comparators, two for up to 8 */ + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2); + if ((drvdata->numvmidc > 4) && (nr_inputs != 2)) return -EINVAL; spin_lock(&drvdata->spinlock); From patchwork Mon Nov 4 18:12:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178461 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389346ocf; Mon, 4 Nov 2019 10:13:22 -0800 (PST) X-Google-Smtp-Source: APXvYqzN+XP0ciTNY2Hw3dJ6RQCsNDN4/0tAmV6eCQs2i1dcl89gQQplcUvOTLoeDt4g8NeDHlJL X-Received: by 2002:a17:906:7257:: with SMTP id n23mr25580465ejk.132.1572891202338; Mon, 04 Nov 2019 10:13:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891202; cv=none; d=google.com; s=arc-20160816; b=vdzUz/vHHSoYxlfjKpDEMpTAcYvvCi64dcyGCUsGnEgwJzsAtPd27XUu1EVyPXsCXB St9ynijqgCLk4rTzAedu7funwYNyRzSwFRb5fFk5aeNplWsZf0mymSUACBxq+wN2jJNJ HloNjU6J9L9NTo8VBh8Y13pa4ZYMvawaED+pkJrGqIc+C5NF0IGsmM0tcMyqBhvBCRgk vOxnn/EpxoA7JkTe6zPviJCDXeGy+/DC7x+V24+G1J0cmlwiNGA5B7SiHod2cxNbW0r6 gQMNdP+p/V1IudOtlELiebm6iSsbbUFlWTMiNQa26bhoG80u43/xxr4ztQE8Z7SN3otK AkHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=2TYCPoaBU+FOY9wFLOA8g8gCr6xKGu2mGQ2/GrP3thc=; b=tD3jOXzvhXv6sR7XPy/pTDqZI2kT/2xxFgUKMq5o5K73EKjybf6RuO9Fv6CwmFKZp8 xlROAGKOw1RMLxLGPtz1rKKbD1N84izPpkUHTrcXCJWAc23xjLd1Hogum2Y742hJg9LW P5u95ZwOEMiK16ll7zbCIbYi1nIjgIWGfOpXe0q3t2hIWhl1Qg2i5U3/fyDjIEmXmrse eOmotQufogzw+EZv1beS2CjWXYpJHsNO0PmxeHFMQDkKlnlNvz5fKXdCgYqHHBvr3UAk AsWlbfN43V2xr8AT/UgbA0DbqYH267x0vCUPQ/auN7FPeuTN/gSNaDRBY1hKTWXiTaHd 2Jug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yK3rgZ6y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u1si12482755ejt.18.2019.11.04.10.13.22; Mon, 04 Nov 2019 10:13:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yK3rgZ6y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729625AbfKDSNK (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:10 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:35755 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729581AbfKDSNF (ORCPT ); Mon, 4 Nov 2019 13:13:05 -0500 Received: by mail-pf1-f193.google.com with SMTP id d13so12854374pfq.2 for ; Mon, 04 Nov 2019 10:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2TYCPoaBU+FOY9wFLOA8g8gCr6xKGu2mGQ2/GrP3thc=; b=yK3rgZ6yZD3RNfOAUT5KKC7wvdg3eQXm0qjVkejDULzy2iZuRlmvREq3bbhUpdK1yS khALmRPYxY4dlRY+isX9N4agFR4UoTPsKwD/6vsAIqMDfeWxfvaKoMPf7chzzc5q+54R vEB2N2EuUUUbnGG5bMEjscAaxdC8YI8lQBdbHz+PCeQrjyVO+7JpmNQslY/XnMlDe1PW Wi2ydjh99cSMbKV58a+E6gX6sBCdrFuLjdvWRDZpVEILepT4at6fB49Yorc43Q9JXYXX TM+5i7xjPb7+QaGyNajUfII87qr1XfK7oIb9e5AbS9tvHPtcD8NSGbZTen6Tx9fNnMS7 hD4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2TYCPoaBU+FOY9wFLOA8g8gCr6xKGu2mGQ2/GrP3thc=; b=hOoEiqDs+UFrihBmn/qOS91jy1fsYJVbcTmXRDK59hesmywFeno20Mur3ZRMbzXJ7I oQUI9HykvHAaTeCZU56GE1Ftict7FB5SMD9GSpGUt7RzZ/GS27V0Hlq/eD6GoJDPycwA RcQzdJjY0Dc9v9htBRxQy3cLUwWBk0wQPhY9WMPM5Pt+agvzneoFm3e0ts4WaE/Za2bq zojmjZUSZ3VOVC4rxSDYW/b5X9+CnO8U1fGEDT4s6mk/bA++BgTuy8pvE1ux2s1NM4Wj VRrVI5SIEbdeshL0FzD9wAf3/u6UFRcmXOU12cyMuXJ7bJY0GDQ0upRQLbUNua1qOMGN ww/w== X-Gm-Message-State: APjAAAVUWO9Fxrnph1LTPS3yuVc7GRO3pF9MnMklWQfTpEeAYkuZO0e3 K0+q9imy7UwqOKZzcScJcqzJH+2fp6Q= X-Received: by 2002:a63:3203:: with SMTP id y3mr31406523pgy.437.1572891183679; Mon, 04 Nov 2019 10:13:03 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:03 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] coresight: etm4x: Add view comparator settings API to sysfs. Date: Mon, 4 Nov 2019 11:12:47 -0700 Message-Id: <20191104181251.26732-11-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach Currently it is not possible to view the current settings of a given address comparator without knowing what type it is set to. For example, if a comparator is set as an addr_start comparator, attempting to read addr_stop for the same index will result in an error. addr_cmp_view is added to allow the user to see the current settings of the indexed address comparator without resorting to trial and error when the set type is not known. Signed-off-by: Mike Leach Reviewed-by: Leo Yan Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 1cfbddda0b4d..1768e7286a9e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1275,6 +1275,57 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev, } static DEVICE_ATTR_RW(addr_exlevel_s_ns); +static const char * const addr_type_names[] = { + "unused", + "single", + "range", + "start", + "stop" +}; + +static ssize_t addr_cmp_view_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 idx, addr_type; + unsigned long addr_v, addr_v2, addr_ctrl; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + int size = 0; + bool exclude = false; + + spin_lock(&drvdata->spinlock); + idx = config->addr_idx; + addr_v = config->addr_val[idx]; + addr_ctrl = config->addr_acc[idx]; + addr_type = config->addr_type[idx]; + if (addr_type == ETM_ADDR_TYPE_RANGE) { + if (idx & 0x1) { + idx -= 1; + addr_v2 = addr_v; + addr_v = config->addr_val[idx]; + } else { + addr_v2 = config->addr_val[idx + 1]; + } + exclude = config->viiectlr & BIT(idx / 2 + 16); + } + spin_unlock(&drvdata->spinlock); + if (addr_type) { + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx, + addr_type_names[addr_type], addr_v); + if (addr_type == ETM_ADDR_TYPE_RANGE) { + size += scnprintf(buf + size, PAGE_SIZE - size, + " %#lx %s", addr_v2, + exclude ? "exclude" : "include"); + } + size += scnprintf(buf + size, PAGE_SIZE - size, + " ctrl(%#lx)\n", addr_ctrl); + } else { + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx); + } + return size; +} +static DEVICE_ATTR_RO(addr_cmp_view); + static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2120,6 +2171,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_ctxtype.attr, &dev_attr_addr_context.attr, &dev_attr_addr_exlevel_s_ns.attr, + &dev_attr_addr_cmp_view.attr, &dev_attr_vinst_pe_cmp_start_stop.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, From patchwork Mon Nov 4 18:12:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178465 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389580ocf; Mon, 4 Nov 2019 10:13:34 -0800 (PST) X-Google-Smtp-Source: APXvYqzmPKB3JQ/f5YCctqlwNNCxCRFjZJIEhqOeEiyYgtuRfB4i1fIO3kV3+optNNE/rpgEjU19 X-Received: by 2002:a17:906:c9d8:: with SMTP id hk24mr17441169ejb.159.1572891214625; Mon, 04 Nov 2019 10:13:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891214; cv=none; d=google.com; s=arc-20160816; b=M56k5oXvmLGTQF7h64TMAnHr31MZ5+eRYQs+CMFoKPB8lOSm59Nvx0US/WyIu/7Eo7 ITjBd+5jCbKRqh1dTxqwuT4YcCAYPY7ShLTUp3Gcn+WWbTGo07430Jv/dNi9+cij6feY a4L9Bs0bWXRHy0/RJT36cYr6F1kAvlG/m3VwpeoiXxKB92s7u8ua72VYj2G4+0L1rJFy dRZe/Dja43eGl6yje0ACyY6uXl5PJ52o3/KWQl6Q4bbAt3QK6dPWO04iJQwrp/mqw+aK hSTxWDs53YXuFSjbjHndNOWlC84ScnIfonbn4+sLuOnmD87UD8NSzk3SHhMmJKd8NidM zijQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=RUUAX/bpgKOoYdqsMy2RyiY7Jv3TB4H8rCWJgZ2XPlo=; b=ZY4ezjPcl6Qhb8QqUER5mRs5eCOoTmDNMonBwEIumaQmnhEhs6QrBBDWdnEpc2X5cX aRufPM2sbqrxP3EK75k+OKi39XbTX4rPirnIlv+vZ+XNleejWXbWFUHOQyRIXfi4ZRfn wMl1XavqG3xY2+RawViBbIrZYuY/823Q/zazTgTW/+I6ToRaYHTk1nkpGihmjEuSt8U5 aT/7x52QucSJM1LLSOI3eP7gkPna2BFT1OQ6vN53X81OSYcf6l8lDz3WNFSdAlzNI2MG E+4eznSozxs7UfrTfBtuE4tw1mx/UINAIKP296l7Fnw1Z9OzLoIayu8getC+mCP4Vkdy PBDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fzAlnjmV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v20si8362293edc.69.2019.11.04.10.13.34; Mon, 04 Nov 2019 10:13:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fzAlnjmV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729666AbfKDSN3 (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:29 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:36714 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729589AbfKDSNG (ORCPT ); Mon, 4 Nov 2019 13:13:06 -0500 Received: by mail-pf1-f194.google.com with SMTP id v19so12848457pfm.3 for ; Mon, 04 Nov 2019 10:13:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RUUAX/bpgKOoYdqsMy2RyiY7Jv3TB4H8rCWJgZ2XPlo=; b=fzAlnjmVK1lVZ+kMaVRUiNKIXpyjmmer9EJQAHLy3om7kOc//Dw0QjKBlo+Qkuxfz1 9BlvWNnTl5cGV1eiwV72LMhbuYuCLLzzgeVNOKmiWVl0gXN1kBwWYrm9/H2wzt02CBnj FRNHkDp0l/bHlMdgpXySUFc6a/blQzLkpIBsfY9cjfNQm5VrkK4A7yYAzjJj1C4gA0r5 uvd3lDuSnFmyMCqYgl/SYeySyOusNl616qlz2HV+Vqz+OUbiheNDoA+A6BP4vSQ3Du3N +uqK+x6DPCsuU1LcWjmFnSluDXnf3B4n5hecGAXrwJQBepxa4xOqEzrsgs02tmFC/+Nn MCIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RUUAX/bpgKOoYdqsMy2RyiY7Jv3TB4H8rCWJgZ2XPlo=; b=ZftzLcCbUkBDe7sfszAr86jqS1ZxiUC27HSfMqd50XYUxNntZj2YwHjAfx3DjVmi5t KoL8OmPoO2nRIxe/7yXnP3OYwwCuw8SjtmTMzo01EbOKs21Ojve4EoNimWAj9k7s/8q4 sdWdwHfIFJapb31alD0pjt8khMVD0lQ/fDnnG+28DyqUO9ELs8pZ3atsvOq95Qe6bVhL no2sbmTJLxxKfWup40kuVTtc69rzxX5X2yegxx+eTHUmVNqHhqHDaLhY81FrahfpwelD NTezFEZyJeSziE4tYZ+vEF4O5r8UFvdzP1xi449UiBuNhb5pxopcPVwEHGfHGpK2pNMm RAmw== X-Gm-Message-State: APjAAAUMJ5e6T0AF97mHEDzSOM71ndhxX+lrrIljYY5TshPWz+HThpn+ 3EHH687TroZuulRPXz8GW+ZT3Ke/nJU= X-Received: by 2002:a63:b909:: with SMTP id z9mr31246808pge.136.1572891185130; Mon, 04 Nov 2019 10:13:05 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:04 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] coresight: etm4x: Add missing single-shot control API to sysfs Date: Mon, 4 Nov 2019 11:12:48 -0700 Message-Id: <20191104181251.26732-12-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach An API to control single-shot comparator operation was missing from sysfs. This adds the parameters to sysfs to allow programming of this feature. Signed-off-by: Mike Leach Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 122 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 26 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 2 + 3 files changed, 149 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 1768e7286a9e..3fc12ac44270 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev, for (i = 0; i < drvdata->nr_resource; i++) config->res_ctrl[i] = 0x0; + config->ss_idx = 0x0; for (i = 0; i < drvdata->nr_ss_cmp; i++) { config->ss_ctrl[i] = 0x0; config->ss_pe_cmp[i] = 0x0; @@ -1717,6 +1718,123 @@ static ssize_t res_ctrl_store(struct device *dev, } static DEVICE_ATTR_RW(res_ctrl); +static ssize_t sshot_idx_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + val = config->ss_idx; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val >= drvdata->nr_ss_cmp) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + config->ss_idx = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_idx); + +static ssize_t sshot_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_ctrl[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->ss_idx; + config->ss_ctrl[idx] = val & GENMASK(24, 0); + /* must clear bit 31 in related status register on programming */ + config->ss_status[idx] &= ~BIT(31); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_ctrl); + +static ssize_t sshot_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_status[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(sshot_status); + +static ssize_t sshot_pe_ctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + val = config->ss_pe_cmp[config->ss_idx]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t sshot_pe_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u8 idx; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etmv4_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + idx = config->ss_idx; + config->ss_pe_cmp[idx] = val & GENMASK(7, 0); + /* must clear bit 31 in related status register on programming */ + config->ss_status[idx] &= ~BIT(31); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(sshot_pe_ctrl); + static ssize_t ctxid_idx_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2173,6 +2291,10 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_addr_exlevel_s_ns.attr, &dev_attr_addr_cmp_view.attr, &dev_attr_vinst_pe_cmp_start_stop.attr, + &dev_attr_sshot_idx.attr, + &dev_attr_sshot_ctrl.attr, + &dev_attr_sshot_pe_ctrl.attr, + &dev_attr_sshot_status.attr, &dev_attr_seq_idx.attr, &dev_attr_seq_state.attr, &dev_attr_seq_event.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d5148afdbe80..dc3f507e7562 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -168,6 +168,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) drvdata->base + TRCRSCTLRn(i)); for (i = 0; i < drvdata->nr_ss_cmp; i++) { + /* always clear status bit on restart if using single-shot */ + if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) + config->ss_status[i] &= ~BIT(31); writel_relaxed(config->ss_ctrl[i], drvdata->base + TRCSSCCRn(i)); writel_relaxed(config->ss_status[i], @@ -467,6 +470,9 @@ static void etm4_disable_hw(void *info) { u32 control; struct etmv4_drvdata *drvdata = info; + struct etmv4_config *config = &drvdata->config; + struct device *etm_dev = &drvdata->csdev->dev; + int i; CS_UNLOCK(drvdata->base); @@ -489,6 +495,18 @@ static void etm4_disable_hw(void *info) isb(); writel_relaxed(control, drvdata->base + TRCPRGCTLR); + /* wait for TRCSTATR.PMSTABLE to go to '1' */ + if (coresight_timeout(drvdata->base, TRCSTATR, + TRCSTATR_PMSTABLE_BIT, 1)) + dev_err(etm_dev, + "timeout while waiting for PM stable Trace Status\n"); + + /* read the status of the single shot comparators */ + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + config->ss_status[i] = + readl_relaxed(drvdata->base + TRCSSCSRn(i)); + } + coresight_disclaim_device_unlocked(drvdata->base); CS_LOCK(drvdata->base); @@ -595,6 +613,7 @@ static void etm4_init_arch_data(void *info) u32 etmidr4; u32 etmidr5; struct etmv4_drvdata *drvdata = info; + int i; /* Make sure all registers are accessible */ etm4_os_unlock(drvdata); @@ -718,9 +737,14 @@ static void etm4_init_arch_data(void *info) drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1; /* * NUMSSCC, bits[23:20] the number of single-shot - * comparator control for tracing + * comparator control for tracing. Read any status regs as these + * also contain RO capability data. */ drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); + for (i = 0; i < drvdata->nr_ss_cmp; i++) { + drvdata->config.ss_status[i] = + readl_relaxed(drvdata->base + TRCSSCSRn(i)); + } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ drvdata->numcidc = BMVAL(etmidr4, 24, 27); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b873df38e7d8..4a695bf90582 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -227,6 +227,7 @@ * @cntr_val: Sets or returns the value for a counter. * @res_idx: Resource index selector. * @res_ctrl: Controls the selection of the resources in the trace unit. + * @ss_idx: Single-shot index selector. * @ss_ctrl: Controls the corresponding single-shot comparator resource. * @ss_status: The status of the corresponding single-shot comparator. * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. @@ -270,6 +271,7 @@ struct etmv4_config { u32 cntr_val[ETMv4_MAX_CNTR]; u8 res_idx; u32 res_ctrl[ETM_MAX_RES_SEL]; + u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP]; u32 ss_status[ETM_MAX_SS_CMP]; u32 ss_pe_cmp[ETM_MAX_SS_CMP]; From patchwork Mon Nov 4 18:12:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178460 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389269ocf; Mon, 4 Nov 2019 10:13:18 -0800 (PST) X-Google-Smtp-Source: APXvYqyVqqtJImxHYPh2S9pqTvARiASq9EsFhjfV9be9DZ2JRGNwiuUS7jmlJNGBtuLq6RQzUa1z X-Received: by 2002:a17:906:27c5:: with SMTP id k5mr24738727ejc.173.1572891198492; Mon, 04 Nov 2019 10:13:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891198; cv=none; d=google.com; s=arc-20160816; b=vnfNGnHeg0MDOjpNBAkJPE4yTAOKnmMAYL9yAPdTJBB1L4/pD3g/oa9D2A4CXPRJQI FEZ7i0LMmkE5vc//XuuoOTfk5ME9eZmHI6NV3Ty/LvH07sdojaGUt9zrmy2+om083uqZ b6Zt+Qlsh+yu6+h/NZ+GWn1cjYvvGUI8HK5DKwSn+sTgeyZA/SQTE6c5hD49vvQNcBIl 6WGP89morp/r+3kaj2Ml0Jb/WVyGwh/DaA/t8S7Esmlu9sEyTbMO+86bxrW8WQVz6VCs 6WoEo4mnkIZaPmYPAz2ho94P84024uMoO79KEmvJT0bZZ2YNHUjARmHyRPEzuKwAGMzV /vAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=I32GagO5xwpjaCvYA7jwVW7GwjuY4NbR5b26Ld8w57U=; b=tLjD3GsAbAKmLIXcFgfQNxj4WAqrKnCaWSjwLZgXpcm/VQsNGXOsZ5mKvv321hc2pl yWK5Nn7POdspShvVZHdYKjE3L5+T1SOd7KAN0WjeUZdLJqzUc8E+1NvEpV0JnuBY47Qq /GtO81OmgGisplo5jJDajHPx6kQY9HxBRqdoKANFHOUiRx6s8wvRayRWhYCcJ7sURMdB K+80B+cwc5zga5P1+BvEz3k4G+nVn0npTU+uM9dxiJHXBlyj9rTY+MUZ0ZlOpfNNoDM0 B90k5U3AncG8xt5lxTbrWgJ/YQwRxU4E0vljsOywbic8AMJZZMyWmqZa08m4fxi6a33j Kbwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X6kZP/Gv"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u20si3696516ejr.168.2019.11.04.10.13.18; Mon, 04 Nov 2019 10:13:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X6kZP/Gv"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729637AbfKDSNL (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:11 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42523 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729595AbfKDSNH (ORCPT ); Mon, 4 Nov 2019 13:13:07 -0500 Received: by mail-pg1-f195.google.com with SMTP id s23so8479845pgo.9 for ; Mon, 04 Nov 2019 10:13:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I32GagO5xwpjaCvYA7jwVW7GwjuY4NbR5b26Ld8w57U=; b=X6kZP/GvXomxJTpONdRTjc05uKXG60V6KmAFh5sdmFw/KfM+oijNNCl2oUL5CbnjJD bZ7fCXsjov868pGwWXolsD5V2kCStDPw6mIa/4CVypZPHYNENWm6bZ6r9+gu5oFKbMRR BqnsYkoJg6S/ScRTH7LQyZ948THS5mscenYO2Bc7fthtzq+9iHb17I5dcr+4egxIkjAM 8IvalnEp6sE3Eb9ZhupQbObuTPvb59awJR6zpiJ/gDmi/q1nxfMiJvCttciyJpccXbiB 1+OiRYaS+i3nBuhwvhWsOU/IrxT1rBjWGbWxjGEjOvYfbU02a7Y62IYwBlAOfm336zwp GFzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I32GagO5xwpjaCvYA7jwVW7GwjuY4NbR5b26Ld8w57U=; b=grWsw0YfiF8HrbrceA/Vkw01PNNW1cmduGgBQ1BcSuiUQbaRIYwRd0q82peY5T3Vmy BN65gvh3C5EX5F/Cb8QOcNTBp1M/nBJP7XzU2psILLqV0N/wiHmKVkQwtn3FnSYqn2Bd N6UQMmO8Q5fW7uq/7Swjh4of8OdnDAvBqwQWuUwjAuEpvu+zpTCANF4h8byviPwJVa7p XoLo8MRXqmhpQ54gaw+shdGXS9oZVaUQyRHmQCUeSQvoUPCJloCXzbgi8K0sotETMN3M va6yFz6f4pXbLbPODrOGqoRFU8QAz39NUuxUCh2KdnPk9uE9H21VrHMsQgRKEtOyKHGi aomQ== X-Gm-Message-State: APjAAAXvTwHpahVns+t0saPVPBjqNF1qScPOjUaPTDXsc21Ta0Ve9NMB mhw5YGavvjlENlD+EsB70RVlCm6MpSM= X-Received: by 2002:a17:90a:f496:: with SMTP id bx22mr547355pjb.101.1572891186044; Mon, 04 Nov 2019 10:13:06 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:05 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/14] coresight: Add explicit architecture dependency Date: Mon, 4 Nov 2019 11:12:49 -0700 Message-Id: <20191104181251.26732-13-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mark Brown Coresight hardware is only likely to appear on Arm systems and currently the core code has Arm-specific barrier operations in it so can't be built anywhere else so add an explicit dependency saying so. This will make no practical difference currently due to the way subsystems are referenced, the subsystem is only pulled in on arm and arm64, so mainly serves as documentation in case someone wants to increase build coverage. Signed-off-by: Mark Brown Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/Kconfig | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 7a9f5fb08330..6ff30e25af55 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -4,6 +4,7 @@ # menuconfig CORESIGHT bool "CoreSight Tracing Support" + depends on ARM || ARM64 depends on OF || ACPI select ARM_AMBA select PERF_EVENTS From patchwork Mon Nov 4 18:12:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178462 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389435ocf; Mon, 4 Nov 2019 10:13:26 -0800 (PST) X-Google-Smtp-Source: APXvYqz1uOBh+/M+wAoFdrGkluzvhHRVZzxIjot8A7B0zN6jd3487s7mqWbSp22jrL6Yg1ZHxOCs X-Received: by 2002:a50:ac3c:: with SMTP id v57mr30365002edc.300.1572891206587; Mon, 04 Nov 2019 10:13:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891206; cv=none; d=google.com; s=arc-20160816; b=x9HifsXke46vjOXybIbdmyYxNOWDy/UUgNiXgbLgZnVazu93BxU5zhrlJd8wylDtwC A/3irCMZOAiBQznBUvA0tlUUo1GsrVRYSoLiOR7J3iq7vAKkYEjYJ9EnsSXUZOsraUyh vKZu8X3DCgKt9WLWjGXYOH4xFAL8V66uRl2/HejTX/yNnnYDqQAadVQx7ip5vaDlyBc4 mqeHBNitzmD4uGiKZaGWTj0cGpQ8cxJdYe3Lmo/iB2XK9hzalPH8xPr+Ww2KsK3xOVkS RAgGgWEUBpyFJ74vwVeQMVZ32QSXB+257VccsxzGA6J4Gnc40fuh6NjEougRJjNnJOQi uFqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=zNSLQ4yVOGXzKEZuz3+X88N/a9oM0tmHL+W7cfWAqG4=; b=Q0f9z+aylPMOfWpgxP1e5Pi8MIzK5/nK4Ph+Eabx87knvqjEMmLzUb9Sy9Ef+62aST u27rKKPHMIcL10PKnvimczuFleSCJ5e7y60ZeqXnQ3bOA5KTzhXAThWk4XLtlM0s+HAW rRXt334QhgpZvqb18Z9Y0BEuPsZ5sFJPhJYJ4muTegZ5SNPjUWxP3n3fO/N9eger6/qU tRarPhg8tECwv77K9g4oLZqKItuZGk4jLU+uZE60BbZP535Cry/Q6+z1G7WC5x+lAzSY gxmUnpEuzV6qX6lRcW4ChkP4l/DXytaai6m2FoG1s0iv3ZDgMjU+q18f9A5FIlISskrP wpag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U61y0vCE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o14si1259472ejr.14.2019.11.04.10.13.26; Mon, 04 Nov 2019 10:13:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U61y0vCE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729657AbfKDSNW (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:22 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:34668 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729617AbfKDSNK (ORCPT ); Mon, 4 Nov 2019 13:13:10 -0500 Received: by mail-pg1-f195.google.com with SMTP id e4so11881345pgs.1 for ; Mon, 04 Nov 2019 10:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zNSLQ4yVOGXzKEZuz3+X88N/a9oM0tmHL+W7cfWAqG4=; b=U61y0vCEaJMrncMMWKTp6alsvzkXjC9SFPXjSpuTDW5wP2lJ5MWsrgFL0edDG6iB8A 16U73gfEg4PN6OKZfBs2IYB12wQk9ICH/0R/6rLVJhTvUE1wLuQUwtzL0htIZrbkCD/n qKbYEmA5lAbSze1N5pEKHVX2FPwCN+nKZfWN3ZMCWHjt5my8w9wWsjiXWnqoZV0hWCrB +fgtm569leiYQPgNkZTaA81ov8RlBc4jSc82Pr3q71AjyuaOMYlwS4SNEgQxIMHvqIMC 5jncbym3qbVGrIsHRj53O1kEzrwC4S2jnN1icF/c1wyvIKRTKeuoM09MJv+wI8zHWdEi leqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zNSLQ4yVOGXzKEZuz3+X88N/a9oM0tmHL+W7cfWAqG4=; b=gzPHuxCwCvVUfPZ/dxSaBWGgTLqoQGDkvNlXv0g9R7vGRrJbIdRrFR9zcKO7JQTHTu lRE2lii+MeklZNK2FxukXVMRi0VLNPnJ2JJh7YgsAthm35/vMhfq+sHxOaG1+rUPKccj EoV5gqJmJLG/uhfY0WPwlG8uHnhVSHFRiTyCacbg0TSazraOjGBxvt5ZX6LKoOTi836u PagHNmcxeEiJox2o06dlzs6Hi+m0/Q58qXE2BKPacy8YT4PvDqujdV6pMqYlxGrT4p5v DzGO7BaFSHdjlojv/Ioc3XgurCAKrPQbqEYYTadSueXhbi8d3zC0m0zK+4Gu226um1oQ IiLQ== X-Gm-Message-State: APjAAAX27BGK1LHm1hajx3U6xk66T3d1sQlkEZvY9v4zmGRFUe2HAmun itCOWJJ5U2xSxqPm8dqKciP5Tw== X-Received: by 2002:a17:90a:fc8d:: with SMTP id ci13mr610341pjb.6.1572891186945; Mon, 04 Nov 2019 10:13:06 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:06 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] coresight: Serialize enabling/disabling a link device. Date: Mon, 4 Nov 2019 11:12:50 -0700 Message-Id: <20191104181251.26732-14-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yabin Cui When tracing etm data of multiple threads on multiple cpus through perf interface, some link devices are shared between paths of different cpus. It creates race conditions when different cpus wants to enable/disable the same link device at the same time. Example 1: Two cpus want to enable different ports of a coresight funnel, thus calling the funnel enable operation at the same time. But the funnel enable operation isn't reentrantable. Example 2: For an enabled coresight dynamic replicator with refcnt=1, one cpu wants to disable it, while another cpu wants to enable it. Ideally we still have an enabled replicator with refcnt=1 at the end. But in reality the result is uncertain. Since coresight devices claim themselves when enabled for self-hosted usage, the race conditions above usually make the link devices not usable after many cycles. To fix the race conditions, this patch uses spinlocks to serialize enabling/disabling link devices. Fixes: a06ae8609b3d ("coresight: add CoreSight core layer framework") Signed-off-by: Yabin Cui Signed-off-by: Mathieu Poirier Cc: stable # 5.3 --- .../hwtracing/coresight/coresight-funnel.c | 36 +++++++++++---- .../coresight/coresight-replicator.c | 35 ++++++++++++--- .../hwtracing/coresight/coresight-tmc-etf.c | 26 ++++++++--- drivers/hwtracing/coresight/coresight.c | 45 ++++++------------- 4 files changed, 90 insertions(+), 52 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 05f7896c3a01..b605889b507a 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -38,12 +38,14 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @atclk: optional clock for the core parts of the funnel. * @csdev: component vitals needed by the framework. * @priority: port selection order. + * @spinlock: serialize enable/disable operations. */ struct funnel_drvdata { void __iomem *base; struct clk *atclk; struct coresight_device *csdev; unsigned long priority; + spinlock_t spinlock; }; static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) @@ -76,11 +78,21 @@ static int funnel_enable(struct coresight_device *csdev, int inport, { int rc = 0; struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - if (drvdata->base) - rc = dynamic_funnel_enable_hw(drvdata, inport); - + unsigned long flags; + bool first_enable = false; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (atomic_read(&csdev->refcnt[inport]) == 0) { + if (drvdata->base) + rc = dynamic_funnel_enable_hw(drvdata, inport); + if (!rc) + first_enable = true; + } if (!rc) + atomic_inc(&csdev->refcnt[inport]); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + if (first_enable) dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", inport); return rc; } @@ -107,11 +119,19 @@ static void funnel_disable(struct coresight_device *csdev, int inport, int outport) { struct funnel_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + bool last_disable = false; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (atomic_dec_return(&csdev->refcnt[inport]) == 0) { + if (drvdata->base) + dynamic_funnel_disable_hw(drvdata, inport); + last_disable = true; + } + spin_unlock_irqrestore(&drvdata->spinlock, flags); - if (drvdata->base) - dynamic_funnel_disable_hw(drvdata, inport); - - dev_dbg(&csdev->dev, "FUNNEL inport %d disabled\n", inport); + if (last_disable) + dev_dbg(&csdev->dev, "FUNNEL inport %d disabled\n", inport); } static const struct coresight_ops_link funnel_link_ops = { diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index b29ba640eb25..43304196a1a6 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -31,11 +31,13 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * whether this one is programmable or not. * @atclk: optional clock for the core parts of the replicator. * @csdev: component vitals needed by the framework + * @spinlock: serialize enable/disable operations. */ struct replicator_drvdata { void __iomem *base; struct clk *atclk; struct coresight_device *csdev; + spinlock_t spinlock; }; static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) @@ -97,10 +99,22 @@ static int replicator_enable(struct coresight_device *csdev, int inport, { int rc = 0; struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - if (drvdata->base) - rc = dynamic_replicator_enable(drvdata, inport, outport); + unsigned long flags; + bool first_enable = false; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (atomic_read(&csdev->refcnt[outport]) == 0) { + if (drvdata->base) + rc = dynamic_replicator_enable(drvdata, inport, + outport); + if (!rc) + first_enable = true; + } if (!rc) + atomic_inc(&csdev->refcnt[outport]); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + if (first_enable) dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); return rc; } @@ -137,10 +151,19 @@ static void replicator_disable(struct coresight_device *csdev, int inport, int outport) { struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + bool last_disable = false; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (atomic_dec_return(&csdev->refcnt[outport]) == 0) { + if (drvdata->base) + dynamic_replicator_disable(drvdata, inport, outport); + last_disable = true; + } + spin_unlock_irqrestore(&drvdata->spinlock, flags); - if (drvdata->base) - dynamic_replicator_disable(drvdata, inport, outport); - dev_dbg(&csdev->dev, "REPLICATOR disabled\n"); + if (last_disable) + dev_dbg(&csdev->dev, "REPLICATOR disabled\n"); } static const struct coresight_ops_link replicator_link_ops = { diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 807416b75ecc..d0cc3985b72a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -334,9 +334,10 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) static int tmc_enable_etf_link(struct coresight_device *csdev, int inport, int outport) { - int ret; + int ret = 0; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + bool first_enable = false; spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { @@ -344,12 +345,18 @@ static int tmc_enable_etf_link(struct coresight_device *csdev, return -EBUSY; } - ret = tmc_etf_enable_hw(drvdata); + if (atomic_read(&csdev->refcnt[0]) == 0) { + ret = tmc_etf_enable_hw(drvdata); + if (!ret) { + drvdata->mode = CS_MODE_SYSFS; + first_enable = true; + } + } if (!ret) - drvdata->mode = CS_MODE_SYSFS; + atomic_inc(&csdev->refcnt[0]); spin_unlock_irqrestore(&drvdata->spinlock, flags); - if (!ret) + if (first_enable) dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); return ret; } @@ -359,6 +366,7 @@ static void tmc_disable_etf_link(struct coresight_device *csdev, { unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + bool last_disable = false; spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { @@ -366,11 +374,15 @@ static void tmc_disable_etf_link(struct coresight_device *csdev, return; } - tmc_etf_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; + if (atomic_dec_return(&csdev->refcnt[0]) == 0) { + tmc_etf_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; + last_disable = true; + } spin_unlock_irqrestore(&drvdata->spinlock, flags); - dev_dbg(&csdev->dev, "TMC-ETF disabled\n"); + if (last_disable) + dev_dbg(&csdev->dev, "TMC-ETF disabled\n"); } static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index e6ca899fea4e..ef20f74c85fa 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -253,9 +253,9 @@ static int coresight_enable_link(struct coresight_device *csdev, struct coresight_device *parent, struct coresight_device *child) { - int ret; + int ret = 0; int link_subtype; - int refport, inport, outport; + int inport, outport; if (!parent || !child) return -EINVAL; @@ -264,29 +264,17 @@ static int coresight_enable_link(struct coresight_device *csdev, outport = coresight_find_link_outport(csdev, child); link_subtype = csdev->subtype.link_subtype; - if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) - refport = inport; - else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT) - refport = outport; - else - refport = 0; - - if (refport < 0) - return refport; + if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG && inport < 0) + return inport; + if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && outport < 0) + return outport; - if (atomic_inc_return(&csdev->refcnt[refport]) == 1) { - if (link_ops(csdev)->enable) { - ret = link_ops(csdev)->enable(csdev, inport, outport); - if (ret) { - atomic_dec(&csdev->refcnt[refport]); - return ret; - } - } - } - - csdev->enable = true; + if (link_ops(csdev)->enable) + ret = link_ops(csdev)->enable(csdev, inport, outport); + if (!ret) + csdev->enable = true; - return 0; + return ret; } static void coresight_disable_link(struct coresight_device *csdev, @@ -295,7 +283,7 @@ static void coresight_disable_link(struct coresight_device *csdev, { int i, nr_conns; int link_subtype; - int refport, inport, outport; + int inport, outport; if (!parent || !child) return; @@ -305,20 +293,15 @@ static void coresight_disable_link(struct coresight_device *csdev, link_subtype = csdev->subtype.link_subtype; if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_MERG) { - refport = inport; nr_conns = csdev->pdata->nr_inport; } else if (link_subtype == CORESIGHT_DEV_SUBTYPE_LINK_SPLIT) { - refport = outport; nr_conns = csdev->pdata->nr_outport; } else { - refport = 0; nr_conns = 1; } - if (atomic_dec_return(&csdev->refcnt[refport]) == 0) { - if (link_ops(csdev)->disable) - link_ops(csdev)->disable(csdev, inport, outport); - } + if (link_ops(csdev)->disable) + link_ops(csdev)->disable(csdev, inport, outport); for (i = 0; i < nr_conns; i++) if (atomic_read(&csdev->refcnt[i]) != 0) From patchwork Mon Nov 4 18:12:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 178459 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp4389265ocf; Mon, 4 Nov 2019 10:13:18 -0800 (PST) X-Google-Smtp-Source: APXvYqx2Vk/jO2u8j5ZC38yg7WkMHs1+hecbaDau+q38ci6cf2xWGpQ6qfhU6dy1/VtFV22wVqBO X-Received: by 2002:a17:906:2584:: with SMTP id m4mr25838262ejb.287.1572891198097; Mon, 04 Nov 2019 10:13:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1572891198; cv=none; d=google.com; s=arc-20160816; b=cBFAJYCYOBvLNnLlqVGzGYyV3kIhcWQwUBj8rlfmxUMylyrByFU4uHp9nfKpu76o+8 Wxu6VI/KKWy4ZdB8Su/yxsUvaqvjVAPYa5lZBIvXLw4SMR2iihyRKhnoddNqG1JZJ+at 9ZvsCA3dUzx1yoz41iJ0QNdVSJMz1queojTkm/P1cyVfdv8Ig5+tcqiAohgJaYSmeruq mKNFwu4rFxQsNYLaODcpU8LkviwNCs4UMScD2GYTQH15WxKx3+/W0pXbodSzJc8/SL99 kmlAwWiFa0g2lxL7cQxvn2zhywC2hF8AAto+JMUKArPWrjHEgyPt7mGiZfzvdMy+UX1I mzrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=1T5qb1N1RGdNwfpZMS1nmW4JbJwNZQr2qiFyXV+vsXI=; b=m//cDWjUY5Wa9xUzHCwZbREI9WECOAneL5lzITQyooTnMLNVDlgUCcryTAKU2DNPM+ LKzcBBtTOtg7sOB6zaN+Xzm3NKoTL1XAeb94S+kDGySoDMJlpKCBrg0toQl2r0/9xEay JBx9wm3+jpTkLzw2C2Nc69rgZImdvVBdsCkdyeFVmnaQ2zjahAm0UpBB4rX0qmJ+96y3 MOrbh1ctytMqUIFF9Eb9uhVqQol92+e0NoNJr5chz3I7SSKJOYnizy+a7MXioQU7N/4h PLp2sLQKZrPR/+SQlDloAI36mT4hBQLo+w3Ayaeo9Svq2BSVPZnFDXsxpwh5eVxjRbXk s0Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rTRqo8+L; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u20si3696516ejr.168.2019.11.04.10.13.17; Mon, 04 Nov 2019 10:13:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rTRqo8+L; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729648AbfKDSNN (ORCPT + 26 others); Mon, 4 Nov 2019 13:13:13 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:46334 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729575AbfKDSNK (ORCPT ); Mon, 4 Nov 2019 13:13:10 -0500 Received: by mail-pf1-f195.google.com with SMTP id 193so11542993pfc.13 for ; Mon, 04 Nov 2019 10:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1T5qb1N1RGdNwfpZMS1nmW4JbJwNZQr2qiFyXV+vsXI=; b=rTRqo8+L54opQw9nOOIGSx7QK90W2+ZzHTPDMmxn1hbCSkcZuUL/6fkN+CfvtBKTdZ FQyvs5/addpNUheJk5F/Z7kqcvFW/X/4tEeWTflKsewuuK807msXk2yu5EH/mvLFcn8C LwwuwkuAW+DuwfVXerxkf7yv5czpA/VeEQv32eOSsUWvEShW1Ybkhi2zgRLzDd8zw7tP pSqjxj5VrqKF6AG548xdbuEneE6ki/9iCegyLDgHa/LySbv9FCZWD8BK28HoIAoEiAwY d/q6VWHJNPoL3Sj57PjR8LP8rVb4u90xDO2AC9rM93tw7BEO1mg8GLDusfk05LghjoZF cx8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1T5qb1N1RGdNwfpZMS1nmW4JbJwNZQr2qiFyXV+vsXI=; b=EEGMkYB3XoEPsWVvjO/snoKoQeiuDAZZLQPlg+wdWw/VQGmXTps1uJdqlhyu5vTgZ7 p36WhxTkUIlV5ptwMIrggpzlicwTePHb6EmcvyM6bYkOHkGs/0zhQIEkIcr1jScLQ0VG tjyjH6qxGYmpyQt/lTgz+wd2a8l2ewu7uo+eutFar6Ke5XfOL8B087rIj1Eo4EsnOy9w sHMwDK4+rdyopUvH0t5q16M4EAVCSyvzcztCbWka89hcttgbggPqhj6y8C+7i5sQmNgD PGXeM5cVc589NJyR3ngZgGcqSlPkJPPKPg5q6eg11QMpt0XVPxC0kJE0PRXZniqjMhHj ONqA== X-Gm-Message-State: APjAAAV6CSqdWqSqTE+ISEfOUhnUUZ2XbTdxVjqFuEDRW7bQG0ucDV2e IsGCe5Aa5rCXbQkSXPpjb6mP6A== X-Received: by 2002:a17:90a:86c1:: with SMTP id y1mr565934pjv.71.1572891187654; Mon, 04 Nov 2019 10:13:07 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id o12sm16149520pgl.86.2019.11.04.10.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2019 10:13:07 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/14] coresight: etm4x: Fix BMVAL misuse Date: Mon, 4 Nov 2019 11:12:51 -0700 Message-Id: <20191104181251.26732-15-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104181251.26732-1-mathieu.poirier@linaro.org> References: <20191104181251.26732-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rikard Falkeborn The second argument should be the lsb and the third argument should be the msb. Signed-off-by: Rikard Falkeborn Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 3fc12ac44270..ce41482431f9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1246,7 +1246,7 @@ static ssize_t addr_exlevel_s_ns_show(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->addr_idx; - val = BMVAL(config->addr_acc[idx], 14, 8); + val = BMVAL(config->addr_acc[idx], 8, 14); spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); }