From patchwork Thu Jul 18 06:13:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 813642 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127CF55E58 for ; Thu, 18 Jul 2024 06:14:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721283257; cv=none; b=uruDnrC4Z9uw6mjfy+lx4lgrkyyO/FX0ykQMyEbUZ7JS9Gb3HNYG3AB7UlAap0vM5KZbaS44SSzFCnl/ciqYKh/kz25Uyz0CkmwthBqRcglGoxRKAPSP5nYZKAqov9sZQIARJtykb2naAXSlZ2f84oFm08qWWQBfVk6+PXZugQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721283257; c=relaxed/simple; bh=AMLabTprOE+b/0Mf4f8+EuiTx0x4CHg+uCxUzrAs0js=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lfLem/koPgfYrjmn5gQ23haLxRoClyYYXF3XIYiNIkLTg99HxYXpnv0AU5wllOLGyINkN+yF/1zwLU/E60Sctqx7/RjMOgPc3pJnAZB7LOh6FqwCkYxGksBVL+s3UrrqllTsnNrIYWu6FDGCpuLsL02hG31HcZWjdhRtsESCQoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GBhPF+CU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GBhPF+CU" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46I6Ar9a003865; Thu, 18 Jul 2024 06:14:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= WKrj9HrdsIhFLgUAL4hpIqspup4DkR1b1EGnkz8RQvY=; b=GBhPF+CUa/CCmlVs 1F52jNVZH9C7kntDVwErcENa9gf2ybjrXmxLO/Pb73oVl5a6zZUN6IBdq6AkFXXS iBtkTzDNTkEnDJL+RTCLy4gLDJDTqXbbXGAQ8NOtcuR1L+UtIhxr5lbWALbfAgzr uMtjUG33ZgLAcljTzIQV5mWQIbrFOm94WKzkyll0+DiFrjRdHXBI0kwrK7SOVdAL XsABz1soB67l1O8uvatEf0VGE37Fx8s8oj7en6ZgQd+ryWSWkOzzSyvf2LspjdeL yeGWJQmNWS+TMxG8L2q0tp1WC/96zrtNZV+TuZgDVns6QKJIc9ZeALgvkHheB2lN KUxGyA== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 40dwfpcjg7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2024 06:14:06 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46I6E5Vk017496 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2024 06:14:05 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:14:03 -0700 From: Gokul Sriram Palanisamy To: , , CC: , , Subject: [PATCH 1/6] drivers: bus: mhi: Added shared-dma-pool support for mhi_dev Date: Thu, 18 Jul 2024 11:43:39 +0530 Message-ID: <20240718061344.575653-2-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718061344.575653-1-quic_gokulsri@quicinc.com> References: <20240718061344.575653-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 02IdnW0nXZmBCMTaw1gIX3xqNXhg2Hux X-Proofpoint-GUID: 02IdnW0nXZmBCMTaw1gIX3xqNXhg2Hux X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 spamscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180040 When using default memory for coherent memory allocation without reservation, memory gets fragmented after several mhi register/unregister cycles and no coherent reservation was possible. Client driver registering MHI shall reserve a dedicated region as shared-dma-pool for mhi to help avoid this situation. On boards which doesn't reserve this memory, it will continue to allocate memory from default memory. DMA pool is reserved for coherent allocations of size SZ_512K (mhi_cntrl->seg_len) to avoid fragmentation and always ensure allocations of SZ_512K succeeds. Allocations of lower order from the reserved memory would lead to fragmentation on multiple alloc/frees. So use dma_alloc_coherent from mhi_cntrl->cntrl_dev for allocations lower than mhi_cntrl->seg_len. If coherent pool is not reserved, all reservations go through mhi_cntrl->cntrl_dev. Co-developed-by: Vignesh Viswanathan Signed-off-by: Vignesh Viswanathan Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/host/boot.c | 19 ++++++------ drivers/bus/mhi/host/init.c | 51 +++++++++++++++++++++++++++++++++ drivers/bus/mhi/host/internal.h | 26 +++++++++++++++++ include/linux/mhi.h | 5 ++++ 4 files changed, 91 insertions(+), 10 deletions(-) diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c index dedd29ca8db3..ca842facf820 100644 --- a/drivers/bus/mhi/host/boot.c +++ b/drivers/bus/mhi/host/boot.c @@ -303,8 +303,8 @@ void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, struct mhi_buf *mhi_buf = image_info->mhi_buf; for (i = 0; i < image_info->entries; i++, mhi_buf++) - dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len, - mhi_buf->buf, mhi_buf->dma_addr); + mhi_fw_free_coherent(mhi_cntrl, mhi_buf->len, + mhi_buf->buf, mhi_buf->dma_addr); kfree(image_info->mhi_buf); kfree(image_info); @@ -340,9 +340,9 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, vec_size = sizeof(struct bhi_vec_entry) * i; mhi_buf->len = vec_size; - mhi_buf->buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, - vec_size, &mhi_buf->dma_addr, - GFP_KERNEL); + mhi_buf->buf = mhi_fw_alloc_coherent(mhi_cntrl, vec_size, + &mhi_buf->dma_addr, + GFP_KERNEL); if (!mhi_buf->buf) goto error_alloc_segment; } @@ -355,8 +355,8 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, error_alloc_segment: for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) - dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len, - mhi_buf->buf, mhi_buf->dma_addr); + mhi_fw_free_coherent(mhi_cntrl, mhi_buf->len, + mhi_buf->buf, mhi_buf->dma_addr); error_alloc_mhi_buf: kfree(img_info); @@ -452,8 +452,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) fw_sz = firmware->size; skip_req_fw: - buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, size, &dma_addr, - GFP_KERNEL); + buf = mhi_fw_alloc_coherent(mhi_cntrl, size, &dma_addr, GFP_KERNEL); if (!buf) { release_firmware(firmware); goto error_fw_load; @@ -462,7 +461,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) /* Download image using BHI */ memcpy(buf, fw_data, size); ret = mhi_fw_load_bhi(mhi_cntrl, dma_addr, size); - dma_free_coherent(mhi_cntrl->cntrl_dev, size, buf, dma_addr); + mhi_fw_free_coherent(mhi_cntrl, size, buf, dma_addr); /* Error or in EDL mode, we're done */ if (ret) { diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index ce7d2e62c2f1..c1e1412c43e2 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -8,9 +8,12 @@ #include #include #include +#include #include #include #include +#include +#include #include #include #include @@ -929,6 +932,51 @@ static int parse_config(struct mhi_controller *mhi_cntrl, return ret; } +static void mhi_init_fw_coherent_memory(struct mhi_controller *mhi_cntrl, + struct mhi_device *mhi_dev) +{ + struct reserved_mem *mhi_rmem = NULL; + struct device *dev = &mhi_dev->dev; + struct device_node *cma_node = mhi_cntrl->cma_node; + int ret; + + dev->coherent_dma_mask = mhi_cntrl->cntrl_dev->coherent_dma_mask; + + if (!cma_node) { + dev_err(mhi_cntrl->cntrl_dev, "mhi coherent pool is not reserved"); + return; + } + + mhi_rmem = of_reserved_mem_lookup(cma_node); + of_node_put(cma_node); + + if (!mhi_rmem) { + dev_err(mhi_cntrl->cntrl_dev, "Failed to get DMA reserved memory"); + return; + } + + mhi_cntrl->cma_base = mhi_rmem->base; + mhi_cntrl->cma_size = mhi_rmem->size; + + ret = dma_declare_coherent_memory(dev, mhi_cntrl->cma_base, + mhi_cntrl->cma_base, + mhi_cntrl->cma_size); + if (ret) + dev_err(mhi_cntrl->cntrl_dev, "Failed to declare dma coherent memory"); + else + dev_info(mhi_cntrl->cntrl_dev, "DMA Memory initialized at %pa, size %ld MiB", + &mhi_cntrl->cma_base, + (unsigned long)mhi_cntrl->cma_size / SZ_1M); +} + +static void mhi_deinit_fw_coherent_memory(struct mhi_controller *mhi_cntrl) +{ + struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev; + + dma_release_coherent_memory(&mhi_dev->dev); + mhi_dev->dev.dma_mem = NULL; +} + int mhi_register_controller(struct mhi_controller *mhi_cntrl, const struct mhi_controller_config *config) { @@ -1028,6 +1076,7 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, goto error_setup_irq; } + mhi_init_fw_coherent_memory(mhi_cntrl, mhi_dev); mhi_dev->dev_type = MHI_DEVICE_CONTROLLER; mhi_dev->mhi_cntrl = mhi_cntrl; dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index); @@ -1053,6 +1102,7 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, return 0; err_release_dev: + mhi_deinit_fw_coherent_memory(mhi_cntrl); put_device(&mhi_dev->dev); error_setup_irq: mhi_deinit_free_irq(mhi_cntrl); @@ -1095,6 +1145,7 @@ void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) } vfree(mhi_cntrl->mhi_chan); + mhi_deinit_fw_coherent_memory(mhi_cntrl); device_del(&mhi_dev->dev); put_device(&mhi_dev->dev); diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/internal.h index aaad40a07f69..41ce100d87d2 100644 --- a/drivers/bus/mhi/host/internal.h +++ b/drivers/bus/mhi/host/internal.h @@ -396,6 +396,32 @@ void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan); +static inline void *mhi_fw_alloc_coherent(struct mhi_controller *mhi_cntrl, + size_t size, dma_addr_t *dma_handle, + gfp_t gfp) +{ + if (size < mhi_cntrl->seg_len || !mhi_cntrl->cma_base) { + return dma_alloc_coherent(mhi_cntrl->cntrl_dev, + size, dma_handle, gfp); + } else { + return dma_alloc_coherent(&mhi_cntrl->mhi_dev->dev, + size, dma_handle, gfp); + } +} + +static inline void mhi_fw_free_coherent(struct mhi_controller *mhi_cntrl, + size_t size, void *vaddr, + dma_addr_t dma_handle) +{ + if (size < mhi_cntrl->seg_len || !mhi_cntrl->cma_base) { + dma_free_coherent(mhi_cntrl->cntrl_dev, size, vaddr, + dma_handle); + } else { + dma_free_coherent(&mhi_cntrl->mhi_dev->dev, size, vaddr, + dma_handle); + } +} + /* Event processing methods */ void mhi_ctrl_ev_task(unsigned long data); void mhi_ev_task(unsigned long data); diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 059dc94d20bb..c788c12039b5 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -362,6 +362,8 @@ struct mhi_controller_config { * @wake_set: Device wakeup set flag * @irq_flags: irq flags passed to request_irq (optional) * @mru: the default MRU for the MHI device + * @cma_base: Base address of the cohernet memory pool reserved + * @cma_size: Size of the cohernel memory pool reserved * * Fields marked as (required) need to be populated by the controller driver * before calling mhi_register_controller(). For the fields marked as (optional) @@ -447,6 +449,9 @@ struct mhi_controller { bool wake_set; unsigned long irq_flags; u32 mru; + struct device_node *cma_node; + phys_addr_t cma_base; + size_t cma_size; }; /** From patchwork Thu Jul 18 06:13:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 813641 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D42B257CB4 for ; Thu, 18 Jul 2024 06:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721283260; cv=none; b=bxYori4oRRx8eL+5buSuT6Ta3URUZCt5WbaFX4+8MMXUmo8CqGM0UlCDnadL+oRQLrfpPFqVJTCYnafP1G7X5g1wH5p+ENHm+ONd+2kPBo9x2zN7b6SmVPKmywYUGLQ2hzNKb2CCokZ57v4dumqToAPJGLWO/HZ83xsFgZcky0g= ARC-Message-Signature: i=1; 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Thu, 18 Jul 2024 06:14:08 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:14:05 -0700 From: Gokul Sriram Palanisamy To: , , CC: , , Subject: [PATCH 2/6] bus: mhi: add support to allocate rddm memory during crash time Date: Thu, 18 Jul 2024 11:43:40 +0530 Message-ID: <20240718061344.575653-3-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718061344.575653-1-quic_gokulsri@quicinc.com> References: <20240718061344.575653-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5fbezZwkYwd5iMAqMWg-pIQiXPlLDRN0 X-Proofpoint-ORIG-GUID: 5fbezZwkYwd5iMAqMWg-pIQiXPlLDRN0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 mlxscore=0 bulkscore=0 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180040 From: Ram Kumar D Currently, MHI bus pre-allocates the RDDM buffer for crash dump collection during MHI power up. To avoid carving out memory for RDDM buffers even if it is unutilized, add support to allocate memory at runtime during the RDDM download after target crash. This feature can be controlled by the client driver registering the MHI controller by setting the rddm_prealloc flag to false in mhi_cntrl. By default rddm_prealloc is true, retaining the existing behaviour. By default, rddm_seg_len will be same as seg_len. The client driver can override the mhi_cntrl->rddm_seg_len. Signed-off-by: Ram Kumar D Co-developed-by: Vignesh Viswanathan Signed-off-by: Vignesh Viswanathan Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/host/boot.c | 149 +++++++++++++++++++++++++++----- drivers/bus/mhi/host/init.c | 19 ++-- drivers/bus/mhi/host/internal.h | 11 ++- drivers/bus/mhi/host/main.c | 4 +- drivers/bus/mhi/host/pm.c | 2 +- include/linux/mhi.h | 2 + 6 files changed, 156 insertions(+), 31 deletions(-) diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c index ca842facf820..1a918e340424 100644 --- a/drivers/bus/mhi/host/boot.c +++ b/drivers/bus/mhi/host/boot.c @@ -35,6 +35,16 @@ int mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, bhi_vec->size = mhi_buf->len; } + if (!mhi_cntrl->rddm_prealloc) { + mhi_buf->dma_addr = dma_map_single(mhi_cntrl->cntrl_dev, + mhi_buf->buf, mhi_buf->len, + DMA_TO_DEVICE); + if (dma_mapping_error(mhi_cntrl->cntrl_dev, mhi_buf->dma_addr)) { + dev_err(dev, "dma mapping failed\n"); + return -ENOMEM; + } + } + dev_dbg(dev, "BHIe programming for RDDM\n"); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS, @@ -158,10 +168,35 @@ int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic) { void __iomem *base = mhi_cntrl->bhie; struct device *dev = &mhi_cntrl->mhi_dev->dev; + struct mhi_buf *mhi_buf = NULL; u32 rx_status; + int ret; - if (in_panic) - return __mhi_download_rddm_in_panic(mhi_cntrl); + /* + * Allocate RDDM table if specified, this table is for debugging purpose + */ + if (!mhi_cntrl->rddm_prealloc && mhi_cntrl->rddm_size) { + ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, + mhi_cntrl->rddm_size, IMG_TYPE_RDDM); + if (ret) { + dev_err(dev, "Failed to allocate RDDM table memory\n"); + return ret; + } + + /* setup the RX vector table */ + ret = mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image); + if (ret) { + dev_err(dev, "Failed to prepare RDDM\n"); + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image, + IMG_TYPE_RDDM); + return ret; + } + } + + if (in_panic) { + ret = __mhi_download_rddm_in_panic(mhi_cntrl); + goto out; + } dev_dbg(dev, "Waiting for RDDM image download via BHIe\n"); @@ -173,7 +208,16 @@ int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic) &rx_status) || rx_status, msecs_to_jiffies(mhi_cntrl->timeout_ms)); - return (rx_status == BHIE_RXVECSTATUS_STATUS_XFER_COMPL) ? 0 : -EIO; + ret = (rx_status == BHIE_RXVECSTATUS_STATUS_XFER_COMPL) ? 0 : -EIO; + +out: + mhi_buf = &mhi_cntrl->rddm_image->mhi_buf[mhi_cntrl->rddm_image->entries - 1]; + + if (!mhi_cntrl->rddm_prealloc) + dma_unmap_single(mhi_cntrl->cntrl_dev, mhi_buf->dma_addr, + mhi_buf->len, DMA_TO_DEVICE); + + return ret; } EXPORT_SYMBOL_GPL(mhi_download_rddm_image); @@ -297,14 +341,25 @@ static int mhi_fw_load_bhi(struct mhi_controller *mhi_cntrl, } void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, - struct image_info *image_info) + struct image_info *image_info, + enum image_type img_type) { int i; struct mhi_buf *mhi_buf = image_info->mhi_buf; - for (i = 0; i < image_info->entries; i++, mhi_buf++) - mhi_fw_free_coherent(mhi_cntrl, mhi_buf->len, - mhi_buf->buf, mhi_buf->dma_addr); + for (i = 0; i < image_info->entries; i++, mhi_buf++) { + if (img_type == IMG_TYPE_RDDM && !mhi_cntrl->rddm_prealloc) { + if (i == (image_info->entries - 1)) + dma_unmap_single(mhi_cntrl->cntrl_dev, + mhi_buf->dma_addr, + mhi_buf->len, + DMA_FROM_DEVICE); + kfree(mhi_buf->buf); + } else { + mhi_fw_free_coherent(mhi_cntrl, mhi_buf->len, + mhi_buf->buf, mhi_buf->dma_addr); + } + } kfree(image_info->mhi_buf); kfree(image_info); @@ -312,21 +367,31 @@ void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, struct image_info **image_info, - size_t alloc_size) + size_t alloc_size, enum image_type img_type) { size_t seg_size = mhi_cntrl->seg_len; - int segments = DIV_ROUND_UP(alloc_size, seg_size) + 1; + int segments; int i; struct image_info *img_info; struct mhi_buf *mhi_buf; + /* Masked __GFP_DIRECT_RECLAIM flag for non-interrupt context + * to avoid rcu context sleep issue in kmalloc during kernel panic + */ + gfp_t gfp = (in_interrupt() ? GFP_ATOMIC : + ((GFP_KERNEL | __GFP_NORETRY) & ~__GFP_DIRECT_RECLAIM)); + + if (img_type == IMG_TYPE_RDDM) + seg_size = mhi_cntrl->rddm_seg_len; - img_info = kzalloc(sizeof(*img_info), GFP_KERNEL); + segments = DIV_ROUND_UP(alloc_size, seg_size) + 1; + + img_info = kzalloc(sizeof(*img_info), gfp); if (!img_info) return -ENOMEM; /* Allocate memory for entries */ img_info->mhi_buf = kcalloc(segments, sizeof(*img_info->mhi_buf), - GFP_KERNEL); + gfp); if (!img_info->mhi_buf) goto error_alloc_mhi_buf; @@ -340,11 +405,42 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, vec_size = sizeof(struct bhi_vec_entry) * i; mhi_buf->len = vec_size; - mhi_buf->buf = mhi_fw_alloc_coherent(mhi_cntrl, vec_size, - &mhi_buf->dma_addr, - GFP_KERNEL); - if (!mhi_buf->buf) - goto error_alloc_segment; + + if (img_type == IMG_TYPE_RDDM && !mhi_cntrl->rddm_prealloc) { + /* Vector table is the last entry */ + if (i == segments - 1) { + mhi_buf->buf = kzalloc(PAGE_ALIGN(vec_size), + gfp); + if (!mhi_buf->buf) + goto error_alloc_segment; + + /* Vector table entry will be dma_mapped during + * rddm prepare with DMA_TO_DEVICE and unmapped + * once the target completes the RDDM XFER. + */ + continue; + } + mhi_buf->buf = kmalloc(vec_size, gfp); + if (!mhi_buf->buf) + goto error_alloc_segment; + + mhi_buf->dma_addr = dma_map_single(mhi_cntrl->cntrl_dev, + mhi_buf->buf, + vec_size, + DMA_FROM_DEVICE); + if (dma_mapping_error(mhi_cntrl->cntrl_dev, + mhi_buf->dma_addr)) { + kfree(mhi_buf->buf); + goto error_alloc_segment; + } + } else { + mhi_buf->buf = mhi_fw_alloc_coherent(mhi_cntrl, + vec_size, + &mhi_buf->dma_addr, + GFP_KERNEL); + if (!mhi_buf->buf) + goto error_alloc_segment; + } } img_info->bhi_vec = img_info->mhi_buf[segments - 1].buf; @@ -354,9 +450,18 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, return 0; error_alloc_segment: - for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) - mhi_fw_free_coherent(mhi_cntrl, mhi_buf->len, - mhi_buf->buf, mhi_buf->dma_addr); + for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) { + if (img_type == IMG_TYPE_RDDM && !mhi_cntrl->rddm_prealloc) { + dma_unmap_single(mhi_cntrl->cntrl_dev, + mhi_buf->dma_addr, mhi_buf->len, + DMA_FROM_DEVICE); + kfree(mhi_buf->buf); + + } else { + mhi_fw_free_coherent(mhi_cntrl, mhi_buf->len, + mhi_buf->buf, mhi_buf->dma_addr); + } + } error_alloc_mhi_buf: kfree(img_info); @@ -485,7 +590,8 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) * device transitioning into MHI READY state */ if (mhi_cntrl->fbc_download) { - ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image, fw_sz); + ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image, fw_sz, + IMG_TYPE_FBC); if (ret) { release_firmware(firmware); goto error_fw_load; @@ -510,7 +616,8 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) error_ready_state: if (mhi_cntrl->fbc_download) { - mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image, + IMG_TYPE_FBC); mhi_cntrl->fbc_image = NULL; } diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index c1e1412c43e2..8a47c3354560 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -1058,6 +1058,9 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, mhi_cntrl->unmap_single = mhi_unmap_single_no_bb; } + mhi_cntrl->rddm_prealloc = true; + mhi_cntrl->rddm_seg_len = mhi_cntrl->seg_len; + mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL); if (mhi_cntrl->index < 0) { ret = mhi_cntrl->index; @@ -1224,14 +1227,18 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) /* * Allocate RDDM table for debugging purpose if specified */ - mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, - mhi_cntrl->rddm_size); + if (mhi_cntrl->rddm_prealloc) + mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, + mhi_cntrl->rddm_size, + IMG_TYPE_RDDM); + if (mhi_cntrl->rddm_image) { ret = mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image); if (ret) { mhi_free_bhie_table(mhi_cntrl, - mhi_cntrl->rddm_image); + mhi_cntrl->rddm_image, + IMG_TYPE_RDDM); goto error_reg_offset; } } @@ -1254,12 +1261,14 @@ EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up); void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl) { if (mhi_cntrl->fbc_image) { - mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image, + IMG_TYPE_FBC); mhi_cntrl->fbc_image = NULL; } if (mhi_cntrl->rddm_image) { - mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image, + IMG_TYPE_RDDM); mhi_cntrl->rddm_image = NULL; } diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/internal.h index 41ce100d87d2..c7946f81be38 100644 --- a/drivers/bus/mhi/host/internal.h +++ b/drivers/bus/mhi/host/internal.h @@ -176,6 +176,11 @@ enum mhi_er_type { MHI_ER_TYPE_VALID = 0x1, }; +enum image_type { + IMG_TYPE_FBC, + IMG_TYPE_RDDM, +}; + struct db_cfg { bool reset_req; bool db_mode; @@ -314,9 +319,11 @@ int mhi_destroy_device(struct device *dev, void *data); void mhi_create_devices(struct mhi_controller *mhi_cntrl); int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, - struct image_info **image_info, size_t alloc_size); + struct image_info **image_info, size_t alloc_size, + enum image_type img_type); void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, - struct image_info *image_info); + struct image_info *image_info, + enum image_type img_type); /* Power management APIs */ enum mhi_pm_state __must_check mhi_tryset_pm_state( diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 4de75674f193..2f44f11fa5a6 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -503,13 +503,13 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv) } write_unlock_irq(&mhi_cntrl->pm_lock); - if (pm_state != MHI_PM_SYS_ERR_DETECT) + if (pm_state != MHI_PM_SYS_ERR_DETECT && ee != MHI_EE_RDDM) goto exit_intvec; switch (ee) { case MHI_EE_RDDM: /* proceed if power down is not already in progress */ - if (mhi_cntrl->rddm_image && mhi_is_active(mhi_cntrl)) { + if (mhi_cntrl->rddm_size && mhi_is_active(mhi_cntrl)) { mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); mhi_cntrl->ee = ee; wake_up_all(&mhi_cntrl->state_event); diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c index 11c0e751f223..68524e27e76c 100644 --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c @@ -767,7 +767,7 @@ void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl) struct device *dev = &mhi_cntrl->mhi_dev->dev; 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Thu, 18 Jul 2024 06:14:11 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46I6EAgE000684 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2024 06:14:10 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:14:08 -0700 From: Gokul Sriram Palanisamy To: , , CC: , , Subject: [PATCH 3/6] bus: mhi: increase RDDM timeout Date: Thu, 18 Jul 2024 11:43:41 +0530 Message-ID: <20240718061344.575653-4-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718061344.575653-1-quic_gokulsri@quicinc.com> References: <20240718061344.575653-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wAcXuOFLExhnAa_GDbsMfQ28Ra_TFwcD X-Proofpoint-ORIG-GUID: wAcXuOFLExhnAa_GDbsMfQ28Ra_TFwcD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 bulkscore=0 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180040 From: Praveenkumar I Host sometimes misses the EE RDDM during kernel panic causing RDDM failure. Increase RDDM timeout to overcome this issue. Signed-off-by: Praveenkumar I Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/host/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c index 1a918e340424..324510d2c7fd 100644 --- a/drivers/bus/mhi/host/boot.c +++ b/drivers/bus/mhi/host/boot.c @@ -77,7 +77,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) enum mhi_ee_type ee; const u32 delayus = 2000; u32 retry = (mhi_cntrl->timeout_ms * 1000) / delayus; - const u32 rddm_timeout_us = 200000; + const u32 rddm_timeout_us = 400000; int rddm_retry = rddm_timeout_us / delayus; void __iomem *base = mhi_cntrl->bhie; struct device *dev = &mhi_cntrl->mhi_dev->dev; From patchwork Thu Jul 18 06:13:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 813234 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52DB554662 for ; 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Thu, 18 Jul 2024 06:14:14 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46I6EDDY017626 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2024 06:14:13 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:14:10 -0700 From: Gokul Sriram Palanisamy To: , , CC: , , Subject: [PATCH 4/6] bus: mhi: dump debug registers in critical sections Date: Thu, 18 Jul 2024 11:43:42 +0530 Message-ID: <20240718061344.575653-5-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718061344.575653-1-quic_gokulsri@quicinc.com> References: <20240718061344.575653-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rHYlUKGpQLdpZ3IFrLx66KSftGj3SBSq X-Proofpoint-GUID: rHYlUKGpQLdpZ3IFrLx66KSftGj3SBSq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180040 ERRCODE and ERRDBG registers are dumped during BHI failure. Extend this to BHIe and RDDM failures. Also, add additional status registers essential for debug and make this debug function available for client driver. Co-developed-by: Vignesh Viswanathan Signed-off-by: Vignesh Viswanathan Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/host/boot.c | 53 +++++++++++++++++------------- drivers/bus/mhi/host/main.c | 65 +++++++++++++++++++++++++++++++++++++ drivers/bus/mhi/host/pm.c | 4 ++- include/linux/mhi.h | 5 +++ 4 files changed, 103 insertions(+), 24 deletions(-) diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c index 324510d2c7fd..b403890d873b 100644 --- a/drivers/bus/mhi/host/boot.c +++ b/drivers/bus/mhi/host/boot.c @@ -159,6 +159,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) error_exit_rddm: dev_err(dev, "RDDM transfer failed. Current EE: %s\n", TO_MHI_EXEC_STR(ee)); + mhi_debug_reg_dump(mhi_cntrl); return -EIO; } @@ -168,6 +169,7 @@ int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic) { void __iomem *base = mhi_cntrl->bhie; struct device *dev = &mhi_cntrl->mhi_dev->dev; + rwlock_t *pm_lock = &mhi_cntrl->pm_lock; struct mhi_buf *mhi_buf = NULL; u32 rx_status; int ret; @@ -217,6 +219,15 @@ int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic) dma_unmap_single(mhi_cntrl->cntrl_dev, mhi_buf->dma_addr, mhi_buf->len, DMA_TO_DEVICE); + if (ret) { + dev_err(dev, "RDDM transfer failed. RXVEC_STATUS: 0x%x\n", + rx_status); + read_lock_bh(pm_lock); + if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) + mhi_debug_reg_dump(mhi_cntrl); + read_unlock_bh(pm_lock); + } + return ret; } EXPORT_SYMBOL_GPL(mhi_download_rddm_image); @@ -263,8 +274,22 @@ static int mhi_fw_load_bhie(struct mhi_controller *mhi_cntrl, &tx_status) || tx_status, msecs_to_jiffies(mhi_cntrl->timeout_ms)); if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || - tx_status != BHIE_TXVECSTATUS_STATUS_XFER_COMPL) + tx_status != BHIE_TXVECSTATUS_STATUS_XFER_COMPL) { + dev_err(dev, "Upper:0x%x Lower:0x%x len:0x%zx sequence:%u\n", + upper_32_bits(mhi_buf->dma_addr), + lower_32_bits(mhi_buf->dma_addr), + mhi_buf->len, sequence_id); + + dev_err(dev, "MHI pm_state: %s tx_status: %d ee: %s\n", + to_mhi_pm_state_str(mhi_cntrl->pm_state), tx_status, + TO_MHI_EXEC_STR(mhi_get_exec_env(mhi_cntrl))); + + read_lock_bh(pm_lock); + if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) + mhi_debug_reg_dump(mhi_cntrl); + read_unlock_bh(pm_lock); return -EIO; + } return (!ret) ? -ETIMEDOUT : 0; } @@ -273,21 +298,11 @@ static int mhi_fw_load_bhi(struct mhi_controller *mhi_cntrl, dma_addr_t dma_addr, size_t size) { - u32 tx_status, val, session_id; - int i, ret; + u32 tx_status, session_id; + int ret; void __iomem *base = mhi_cntrl->bhi; rwlock_t *pm_lock = &mhi_cntrl->pm_lock; struct device *dev = &mhi_cntrl->mhi_dev->dev; - struct { - char *name; - u32 offset; - } error_reg[] = { - { "ERROR_CODE", BHI_ERRCODE }, - { "ERROR_DBG1", BHI_ERRDBG1 }, - { "ERROR_DBG2", BHI_ERRDBG2 }, - { "ERROR_DBG3", BHI_ERRDBG3 }, - { NULL }, - }; read_lock_bh(pm_lock); if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { @@ -319,16 +334,8 @@ static int mhi_fw_load_bhi(struct mhi_controller *mhi_cntrl, if (tx_status == BHI_STATUS_ERROR) { dev_err(dev, "Image transfer failed\n"); read_lock_bh(pm_lock); - if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { - for (i = 0; error_reg[i].name; i++) { - ret = mhi_read_reg(mhi_cntrl, base, - error_reg[i].offset, &val); - if (ret) - break; - dev_err(dev, "Reg: %s value: 0x%x\n", - error_reg[i].name, val); - } - } + if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) + mhi_debug_reg_dump(mhi_cntrl); read_unlock_bh(pm_lock); goto invalid_pm_state; } diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 2f44f11fa5a6..26baa04badf4 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -1707,3 +1707,68 @@ int mhi_get_channel_doorbell_offset(struct mhi_controller *mhi_cntrl, u32 *chdb_ return 0; } EXPORT_SYMBOL_GPL(mhi_get_channel_doorbell_offset); + +void mhi_debug_reg_dump(struct mhi_controller *mhi_cntrl) +{ + enum mhi_state state; + enum mhi_ee_type ee; + int i, ret; + u32 val; + void __iomem *mhi_base = mhi_cntrl->regs; + void __iomem *bhi_base = mhi_cntrl->bhi; + void __iomem *bhie_base = mhi_cntrl->bhie; + void __iomem *wake_db = mhi_cntrl->wake_db; + struct { + const char *name; + int offset; + void *base; + } debug_reg[] = { + { "MHI_CNTRL", MHICTRL, mhi_base}, + { "MHI_STATUS", MHISTATUS, mhi_base}, + { "MHI_WAKE_DB", 0, wake_db}, + { "BHI_EXECENV", BHI_EXECENV, bhi_base}, + { "BHI_STATUS", BHI_STATUS, bhi_base}, + { "BHI_ERRCODE", BHI_ERRCODE, bhi_base}, + { "BHI_ERRDBG1", BHI_ERRDBG1, bhi_base}, + { "BHI_ERRDBG2", BHI_ERRDBG2, bhi_base}, + { "BHI_ERRDBG3", BHI_ERRDBG3, bhi_base}, + { "BHIE_TXVEC_DB", BHIE_TXVECDB_OFFS, bhie_base}, + { "BHIE_TXVEC_STATUS", BHIE_TXVECSTATUS_OFFS, bhie_base}, + { "BHIE_RXVEC_DB", BHIE_RXVECDB_OFFS, bhie_base}, + { "BHIE_RXVEC_STATUS", BHIE_RXVECSTATUS_OFFS, bhie_base}, + { "BHIE_IMGTXDB", BHI_IMGTXDB, bhie_base}, + { NULL }, + }; + + dev_info(&mhi_cntrl->mhi_dev->dev, + "host pm_state:%s dev_state:%s ee:%s\n", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + mhi_state_str(mhi_cntrl->dev_state), + TO_MHI_EXEC_STR(mhi_cntrl->ee)); + + state = mhi_get_mhi_state(mhi_cntrl); + + if (!mhi_cntrl->bhi) { + dev_err(&mhi_cntrl->mhi_dev->dev, + "BHI not initialized, failed to dump debug registers\n"); + return; + } + + ee = mhi_get_exec_env(mhi_cntrl); + + dev_info(&mhi_cntrl->mhi_dev->dev, + "device ee:%s dev_state:%s\n", TO_MHI_EXEC_STR(ee), + mhi_state_str(state)); + + for (i = 0; debug_reg[i].name; i++) { + if (!debug_reg[i].base) + continue; + + ret = mhi_read_reg(mhi_cntrl, debug_reg[i].base, + debug_reg[i].offset, &val); + dev_info(&mhi_cntrl->mhi_dev->dev, + "reg:%s val:0x%x, ret:%d\n", debug_reg[i].name, val, + ret); + } +} +EXPORT_SYMBOL_GPL(mhi_debug_reg_dump); diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c index 68524e27e76c..5db99e092dbe 100644 --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c @@ -1267,8 +1267,10 @@ int mhi_sync_power_up(struct mhi_controller *mhi_cntrl) msecs_to_jiffies(timeout_ms)); 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Thu, 18 Jul 2024 06:14:16 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46I6EF10024698 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2024 06:14:15 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:14:13 -0700 From: Gokul Sriram Palanisamy To: , , CC: , , Subject: [PATCH 5/6] bus: mhi: check for RDDM cookie set by device to indicate readiness Date: Thu, 18 Jul 2024 11:43:43 +0530 Message-ID: <20240718061344.575653-6-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718061344.575653-1-quic_gokulsri@quicinc.com> References: <20240718061344.575653-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hxxMEmlZ3HNoO6UHnkqmAIBnqwHXqnyB X-Proofpoint-ORIG-GUID: hxxMEmlZ3HNoO6UHnkqmAIBnqwHXqnyB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180040 From: Rajkumar Ayyasamy If the device is unable to send the mission mode execution environment change event but has already entered mission mode with the ability to allow ramdump collection, it can set a unique cookie pattern to indicate the availability of ramdumps. Allow the controller to query for this unique pattern upon any bootup failure or timeout. Signed-off-by: Rajkumar Ayyasamy Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/host/main.c | 44 +++++++++++++++++++++++++++++++++++++ include/linux/mhi.h | 8 +++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 26baa04badf4..de804a701b85 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -1772,3 +1772,47 @@ void mhi_debug_reg_dump(struct mhi_controller *mhi_cntrl) } } EXPORT_SYMBOL_GPL(mhi_debug_reg_dump); + +bool mhi_scan_rddm_cookie(struct mhi_controller *mhi_cntrl, u32 cookie) +{ + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int ret; + int i; + u32 val; + bool result = false; + struct { + char *name; + u32 offset; + } error_reg[] = { + { "ERROR_DBG1", BHI_ERRDBG1 }, + { "ERROR_DBG2", BHI_ERRDBG2 }, + { "ERROR_DBG3", BHI_ERRDBG3 }, + { NULL }, + }; + + if (!mhi_cntrl->rddm_size || !cookie) + return false; + + dev_dbg(dev, "Checking BHI debug register for 0x%x\n", cookie); + + if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) + return false; + + /* look for an RDDM cookie match in any of the error debug registers */ + for (i = 0; error_reg[i].name; i++) { + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, + error_reg[i].offset, &val); + if (ret) + break; + dev_dbg(dev, "reg:%s value:0x%x\n", error_reg[i].name, val); + + if (!(val ^ cookie)) { + dev_err(dev, "RDDM cookie found in %s\n", + error_reg[i].name); + return true; + } + } + dev_dbg(dev, "RDDM cookie not found\n"); + return result; +} +EXPORT_SYMBOL_GPL(mhi_scan_rddm_cookie); diff --git a/include/linux/mhi.h b/include/linux/mhi.h index c0c9bfc28e4a..2f90de8616f3 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -839,4 +839,12 @@ int mhi_get_channel_doorbell_offset(struct mhi_controller *mhi_cntrl, u32 *chdb_ * @mhi_cntrl: MHI controller */ void mhi_debug_reg_dump(struct mhi_controller *mhi_cntrl); + +/** + * mhi_scan_rddm_cookie - Look for supplied cookie value in the BHI debug + * registers set by device to indicate rddm readiness for debugging purposes. + * @mhi_cntrl: MHI controller + * @cookie: cookie/pattern value to match + */ +bool mhi_scan_rddm_cookie(struct mhi_controller *mhi_cntrl, u32 cookie); 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Thu, 18 Jul 2024 06:14:18 GMT Received: from hu-gokulsri-blr.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:14:16 -0700 From: Gokul Sriram Palanisamy To: , , CC: , , Subject: [PATCH 6/6] bus: mhi: change IRQ_HANDLED to IRQ_NONE in mhi_irq_handler Date: Thu, 18 Jul 2024 11:43:44 +0530 Message-ID: <20240718061344.575653-7-quic_gokulsri@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240718061344.575653-1-quic_gokulsri@quicinc.com> References: <20240718061344.575653-1-quic_gokulsri@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3qlNfFwTwjOFWYOBiSUZcSvbhv7h4w5D X-Proofpoint-GUID: 3qlNfFwTwjOFWYOBiSUZcSvbhv7h4w5D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 mlxlogscore=747 priorityscore=1501 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180040 From: Karthick Shanmugham When mhi_irq_handler is a shared interrupt handler. It is the shared interrupt handlers responsibility to identify its own interrupt and exit quickly if it is not. If there is no pending event in the event ring handled, exit the interrupt context returning IRQ_NONE denoting the interrupt either doesn't belong to this event ring or not handled. Signed-off-by: Karthick Shanmugham Signed-off-by: Vignesh Viswanathan Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/host/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index de804a701b85..f87eb0c2b01a 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -462,7 +462,7 @@ irqreturn_t mhi_irq_handler(int irq_number, void *dev) /* Only proceed if event ring has pending events */ if (ev_ring->rp == dev_rp) - return IRQ_HANDLED; + return IRQ_NONE; /* For client managed event ring, notify pending data */ if (mhi_event->cl_manage) {