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Replace the type_init() / type_register_static() combination. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index e6a7142480..dc82caea0d 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -363,17 +363,14 @@ static void loongson_ipi_finalize(Object *obj) g_free(s->cpu); } -static const TypeInfo loongson_ipi_info = { - .name = TYPE_LOONGSON_IPI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPI), - .class_init = loongson_ipi_class_init, - .instance_finalize = loongson_ipi_finalize, +static const TypeInfo loongson_ipi_types[] = { + { + .name = TYPE_LOONGSON_IPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(LoongsonIPI), + .class_init = loongson_ipi_class_init, + .instance_finalize = loongson_ipi_finalize, + } }; -static void loongson_ipi_register_types(void) -{ - type_register_static(&loongson_ipi_info); -} - -type_init(loongson_ipi_register_types) +DEFINE_TYPES(loongson_ipi_types) From patchwork Thu Jul 18 08:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813133 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188416wro; Thu, 18 Jul 2024 01:39:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXzB4RF8C1LsK1WyGf/F6oY8Tm/J1lNgM5bARNQz0zJnmhId8iQBnzDVUT/0V8u5lQY/nw808t3R4IbsvalhD2f X-Google-Smtp-Source: AGHT+IG9nh81eTvwSLMb8fXtUf3JQvQl+k7jQOq9205SrpqX84WwctrehfMG1SN/TX44kr2i7/wD X-Received: by 2002:a05:622a:1825:b0:447:e562:b6b with SMTP id d75a77b69052e-44f96aaa6b7mr1099391cf.64.1721291976296; Thu, 18 Jul 2024 01:39:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721291976; cv=none; d=google.com; s=arc-20160816; b=qJFq7ZEdlSSiYFOWnvgvpXbuAO0W/fs3J95JHDbMuQj/PymkXPa73vF9v4VhdELWWy WR/08RlI4+8AD2GnEfln3+0UaISG9NsVkzWTAwLNatbJqbTR4ufY2oQS8TvgCHu7/c3d Kbk232NXBxX6Dpsqqm0J1+d/UV1xoOmWAC74KcseNghQazOma3xiJJNVIKODNRUWM3+x 94chA0VuuccqRA6hAPSAutUFxXnWggi/rnSMoRMrsLkU6SWDwKzOAk9JnsMxy1RPV1Ou mXeJTmc5hwnpLhYMMqjXF05XRKzw75y7YGDxe1+fyQjfEBWNhJ8vVkgbXj56Ns8MkhkQ PYpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f3KoNavigW3dLA5bJeMlYDVs2sTflgXH0yz8/6ddF9M=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=TAUsRiX9p3IOXcbzoPwn9/A2dz9wXC3HOItH8xzHC5BWjd/K4kMiN6f5e4eydl5YVE QHlF83h4f9LzOxw/6Omeu4YZe+tbLNtuDhQTfa/skaBrMVMHnvm+HaDNrTO5cU2Ebi52 L/9n7NIWyfJTmjAFW4GkwUA8L3CD82pf3WyaFtZNvmhUoN0/K1+fUHg/B213fr99d5tg PZgSyDRQ+i/y7IKfoY9mFf5yH+38vkQrFp45EZ8AgWvLi+JkdffC2uefedLP0C49B80P F83sNWvQBtC/42uO5j4xfH1CBwV1nyYr3bONRVBcbAMJ5k7tHcBRboGRD01V8U5mZXbZ duqg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jJ6NRMEL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support") [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao --- hw/intc/loongson_ipi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index dc82caea0d..d315f6f303 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "exec/address-spaces.h" +#include "exec/memory.h" #include "migration/vmstate.h" #ifdef TARGET_LOONGARCH64 #include "target/loongarch/cpu.h" @@ -102,7 +103,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, * if the mask is 0, we need not to do anything. */ if ((val >> 27) & 0xf) { - data = address_space_ldl(iocsr_as, addr, attrs, NULL); + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); for (i = 0; i < 4; i++) { /* get mask for byte writing */ if (val & (0x1 << (27 + i))) { @@ -113,7 +114,7 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, data &= mask; data |= (val >> 32) & ~mask; - address_space_stl(iocsr_as, addr, data, attrs, NULL); + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); return MEMTX_OK; } From patchwork Thu Jul 18 08:38:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813132 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188404wro; Thu, 18 Jul 2024 01:39:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVS3iFY4g02Rx8E5UL0TTUD0li2s0wXZbTjtabKhGB9rMGBPsANpivW3GYiDAPGhcIyQDdAge199wj8N3E9T1dt X-Google-Smtp-Source: AGHT+IF7HFzhw/KVkC2mlI4lNZSwRv2uf/QFQnnpmYrm4eg316JjiXy+ztjB3ebw//oIg5jhI2ba X-Received: by 2002:a05:6102:32d1:b0:48f:b577:e02d with SMTP id ada2fe7eead31-49159a0b3f8mr4738088137.25.1721291974088; Thu, 18 Jul 2024 01:39:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721291974; cv=none; d=google.com; s=arc-20160816; b=qFqmuO6MXiNj8M/0H2hOiMziHozIdUD4xdEpiojVDBn816xtSccrSRVa5YFeYMsE0C gM/Coi+rTpz6hqj9DMCEoVgGoNasYJ28679LfJyWCP595DncLeXJFs1CNVXqc5JoV5Vw CMn7KUt8wRONhB1NSvsNaapSoqyaXSmzKIPl+7TWSMykn7jey1qDDiy5IY7UJ2a3vwYt dOrqp7YhO3ooU+B5L03mlzTMrA/JtJ02hk/MpeKt6tBlZmBC4an1v3w61AJfB94zeJE8 bkbMAwjs1mpG37lITCXkBX1myrBt7RULTJWn4P4JqUBG2fBq5sHDOWqyWsuAg7vt+mue xqwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f5lansJILRN85MsTS1zJi4KEEbl2KrPrS5MA+Irf47U=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=L1i3ZhGvOz1r3EUUfxQc/NXWyvnv+SvHvmgWNgXFaW05EjeMpR5oJdTg8mDhORz7FC w9ocsud88qPct9CUTDlXwnmb3WS7jw4G7wI6E+Lle2lGA6vl4ZThMakaD2KptayVBjos VZs6igbbkgbl3dHGUr/V0l6DnMMB2UUPMzHiZ9+1H/rb6HCobXYxzmHbV8rzGx+mMDGY OlCm086E4dv75qc2Yc0FHvweHBYiVnrnRFpTYXCgg5FGPhGw027mJSdhrlfNkk4QTtJu wvnCPtYUqECK6XuMD1CVuEmtBuAq39RjjkOo52ol6sk389+P/p8TmWogX7Kbt+DwFD3X 767w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xWnStxm5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi.h | 6 +++--- hw/intc/loongson_ipi.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 3f795edbf3..efb772f384 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -31,10 +31,10 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) +OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) typedef struct IPICore { - LoongsonIPI *ipi; + LoongsonIPIState *ipi; MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; @@ -45,7 +45,7 @@ typedef struct IPICore { qemu_irq irq; } IPICore; -struct LoongsonIPI { +struct LoongsonIPIState { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index d315f6f303..d870af39c1 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPI *ipi = s->ipi; + LoongsonIPIState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPI *ipi = opaque; + LoongsonIPIState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_realize(DeviceState *dev, Error **errp) { - LoongsonIPI *s = LOONGSON_IPI(dev); + LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -337,14 +337,14 @@ static const VMStateDescription vmstate_loongson_ipi = { .version_id = 2, .minimum_version_id = 2, .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu, + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, vmstate_ipi_core, IPICore), VMSTATE_END_OF_LIST() } }; static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1), + DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -359,7 +359,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) static void loongson_ipi_finalize(Object *obj) { - LoongsonIPI *s = LOONGSON_IPI(obj); + LoongsonIPIState *s = LOONGSON_IPI(obj); g_free(s->cpu); } @@ -368,7 +368,7 @@ static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPI), + .instance_size = sizeof(LoongsonIPIState), .class_init = loongson_ipi_class_init, .instance_finalize = loongson_ipi_finalize, } From patchwork Thu Jul 18 08:38:28 2024 Content-Type: text/plain; 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index d870af39c1..960d1e604f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -357,13 +357,18 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_loongson_ipi; } -static void loongson_ipi_finalize(Object *obj) +static void loongson_ipi_common_finalize(Object *obj) { LoongsonIPIState *s = LOONGSON_IPI(obj); g_free(s->cpu); } +static void loongson_ipi_finalize(Object *obj) +{ + loongson_ipi_common_finalize(obj); +} + static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, From patchwork Thu Jul 18 08:38:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813137 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188716wro; Thu, 18 Jul 2024 01:40:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXwxDBlBvFmBjPMjqm1MFArwANkHtU0Rm8YTRh3b3a8chPB8tg2oxa2Dx4eUbxodcgeAGlveUyH9M+1Cawy3F+9 X-Google-Smtp-Source: AGHT+IHi91AJV5GvIN9L3nQJzhBlFn4NjCT234wJoq92fdlLeB4EaGIEyE6K5fZenb+AVf39hbnn X-Received: by 2002:a05:620a:2483:b0:79e:fb4a:ed35 with SMTP id af79cd13be357-7a1939a56admr12889985a.68.1721292028546; Thu, 18 Jul 2024 01:40:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292028; cv=none; d=google.com; s=arc-20160816; b=y+ingII8Puczs9hznrC+fMJm3fjUGnhEpKtMOnUmKmU11e1BnyZ1gxg0mf59mCJoU4 hkIzw4CNTjsx+kGkS8cSLG7SeyXkHMFlFNV77zKlPQVksJslO1N4x9H+cf0t3MZciVjp KSSmN++9EMxcg+1SX4Txw0JadCX+Q/OgBrU9LXRFv5QywxmaoM0a26EfSwouVRfF3l0W 9hlPSIrke6bqFb95AfD/T2USQW5RueGaBjZfaiObGXCMsciNtl64DZb887Eyne5m5Boj L9Y4LwC8ZjpUzmQBnsKtxGb9z4/05nRGmpoUBrtKaZkRivwSka1wdroqzdaBrejKaTtF cIfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C+5AHR8p04TtPyVB2xdxLCWoE6SoJESjvxVPVtFQfTE=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=xA+Zc3UzqFPxjT8JLLVCkTZei0k8IltSodsmfdJELlhC//hX58AVWypUDNf6H0yCK7 DswzXA+0LIFEHQrTesgfVlfAS05DGQgFwkGFQmIyKzUpwxV+Tl0KWNEozZYP6yMMbbIO ER16xX3QBdw/Vj3RGQO20Ako/0Uxn0vckW0qju7QgcwryG3HsPgMpm10phQNQxvZVBz6 rr+d60nhYkh5z1ybzVoSFKWZZS1v3DFkFdrUNLZ13h1s5+xDjK13vqLkTZ13VhfJkTGt SiLXKW7CU5G7FZYdItlDe/VwRC6h8yWM9ShEntoNBQ7s9F4K8r4uOFs2zL8oIcvNStv2 VZvA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iwk7cJ+j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7a1939b0361si7461285a.561.2024.07.18.01.40.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 01:40:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iwk7cJ+j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUMfh-0003LT-Gj; Thu, 18 Jul 2024 04:39:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUMff-0003EP-MJ for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:39:27 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sUMfe-0004jl-2p for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:39:27 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-367e50f71bbso316370f8f.2 for ; Thu, 18 Jul 2024 01:39:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721291964; x=1721896764; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C+5AHR8p04TtPyVB2xdxLCWoE6SoJESjvxVPVtFQfTE=; b=iwk7cJ+jh30jfxt29wlY3xkIgbT4wA1Aj5S2Y8vmFH4+LTRTpoli+X6ME3Wyr/PwTK YB+Le9UzuKqZ2uJH8NMfpZGYKRD0313tgWey3g+TWwM3pTuGBDeleFVyOII5Hi0qiuSi zyadFt8B1YOZb778eQC2PrIhOg3hx/SRIna5CWIf1fKp+IsluLdxyoEWY19Nh68p/Fr0 5zy97tNx22i4xG/KbAjdv/PX+F7rTK7itlmhBdhoqFnqoTJzxe9utt2puBW9BCX2+/PY H8zmNqRIrc6YvTgpf03FQM8Y4g2voG+UdtFpXv+RYlROpL1CXhNR9YuxxJ6wzUpOZ+zG Zr/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721291964; x=1721896764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C+5AHR8p04TtPyVB2xdxLCWoE6SoJESjvxVPVtFQfTE=; b=HDryNVmC8rAgagzTIeVwtSedu0xPBgeck9TDYEdNfdS8la7RXxbE7OtOpeYbo/GgE6 P+nVR2yFZeMqm0oK/sVDMv4zMd/Ha+UJkv3Vr/zhMHJcShAfBY9d8bY7Wb2AUUznmIj/ 2buAodadOkDdwTkw3oSo3sF3KEg+Mo+pGLEFtWvpcwaGLPV2gWCXZ+Uv/50bYkEyoyGa Ef9B93vC/mbcwDJg+l0htqHaHNeqEdDN+Wttn6DmHNot6Fd2n9It0pgyUfbbsWDikH0s CDBZLPz/hHVp3vrQSgEo1WFATyJC29CLmwLIW49CqW14a0XE3qZIkObuGA6WhpcBvZPa IfWg== X-Gm-Message-State: AOJu0Yzfb+0LFkIfri0i7zE+W/snf/UMb3J4mg1z2uUmAdzgNKcaUjgK PbhD6bRmvz/xjeFmC+9fD/AiV3Tbqx4lFb7ZuoukW52an7dZ3zrQxOG49JOReBJQ6fzEFlPVenH br8M= X-Received: by 2002:a05:6000:e88:b0:35f:1c34:adfc with SMTP id ffacd0b85a97d-36831797724mr2189240f8f.67.1721291964275; Thu, 18 Jul 2024 01:39:24 -0700 (PDT) Received: from localhost.localdomain ([176.187.208.21]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680dabefa6sm13595076f8f.44.2024.07.18.01.39.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 01:39:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 05/18] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize() Date: Thu, 18 Jul 2024 10:38:29 +0200 Message-ID: <20240718083842.81199-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao In preparation to extract common IPI code in few commits, extract loongson_ipi_common_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 960d1e604f..bab4d8816b 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -275,7 +275,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void loongson_ipi_realize(DeviceState *dev, Error **errp) +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -301,20 +301,31 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); s->cpu = g_new0(IPICore, s->num_cpu); - if (s->cpu == NULL) { - error_setg(errp, "Memory allocation for IPICore faile"); + for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} + +static void loongson_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPIState *s = LOONGSON_IPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Error *local_err = NULL; + + loongson_ipi_common_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); return; } - for (i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi = s; + for (unsigned i = 0; i < s->num_cpu; i++) { s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } From patchwork Thu Jul 18 08:38:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813136 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188686wro; Thu, 18 Jul 2024 01:40:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXhWRklAjpjzSrvtegSuDCo0L0CzFcLzzbg/+ttHhijVOwvtFl1+W+4UZiqVBXCRRxaA33mRNeYjEV2beYy2Pyb X-Google-Smtp-Source: AGHT+IGd+otfTZg4EQL6OOggkvbqTT4z1Ve75YFiXhjF7zPZ6tQgeS1d+ylIAZG84WBxMoYxOsae X-Received: by 2002:a05:622a:ca:b0:447:eb43:5d0b with SMTP id d75a77b69052e-44f969ee726mr1515681cf.28.1721292020478; Thu, 18 Jul 2024 01:40:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292020; cv=none; d=google.com; s=arc-20160816; b=gIVrA2qAYvLNZVXgzHh8qXvCDHOJgWCnRFBTosVhreiPhhVVJQBz/EQ1Yc8e6bua0B 4NmD/sfCuhaLxi4LIqGQA+okEAEi3DZS6sXSEnRPb7PAPc4EG8h0JZDptHsPm3xlHG6V FKAaSZa/U96emg3ZXwMhgYTRID9+ug6U0UHv9StfiHAQqOocXTPkDF/h7rMCCEEF6dVH acq8TS/55/QngQde4UUP7aDr5GbRXPsp51g5YTbB+dWw/yy9iHbOlyCLO46BI0vybVp4 xjRw4lNz78rlPFi0mv14hkjdCBvaX8JvFsw0lYatuEF4wUT81FHJu8ugJEEgtpmJXJ3s aslQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gRzCXvtzkPmeeEJYSrxHKRmhlxarGZ8XNXu4iVW4RiU=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=hhsM/hO8o5CqEvKQUIkWN+VcihCM/uCEX3it7VbaZaQrvhk0d0Fa2zOVs599Pyr4sW cm9iCp/E7dZmYOSDop6N5xdxjIcCu3bCZPs4pJd04B2NPtoJe8BHjsjwue4EFcjDb5Ky G1XvGrQXoFSKNh5bqVUzEx0qRnzx6y7k2uAlOJpRa6rkGJgT7vTFfqIWFFFggyUIckGQ Ig878D/BzOD6orvLyI4YLK3B59JroY1OBMP2MMaQIQTx+HGHDpYXw2zBNtMAaFi7b6X8 txHafldibf6coYAIHXJKvIyXDSN4uAg1O/5p72ynfxZXbaJWKPQhI5xZN/WiPU305wMF W3aw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KsQZ7ib1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- MAINTAINERS | 4 ++++ include/hw/intc/loongson_ipi.h | 13 +++++++++++-- include/hw/intc/loongson_ipi_common.h | 26 ++++++++++++++++++++++++++ hw/intc/loongson_ipi.c | 7 ++++--- hw/intc/loongson_ipi_common.c | 22 ++++++++++++++++++++++ hw/intc/Kconfig | 4 ++++ hw/intc/meson.build | 1 + 7 files changed, 72 insertions(+), 5 deletions(-) create mode 100644 include/hw/intc/loongson_ipi_common.h create mode 100644 hw/intc/loongson_ipi_common.c diff --git a/MAINTAINERS b/MAINTAINERS index 7d9811458c..a670c8ee67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1249,8 +1249,10 @@ F: configs/devices/loongarch64-softmmu/default.mak F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c @@ -1385,11 +1387,13 @@ Loongson-3 virtual platforms M: Huacai Chen R: Jiaxun Yang S: Maintained +F: hw/intc/loongson_ipi_common.c F: hw/intc/loongson_ipi.c F: hw/intc/loongson_liointc.c F: hw/mips/loongson3_bootp.c F: hw/mips/loongson3_bootp.h F: hw/mips/loongson3_virt.c +F: include/hw/intc/loongson_ipi_common.h F: include/hw/intc/loongson_ipi.h F: include/hw/intc/loongson_liointc.h F: tests/avocado/machine_mips_loongson3v.py diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index efb772f384..82cb64ca40 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -8,6 +8,8 @@ #ifndef HW_LOONGSON_IPI_H #define HW_LOONGSON_IPI_H +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" /* Mainy used by iocsr read and write */ @@ -31,7 +33,7 @@ #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPIState, LOONGSON_IPI) +OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; @@ -45,8 +47,15 @@ typedef struct IPICore { qemu_irq irq; } IPICore; +struct LoongsonIPIClass { + LoongsonIPICommonClass parent_class; + + DeviceRealize parent_realize; +}; + struct LoongsonIPIState { - SysBusDevice parent_obj; + LoongsonIPICommonState parent_obj; + MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h new file mode 100644 index 0000000000..70ac69d0ba --- /dev/null +++ b/include/hw/intc/loongson_ipi_common.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGSON_IPI_COMMON_H +#define HW_LOONGSON_IPI_COMMON_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" +OBJECT_DECLARE_TYPE(LoongsonIPICommonState, + LoongsonIPICommonClass, LOONGSON_IPI_COMMON) + +struct LoongsonIPICommonState { + SysBusDevice parent_obj; +}; + +struct LoongsonIPICommonClass { + SysBusDeviceClass parent_class; +}; + +#endif diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index bab4d8816b..20f3f6bd3f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -362,8 +362,10 @@ static Property ipi_properties[] = { static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); - dc->realize = loongson_ipi_realize; + device_class_set_parent_realize(dc, loongson_ipi_realize, + &lic->parent_realize); device_class_set_props(dc, ipi_properties); dc->vmsd = &vmstate_loongson_ipi; } @@ -383,8 +385,7 @@ static void loongson_ipi_finalize(Object *obj) static const TypeInfo loongson_ipi_types[] = { { .name = TYPE_LOONGSON_IPI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LoongsonIPIState), + .parent = TYPE_LOONGSON_IPI_COMMON, .class_init = loongson_ipi_class_init, .instance_finalize = loongson_ipi_finalize, } diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c new file mode 100644 index 0000000000..87d992aa95 --- /dev/null +++ b/hw/intc/loongson_ipi_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt common support + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/intc/loongson_ipi_common.h" + +static const TypeInfo loongarch_ipi_types[] = { + { + .name = TYPE_LOONGSON_IPI_COMMON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(LoongsonIPICommonState), + .class_size = sizeof(LoongsonIPICommonClass), + .abstract = true, + } +}; + +DEFINE_TYPES(loongarch_ipi_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 58b6d3a710..a2a0fdca85 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -87,8 +87,12 @@ config GOLDFISH_PIC config M68K_IRQC bool +config LOONGSON_IPI_COMMON + bool + config LOONGSON_IPI bool + select LOONGSON_IPI_COMMON config LOONGARCH_PCH_PIC bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index afd1aa51ee..a09a527207 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -69,6 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) From patchwork Thu Jul 18 08:38:31 2024 Content-Type: text/plain; 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Thu, 18 Jul 2024 01:39:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 07/18] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h Date: Thu, 18 Jul 2024 10:38:31 +0200 Message-ID: <20240718083842.81199-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi.h | 18 ------------------ include/hw/intc/loongson_ipi_common.h | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 82cb64ca40..d53bd5dcfe 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,24 +12,6 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -/* Mainy used by iocsr read and write */ -#define SMP_IPI_MAILBOX 0x1000ULL -#define CORE_STATUS_OFF 0x0 -#define CORE_EN_OFF 0x4 -#define CORE_SET_OFF 0x8 -#define CORE_CLEAR_OFF 0xc -#define CORE_BUF_20 0x20 -#define CORE_BUF_28 0x28 -#define CORE_BUF_30 0x30 -#define CORE_BUF_38 0x38 -#define IOCSR_IPI_SEND 0x40 -#define IOCSR_MAIL_SEND 0x48 -#define IOCSR_ANY_SEND 0x158 - -#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) -#define MAIL_SEND_OFFSET 0 -#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) - #define IPI_MBX_NUM 4 #define TYPE_LOONGSON_IPI "loongson_ipi" diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 70ac69d0ba..b43b77bda6 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -23,4 +23,23 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; }; +/* Mainy used by iocsr read and write */ +#define SMP_IPI_MAILBOX 0x1000ULL + +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 +#define IOCSR_IPI_SEND 0x40 +#define IOCSR_MAIL_SEND 0x48 +#define IOCSR_ANY_SEND 0x158 + +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) + #endif From patchwork Thu Jul 18 08:38:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813140 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188764wro; Thu, 18 Jul 2024 01:40:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVxaQPpZ2pmi7CNp44nRTMkTBExjmjOkXIQ9ukmCj73qxJzTd3bSqJ2xdH6l0mwFlbdzeNNVASmXlc6eouY7uXo X-Google-Smtp-Source: AGHT+IHK2W6oOQgBL7Z6bleqEzQFdxtOgX3RZsDq9IBdkvellYQ467qhGJy0/hZMT72nJO2EyYk6 X-Received: by 2002:a05:620a:4155:b0:795:5f15:f9e8 with SMTP id af79cd13be357-7a1939a8ac7mr13431785a.31.1721292036203; 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi.h | 2 +- hw/intc/loongson_ipi.c | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index d53bd5dcfe..00a65a82fb 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -19,7 +19,6 @@ OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) typedef struct IPICore { LoongsonIPIState *ipi; - MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; @@ -38,6 +37,7 @@ struct LoongsonIPIClass { struct LoongsonIPIState { LoongsonIPICommonState parent_obj; + MemoryRegion *ipi_mmio_mem; MemoryRegion ipi_iocsr_mem; MemoryRegion ipi64_iocsr_mem; uint32_t num_cpu; diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 20f3f6bd3f..2319aea18f 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -320,12 +320,12 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } + s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); for (unsigned i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1); g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } @@ -379,6 +379,9 @@ static void loongson_ipi_common_finalize(Object *obj) static void loongson_ipi_finalize(Object *obj) { + LoongsonIPIState *s = LOONGSON_IPI(obj); + + g_free(s->ipi_mmio_mem); loongson_ipi_common_finalize(obj); } From patchwork Thu Jul 18 08:38:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813142 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188870wro; Thu, 18 Jul 2024 01:40:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUTrQTQV87Q5GkB7Z1eLxi5/D+VlBc4DU2wNhQfL/C9oVVOvd7A3jqTBDIprQ3vxkrjOZnXQzOE0BAyph4rCWdH X-Google-Smtp-Source: AGHT+IHNW9ghhz/UTXVzLrsNq7/b7nMslZy7j1CZYf7SyszPDEotvFoh+rorW9GS020XPcKoJxgv X-Received: by 2002:a05:622a:2c1:b0:447:ea03:453e with SMTP id d75a77b69052e-44f96a3c280mr1239521cf.20.1721292055550; Thu, 18 Jul 2024 01:40:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292055; cv=none; d=google.com; s=arc-20160816; b=Smu50ihfe8/+Iox2oh1MXK8X5PaTiGLFbdl1nAfcNkBN/MgwzfxX2tQrtD3nXLSkV1 BYnIA9i6XYiPpcQSUD+bIaPFHV7zMWVOKPIyVSQVZw6ktkhnK2xoWUcBq3B1H7EbwM94 5k36CiXmOB2byjItYGym465Jqog8QvIepNumPwM5seco/GeYQ4/gkEDqgRHVxOhIx3wE OPF3oAerFg2f5C5BJ8LbXpwYj9fhkICA/UvaTQVPolzPjE40pirRXZgKHjsQhvlUb2Eb GpKafRGLzIOsZXcZK9+MiX9DAzasO+TKuW+8bzItCNO+1vcEfONJdFzq+GKXRZnIWrzg omBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MwUlVbRS/OHLa3iAWELYTaarEP0fTVCwOuM3NQnYqOU=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=u29fLnBaCR1rPhlMlRI0aTDlcQvZe9RIA/IvhPIkJgMvluAVS9c7kQzsQRiC5wwaaP sBKbRwR3jCJ3V7bUIPKsXzo1GETPnEWoVYB/6hc1bVNTMbC9J1RIb55w8Tcw30fuk5RP kGKij5BZIkdbn/cI5s2xqlghdCQds9NhoMSuNgnr2lIETxWF3tY+feeRB4m2paw523MQ +vMI5JvfdgigJPRCoUXv7X67fsdxYMhmZwNz4jT0lTun3SPfhcqGMzdEynSCsk54SxiX mbCIfuJndfRriYNL5U2Y+251VoBzk+HsSjd57n1IzL923+t/6YdcGUBIdGOSlMwX7MPM Zzdg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=luqNan6l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi.h | 17 -------- include/hw/intc/loongson_ipi_common.h | 18 +++++++++ hw/intc/loongson_ipi.c | 56 +++++---------------------- hw/intc/loongson_ipi_common.c | 50 ++++++++++++++++++++++++ 4 files changed, 77 insertions(+), 64 deletions(-) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 00a65a82fb..bb55899991 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -12,22 +12,9 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" -#define IPI_MBX_NUM 4 - #define TYPE_LOONGSON_IPI "loongson_ipi" OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) -typedef struct IPICore { - LoongsonIPIState *ipi; - uint32_t status; - uint32_t en; - uint32_t set; - uint32_t clear; - /* 64bit buf divide into 2 32bit buf */ - uint32_t buf[IPI_MBX_NUM * 2]; - qemu_irq irq; -} IPICore; - struct LoongsonIPIClass { LoongsonIPICommonClass parent_class; @@ -38,10 +25,6 @@ struct LoongsonIPIState { LoongsonIPICommonState parent_obj; MemoryRegion *ipi_mmio_mem; - MemoryRegion ipi_iocsr_mem; - MemoryRegion ipi64_iocsr_mem; - uint32_t num_cpu; - IPICore *cpu; }; #endif diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index b43b77bda6..891b43644d 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -11,12 +11,30 @@ #include "qom/object.h" #include "hw/sysbus.h" +#define IPI_MBX_NUM 4 + #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" OBJECT_DECLARE_TYPE(LoongsonIPICommonState, LoongsonIPICommonClass, LOONGSON_IPI_COMMON) +typedef struct IPICore { + LoongsonIPICommonState *ipi; + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + /* 64bit buf divide into 2 32bit buf */ + uint32_t buf[IPI_MBX_NUM * 2]; + qemu_irq irq; +} IPICore; + struct LoongsonIPICommonState { SysBusDevice parent_obj; + + MemoryRegion ipi_iocsr_mem; + MemoryRegion ipi64_iocsr_mem; + uint32_t num_cpu; + IPICore *cpu; }; struct LoongsonIPICommonClass { diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 2319aea18f..f3d1f031bc 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -64,7 +64,7 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -160,7 +160,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, MemTxAttrs attrs) { IPICore *s = opaque; - LoongsonIPIState *ipi = s->ipi; + LoongsonIPICommonState *ipi = s->ipi; int index = 0; uint32_t cpuid; uint8_t vector; @@ -214,7 +214,7 @@ static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { - LoongsonIPIState *ipi = opaque; + LoongsonIPICommonState *ipi = opaque; IPICore *s; if (attrs.requester_id >= ipi->num_cpu) { @@ -277,7 +277,7 @@ static const MemoryRegionOps loongson_ipi64_ops = { static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) { - LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); int i; @@ -310,6 +310,7 @@ static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) static void loongson_ipi_realize(DeviceState *dev, Error **errp) { + LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; @@ -320,45 +321,16 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp) return; } - s->ipi_mmio_mem = g_new0(MemoryRegion, s->num_cpu); - for (unsigned i = 0; i < s->num_cpu; i++) { + s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu); + for (unsigned i = 0; i < sc->num_cpu; i++) { g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); + memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x48); + &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48); sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); } } -static const VMStateDescription vmstate_ipi_core = { - .name = "ipi-single", - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongson_ipi = { - .name = TYPE_LOONGSON_IPI, - .version_id = 2, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPIState, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] = { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPIState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -366,15 +338,6 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) device_class_set_parent_realize(dc, loongson_ipi_realize, &lic->parent_realize); - device_class_set_props(dc, ipi_properties); - dc->vmsd = &vmstate_loongson_ipi; -} - -static void loongson_ipi_common_finalize(Object *obj) -{ - LoongsonIPIState *s = LOONGSON_IPI(obj); - - g_free(s->cpu); } static void loongson_ipi_finalize(Object *obj) @@ -382,7 +345,6 @@ static void loongson_ipi_finalize(Object *obj) LoongsonIPIState *s = LOONGSON_IPI(obj); g_free(s->ipi_mmio_mem); - loongson_ipi_common_finalize(obj); } static const TypeInfo loongson_ipi_types[] = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 87d992aa95..3b9e5c943d 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,6 +8,54 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +static void loongson_ipi_common_finalize(Object *obj) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(obj); + + g_free(s->cpu); +} + +static const VMStateDescription vmstate_ipi_core = { + .name = "ipi-single", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_UINT32(status, IPICore), + VMSTATE_UINT32(en, IPICore), + VMSTATE_UINT32(set, IPICore), + VMSTATE_UINT32(clear, IPICore), + VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_loongson_ipi = { + .name = "loongson_ipi", + .version_id = 2, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState, + num_cpu, vmstate_ipi_core, + IPICore), + VMSTATE_END_OF_LIST() + } +}; + +static Property ipi_properties[] = { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + device_class_set_props(dc, ipi_properties); + dc->vmsd = &vmstate_loongson_ipi; +} static const TypeInfo loongarch_ipi_types[] = { { @@ -15,6 +63,8 @@ static const TypeInfo loongarch_ipi_types[] = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(LoongsonIPICommonState), .class_size = sizeof(LoongsonIPICommonClass), + .class_init = loongson_ipi_common_class_init, + .instance_finalize = loongson_ipi_common_finalize, .abstract = true, } }; From patchwork Thu Jul 18 08:38:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813143 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188914wro; Thu, 18 Jul 2024 01:41:04 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUPL6Gr8NdK4KHYYaHlTyjsufj5cHWSXDYziTUM1KNBnTVvv7CfhiBvS7irCKi9GZz1cRCWvgycOSDHlWKbaaHu X-Google-Smtp-Source: AGHT+IGC2RsVMfMDykEYsRe0dzLCb3bZjP4FIYvZJ+g+ygU3K75afjJTuuIme7iX+41Kov25kLMB X-Received: by 2002:a05:620a:1729:b0:79f:14de:2a2a with SMTP id af79cd13be357-7a18746e0d3mr545389885a.37.1721292063904; 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[209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7a193990676si8052585a.496.2024.07.18.01.41.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 01:41:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xWFQrn2Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUMgX-0007m4-Cy; Thu, 18 Jul 2024 04:40:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUMgJ-0006xW-5i for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:08 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sUMgH-0004v4-7c for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:06 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-36798ea618bso314414f8f.0 for ; Thu, 18 Jul 2024 01:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721292003; x=1721896803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vcjSxPAzKxhH+dpnOyTqicwIlTcohXs+GfUPxVSqVy8=; b=xWFQrn2ZO/VnM5Lz1Ld/Z1fKxpdvtWj1fugBcoKaALj1hF0ClfiZO5pA9chSJbE18B cFzuvWjh5iKOP6j/gUzQTcsvjdk3pAy1ualvU7poiyN47zrXR5xQATjhuHjHpuyI0giu WBhEULfkARknpL4O98VnCRwFo0oqd2fLmTEKsLuddxs/2pOlYFOzHKgd+x+jIegcPLzi /mtm4iUhQ5SmiIsitNfpwRDIh85lp/Cb1qObfLPrV/cWdmgvDhCOs+AdOcDG/na6w2Va gK2WhDmPLCduZR26UjwzWuOtYocetpWikHdarl0W6Lkwc3aFNj1gIrd+UQBb26HQt40r c+SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721292003; x=1721896803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vcjSxPAzKxhH+dpnOyTqicwIlTcohXs+GfUPxVSqVy8=; b=wNFK9MlEkODbY1nyQHP2RthJD/9t5s1/6NhjZKZBqX4GEg0nYTXo9+dgSAXKnZ7aoH Fvy3hkJSoE2KYyGnaPFkoxYI2XmcaNQqOMdnIGRNrg38LE2nlN2wxnjWynS1SjRXPu5G lNDEtoeEym0juKTuygjzIgnzFq0yoLLkjel2XZlzQQU0wQy8HxQm9SPwdA4s57+UKmO6 xO1SNdVWndwoFqB+VPPhz/dmitGByKT6CBdglCjv9eixVgmKjdSyHX14A/UOrU9luMSR cfPWep/2GwdBq64wskZ4MKFsF40Y7UdeGWiIlzyfiENCq89ymV34LYjmh1FohNeP+9o1 kjIw== X-Gm-Message-State: AOJu0YytpxkdN37ZJlR4j9lRt7MhpBMIPVkujyWvfmL0r7O1gPlehVIe EVznkmvl7cpnBz+AOq4UQcI7UNCtRry2TKQrNMyJ+KO/v9cBA/8cFCaC6dhscto2h1mPPJF3o4v K0/c= X-Received: by 2002:adf:9b86:0:b0:368:3f6a:1dec with SMTP id ffacd0b85a97d-3683f6a1fc2mr2024381f8f.9.1721292003209; Thu, 18 Jul 2024 01:40:03 -0700 (PDT) Received: from localhost.localdomain ([176.187.208.21]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680daccad8sm13651982f8f.60.2024.07.18.01.40.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 01:40:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 10/18] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data() Date: Thu, 18 Jul 2024 10:38:34 +0200 Message-ID: <20240718083842.81199-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao In order to get LoongsonIPICommonClass in send_ipi_data() in the next commit, propagate LoongsonIPICommonState. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index f3d1f031bc..a54db87638 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -88,8 +88,8 @@ static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) return NULL; } -static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, - MemTxAttrs attrs) +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) { int i, mask = 0, data = 0; AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); @@ -119,7 +119,8 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, return MEMTX_OK; } -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -134,10 +135,11 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; hwaddr addr; @@ -152,7 +154,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) /* override requester_id */ addr = val & 0xffff; attrs.requester_id = cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); + return send_ipi_data(ipi, cs, val, addr, attrs); } static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, @@ -249,15 +251,16 @@ static const MemoryRegionOps loongson_ipi_iocsr_ops = { static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { + LoongsonIPICommonState *ipi = opaque; MemTxResult ret = MEMTX_OK; addr &= 0xfff; switch (addr) { case MAIL_SEND_OFFSET: - ret = mail_send(val, attrs); + ret = mail_send(ipi, val, attrs); break; case ANY_SEND_OFFSET: - ret = any_send(val, attrs); + ret = any_send(ipi, val, attrs); break; default: break; From patchwork Thu Jul 18 08:38:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813147 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp189053wro; Thu, 18 Jul 2024 01:41:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWJIAN8apgBUu4JU4uxVbjsqCt7lRhtE2dfMajozeJXNWvMIYkDRcKbPN6X1D4Uxp1S0LrzgYVQowCev5ojOC3t X-Google-Smtp-Source: AGHT+IEfZCNEwy43HZr3dgfWrXqqQlwRb3xw/DiWjVWXDwCbq3a2ojgIlDAh5JxkscnfQ/FW1G9/ X-Received: by 2002:a05:6102:8007:b0:48f:8b6b:75a3 with SMTP id ada2fe7eead31-491598b1ff7mr5432529137.8.1721292092525; Thu, 18 Jul 2024 01:41:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292092; cv=none; d=google.com; s=arc-20160816; b=EjdT+zjjXXHFkBMyL3NNjIwaW7U3dS66WVzpe9hgl/UPjYjTHNefctrFk2hSOYbHUH X58PqVsDO9m4Mkc9UPMIIm9WhPgD7C5QFs/9VA4IepGnK8lGeM7spxWmP/2ssxB7Aof1 r0tutpYqcPYVr3bxl+/G6F0lMfW3xtmPJVVoQJjt7KOsETtENFAjKGGKrHMHlassdzvT ToMVCJRScVXYXzwQGnF8MZ/o5TOPuwedpJuS8fjdn+eK8a79YRD8ta1kovLGNDrXPQL1 /Pr+JoGQgGrh2dnn3ME7d5gFT42moc+sZQBbU6kKVUK35k+t+80AoY8lMN3LPVgx2Rap XC6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2fEZNDPPoxKFs7H+NykCV578N/mSSTlQ4AcK8WKF7wg=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=Uv26y/Wu7LONEFALatzQGNZTKNlC3XHSFwvma6gBhh2O1cQiguCGJBCWWn6asvXYlP Ap4zwFa8CC+hykj++wePFI+QIavTs61pv4vw4wGl7DAzGfSA8ck+vEkrqEPXSxX2FyTV 4miRzsi1IsA6R7yxZdXUMU76Pr05k5vuBi6OMjxtpTpye7eoo7Ueeoa8MPRMIzQBBEgx XCD5/1ZPwgPirqRxmdIZy7th5o32ZhPjM2r+LH8TQfdN7zU/LyALXaST9Ph80B7qG8IA b6F+powQCk1JkQrQOGqHwYYcw8yfGF4PZ2bdi3hNo5Vltli1jOLJ6hssMzA/p5//xklz A/xA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uTZ4wTLc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi_common.h | 2 ++ hw/intc/loongson_ipi.c | 16 ++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 891b43644d..e49c156db3 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -39,6 +39,8 @@ struct LoongsonIPICommonState { struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; + + AddressSpace *(*get_iocsr_as)(CPUState *cpu); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index a54db87638..2c8829c3cc 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -75,24 +75,30 @@ static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, return loongson_ipi_core_readl(s, addr, data, size, attrs); } -static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) -{ #ifdef TARGET_LOONGARCH64 +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} #endif + #ifdef TARGET_MIPS +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { return &MIPS_CPU(cpu)->env.iocsr.as; } -#endif + return NULL; } +#endif static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, uint64_t val, hwaddr addr, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int i, mask = 0, data = 0; - AddressSpace *iocsr_as = get_cpu_iocsr_as(cpu); + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); if (!iocsr_as) { return MEMTX_DECODE_ERROR; @@ -338,9 +344,11 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); device_class_set_parent_realize(dc, loongson_ipi_realize, &lic->parent_realize); + licc->get_iocsr_as = get_iocsr_as; } static void loongson_ipi_finalize(Object *obj) From patchwork Thu Jul 18 08:38:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813139 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188733wro; Thu, 18 Jul 2024 01:40:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVbhlBZSIKtMHWMJB67OAXf3TH4AHTGOAUcC/M8MWCOO3TwjKh6aJUqy6sHNIpJrLYEJzg90V+jAQpxFV4KLSkr X-Google-Smtp-Source: AGHT+IHI6BfnumjFN0MB4G2yHPUTn8gUw5MFr/3GVWI10EjImRhB5olteVgSnZXyvHTMYTIV2d5Y X-Received: by 2002:a05:620a:191d:b0:79d:6039:784c with SMTP id af79cd13be357-7a18745fb4emr497195085a.30.1721292030107; Thu, 18 Jul 2024 01:40:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292030; cv=none; d=google.com; s=arc-20160816; b=Xl9PE5ZASUg2eKU4XmJPIUuWaiJcTO2OjqcckanBtrsLWN8e0QydXSqe8oFspTBfhG 8rSLJMuEsTyYw1IAcKZtyfmbTeV3mvR++EhuPKdknEK3E8tUHnwK8mfQzxekHxa/KY/v lNY3y7cEM8S6yIS/Xa+uoHCaV6XQXoFchRYxBmrBl30pqCNcL0kiz6lcbg9xvo0m9Rpk 32VlG8apLZOIb7OJThqLJkRQw8ZMF5qgVK0pGYrTbKVQ2McAuiWckoe7zEOsy5wb0uaL d4t/X9GkTCCPB3annPMOgSH5s0up3aKkckrTIgX9Uv8/tUJDAufpJKGp9++dNcTX/YcE cthQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jW541QXlMDLOV+DwTuPovPBUePRuwd+f2A4/2HtxxX0=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=dDTOQZ3vT8wkGeQgTR3UUIpQaZ0cokDsQ9+moU2kX5GPTnCrhVVYfKXnVczhKjqTP/ o4+V9+7FMo+QDIzstjaJjylhLqwyBuf/T3ydreG22dyMB4wNePysUHBPpFaXFBbc++Yi wqerTaH8ER/FXP/IgtDnBLA8l+cmemmh3TMt9+GfKS6Ufv6vHH7F6CmqSROI1EFfLWcY OnDgXWgXqcrb6cJfV2Gn0UpWQJLB8hZC04+GtqW9vSVCUKlLuG49kGe5Sc14PKZfULkp fbwRHt8nQ2U0OvTQMsD6GHjgDCDbhLUPejnSNAa0y/ZKSy0DtAeAPo4ZXVgANpKJKMoK 6aOw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CuDoV8aJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi_common.h | 1 + hw/intc/loongson_ipi.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index e49c156db3..5447e9f650 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -41,6 +41,7 @@ struct LoongsonIPICommonClass { SysBusDeviceClass parent_class; AddressSpace *(*get_iocsr_as)(CPUState *cpu); + CPUState *(*cpu_by_arch_id)(int64_t id); }; /* Mainy used by iocsr read and write */ diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 2c8829c3cc..39bcf0031d 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi, static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val, MemTxAttrs attrs) { + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); uint32_t cpuid; hwaddr addr; CPUState *cs; cpuid = extract32(val, 16, 10); - cs = cpu_by_arch_id(cpuid); + cs = licc->cpu_by_arch_id(cpuid); if (cs == NULL) { return MEMTX_DECODE_ERROR; } @@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); int index = 0; uint32_t cpuid; uint8_t vector; @@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, cpuid = extract32(val, 16, 10); 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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-44f96ac42bbsi785311cf.691.2024.07.18.01.41.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 01:41:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d3jthEd5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUMgs-0001op-BD; Thu, 18 Jul 2024 04:40:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUMgg-000130-3s for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:30 -0400 Received: from mail-lj1-x235.google.com ([2a00:1450:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sUMgd-0005FH-W0 for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:29 -0400 Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2eedec7fbc4so6998521fa.0 for ; Thu, 18 Jul 2024 01:40:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721292026; x=1721896826; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6UPq27AY4GIf4EDDpmU+ZO9tTp1hi1LFdlwBIRXsUDE=; b=d3jthEd5Co/UPul0LFOTpB/Q2CXBGc+HQj8OU66S4MyiUkNDo+ME83vKLr5imAxQw4 6EihMxbLYl5FZsgD77szE6uLZ8uZXzhTdOUWe/axHQz2vE7meaC+DkK9MVj0wAxdA+Cp 6eo8IQC/AceCNuXbRPdOoALM7+zqHYGZMSYLOeAec2lyXHU8zaK3mEySh47V9rQITS7J MUNW2mtK58Qdy7u0d6xX53DVtgMn9mNqf6Zi/5jPEuuvFZdMl1tzN/DHCJFdWy8DYiME +T0RfUPb0xzu3rBJ3Ax+pMWZqg3DSIf5+rM/Ls+tmzsQluaE3YpJNxju5Zo5qdhqMNpG nDbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721292026; x=1721896826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6UPq27AY4GIf4EDDpmU+ZO9tTp1hi1LFdlwBIRXsUDE=; b=tEEMG3mMMfvLDu3BYgwd3t7NBPceGHVxQO+oeD7ygDzNlVkxzKGOvy5YvrmuI4ZY5L ebamtuRSKNq2fhY6U+x1gZoxGqUbJMXRNXj7pTf917qLa+OqNjK/DbPW0GV5yX9a6zgo 8TEBiRM2Im/+iCTwdIDxfnIQ5jcnV9Q6zfvFKYiROwnes+Rw7obcGHef1e5dLI0zrBQf M+OE3MrgvIoSDYtgT/eAZgIgfYnk1xaOoOGxgfaNmjSTP+NtnV24IF+qkQ4r61nsawIA fRuKeLp6cRMc8zUDQcBpnI1edEVrP/1iZdFIZxKMzkyGbg0T1NcsxwCh13SEoYmVwEQW ViIw== X-Gm-Message-State: AOJu0YzvXmshfV34IOInabjKHgP3m4s2Jeb+gHkci8N++z24WLvSHd9U hJurcQxLwbelh7mEA9uUhi39QlhMvHXQ/Yrp89x/piYMgbsXMO8mirej7DURjSHc8TsFBr5goJU wEc8= X-Received: by 2002:a2e:9888:0:b0:2ee:e0a1:c496 with SMTP id 38308e7fff4ca-2ef05c57438mr11915131fa.9.1721292025720; Thu, 18 Jul 2024 01:40:25 -0700 (PDT) Received: from localhost.localdomain ([176.187.208.21]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2a9ff5dsm2018875e9.0.2024.07.18.01.40.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 01:40:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 13/18] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers Date: Thu, 18 Jul 2024 10:38:37 +0200 Message-ID: <20240718083842.81199-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=philmd@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao In order to access loongson_ipi_core_read/write helpers from loongson_ipi_common.c in the next commit, make their prototype declaration public. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/intc/loongson_ipi_common.h | 6 ++++++ hw/intc/loongson_ipi.c | 10 ++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index 5447e9f650..a75882f775 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -10,6 +10,7 @@ #include "qom/object.h" #include "hw/sysbus.h" +#include "exec/memattrs.h" #define IPI_MBX_NUM 4 @@ -44,6 +45,11 @@ struct LoongsonIPICommonClass { CPUState *(*cpu_by_arch_id)(int64_t id); }; +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs); +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs); + /* Mainy used by iocsr read and write */ #define SMP_IPI_MAILBOX 0x1000ULL diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 39bcf0031d..a2db8bb2e2 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,9 +24,8 @@ #endif #include "trace.h" -static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; uint64_t ret = 0; @@ -165,9 +164,8 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi, return send_ipi_data(ipi, cs, val, addr, attrs); } -static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) { IPICore *s = opaque; LoongsonIPICommonState *ipi = s->ipi; From patchwork Thu Jul 18 08:38:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813149 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp189086wro; Thu, 18 Jul 2024 01:41:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXONrRTVCiEraBfTwfwOjnMHdHEXC5UCObaVe/XccmQE3159ItB1L81kvEedXjn6n3YL/Efp8Za0tTg07X0Y5uh X-Google-Smtp-Source: AGHT+IFngQWvKu1lABLJIVdbZZkxU8ZpiZUw0EAlt6GTKiKKlEPOMUAuesSRFEwXY9mcKT8/rKB8 X-Received: by 2002:a05:622a:293:b0:447:efa4:64eb with SMTP id d75a77b69052e-44f96a56f46mr1667591cf.53.1721292097979; Thu, 18 Jul 2024 01:41:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292097; cv=none; d=google.com; s=arc-20160816; b=L39gmyRdubWLmSxvqSmBlzyg8KQ+WKN8ySz3cV+NQV0VBILlVjLGIlEZQH5Yu/nsy7 x32UEi7nAN83tiLP3VAXQ803u7OiW/TCMXqgnVT0GdGtGh9pfE7+GYlpLt7NEfyfBEk6 HClEKeEPnuRpZm3ZbldHSurtm7A55fLZKxaJmNp9mefxmyHGws0rGvCAsB7rrdcBqsHU DiM3JiVpMhPes+UOHkUmVLx0V5wsyLvyjbFK/pR1yaJTe8vRp1VWLO3nKvW24ISMOMKY Yd4Op8pKNb+S9/3tSVxTMSZb09YvYMXSohZjVnF/pTxndcvqe2ZBPE8RyWtr8DKHucH1 yY3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QAAADLqB/ywse+fbm4/hNi0SZ7JLjPzn4jkX3T2CABk=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=E6z09g+NFkiIPGq5vB203nK5ec86Xe8iNW+svpd1EoR50E2Rky7fGvmKvKsE2wJb2Q nde+H9exAsWMP7rLJWrq8wNkLEp5E96hzEh/WwBf8aC5w6IcAZ91UsrC0L4/Fc8mGdLy RuEBCINK/dxg9pLgulO5lOgzDu+3QgripeMVr+xl3z58LlszIFrc3SNEnKncm5ubuizx RmGGKopoUTzH/hbs86n+QTu4bHo069D+EsoSt9aqhB1JjbxIeTCQqN3Es9PVDhcf1OEz l+1mDzbMTNYy6jEJ1Wexoy98KSwue/6TUYcBDLRE13jDZuj4OAYRJ9IEIl2bbE8q7O0z xH+g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MWtphYh2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 269 +-------------------------------- hw/intc/loongson_ipi_common.c | 272 ++++++++++++++++++++++++++++++++++ 2 files changed, 274 insertions(+), 267 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index a2db8bb2e2..86badb2972 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -24,56 +24,6 @@ #endif #include "trace.h" -MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - uint64_t ret = 0; - int index = 0; - - addr &= 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret = s->status; - break; - case CORE_EN_OFF: - ret = s->en; - break; - case CORE_SET_OFF: - ret = 0; - break; - case CORE_CLEAR_OFF: - ret = 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - ret = s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongson_ipi_read(size, (uint64_t)addr, ret); - *data = ret; - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_readl(s, addr, data, size, attrs); -} - #ifdef TARGET_LOONGARCH64 static AddressSpace *get_iocsr_as(CPUState *cpu) { @@ -92,148 +42,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) } #endif -static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, - uint64_t val, hwaddr addr, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int i, mask = 0, data = 0; - AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); - - if (!iocsr_as) { - return MEMTX_DECODE_ERROR; - } - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); - for (i = 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |= 0xff << (i * 8); - } - } - } - - data &= mask; - data |= (val >> 32) & ~mask; - address_space_stl_le(iocsr_as, addr, data, attrs, NULL); - - return MEMTX_OK; -} - -static MemTxResult mail_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -static MemTxResult any_send(LoongsonIPICommonState *ipi, - uint64_t val, MemTxAttrs attrs) -{ - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; - return send_ipi_data(ipi, cs, val, addr, attrs); -} - -MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s = opaque; - LoongsonIPICommonState *ipi = s->ipi; - LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); - int index = 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - addr &= 0xff; - trace_loongson_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en = val; - break; - case CORE_SET_OFF: - s->status |= val; - if (s->status != 0 && (s->status & s->en) != 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &= ~val; - if (s->status == 0 && s->en != 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index = (addr - CORE_BUF_20) >> 2; - s->buf[index] = val; - break; - case IOCSR_IPI_SEND: - cpuid = extract32(val, 16, 10); - /* IPI status vector */ - vector = extract8(val, 0, 5); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, - BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - IPICore *s; - - if (attrs.requester_id >= ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s = &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_writel(s, addr, val, size, attrs); -} - static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, .write_with_attrs = loongson_ipi_core_writel, @@ -244,88 +52,15 @@ static const MemoryRegionOps loongson_ipi_core_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static const MemoryRegionOps loongson_ipi_iocsr_ops = { - .read_with_attrs = loongson_ipi_iocsr_readl, - .write_with_attrs = loongson_ipi_iocsr_writel, - .impl.min_access_size = 4, - .impl.max_access_size = 4, - .valid.min_access_size = 4, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, - unsigned size, MemTxAttrs attrs) -{ - LoongsonIPICommonState *ipi = opaque; - MemTxResult ret = MEMTX_OK; - - addr &= 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret = mail_send(ipi, val, attrs); - break; - case ANY_SEND_OFFSET: - ret = any_send(ipi, val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongson_ipi64_ops = { - .write_with_attrs = loongson_ipi_writeq, - .impl.min_access_size = 8, - .impl.max_access_size = 8, - .valid.min_access_size = 8, - .valid.max_access_size = 8, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) -{ - LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu == 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), - &loongson_ipi_iocsr_ops, - s, "loongson_ipi_iocsr", 0x48); - - /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard = true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongson_ipi64_ops, - s, "loongson_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu = g_new0(IPICore, s->num_cpu); - for (i = 0; i < s->num_cpu; i++) { - s->cpu[i].ipi = s; - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - static void loongson_ipi_realize(DeviceState *dev, Error **errp) { LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); LoongsonIPIState *s = LOONGSON_IPI(dev); + LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *local_err = NULL; - loongson_ipi_common_realize(dev, &local_err); + lic->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 3b9e5c943d..015f86c066 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -8,8 +8,279 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" #include "migration/vmstate.h" +#include "trace.h" + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + uint64_t ret = 0; + int index = 0; + + addr &= 0xff; + switch (addr) { + case CORE_STATUS_OFF: + ret = s->status; + break; + case CORE_EN_OFF: + ret = s->en; + break; + case CORE_SET_OFF: + ret = 0; + break; + case CORE_CLEAR_OFF: + ret = 0; + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + ret = s->buf[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); + break; + } + + trace_loongson_ipi_read(size, (uint64_t)addr, ret); + *data = ret; + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, + uint64_t val, hwaddr addr, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int i, mask = 0, data = 0; + AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); + + if (!iocsr_as) { + return MEMTX_DECODE_ERROR; + } + + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); + for (i = 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |= 0xff << (i * 8); + } + } + } + + data &= mask; + data |= (val >> 32) & ~mask; + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); + + return MEMTX_OK; +} + +static MemTxResult mail_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +static MemTxResult any_send(LoongsonIPICommonState *ipi, + uint64_t val, MemTxAttrs attrs) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid = extract32(val, 16, 10); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr = val & 0xffff; + attrs.requester_id = cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s = opaque; + LoongsonIPICommonState *ipi = s->ipi; + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); + int index = 0; + uint32_t cpuid; + uint8_t vector; + CPUState *cs; + + addr &= 0xff; + trace_loongson_ipi_write(size, (uint64_t)addr, val); + switch (addr) { + case CORE_STATUS_OFF: + qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); + break; + case CORE_EN_OFF: + s->en = val; + break; + case CORE_SET_OFF: + s->status |= val; + if (s->status != 0 && (s->status & s->en) != 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status &= ~val; + if (s->status == 0 && s->en != 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index = (addr - CORE_BUF_20) >> 2; + s->buf[index] = val; + break; + case IOCSR_IPI_SEND: + cpuid = extract32(val, 16, 10); + /* IPI status vector */ + vector = extract8(val, 0, 5); + cs = licc->cpu_by_arch_id(cpuid); + if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); + break; + } + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + IPICore *s; + + if (attrs.requester_id >= ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s = &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_iocsr_ops = { + .read_with_attrs = loongson_ipi_iocsr_readl, + .write_with_attrs = loongson_ipi_iocsr_writel, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +/* mail send and any send only support writeq */ +static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi = opaque; + MemTxResult ret = MEMTX_OK; + + addr &= 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + ret = mail_send(ipi, val, attrs); + break; + case ANY_SEND_OFFSET: + ret = any_send(ipi, val, attrs); + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps loongson_ipi64_ops = { + .write_with_attrs = loongson_ipi_writeq, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpu == 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, + s, "loongson_ipi_iocsr", 0x48); + + /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ + s->ipi_iocsr_mem.disable_reentrancy_guard = true; + + sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); + + memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), + &loongson_ipi64_ops, + s, "loongson_ipi64_iocsr", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); + + s->cpu = g_new0(IPICore, s->num_cpu); + for (i = 0; i < s->num_cpu; i++) { + s->cpu[i].ipi = s; + + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} static void loongson_ipi_common_finalize(Object *obj) { @@ -53,6 +324,7 @@ static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = loongson_ipi_common_realize; device_class_set_props(dc, ipi_properties); dc->vmsd = &vmstate_loongson_ipi; } From patchwork Thu Jul 18 08:38:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813150 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp189091wro; 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It can be used when ipi is emulated in userspace with KVM mode. Signed-off-by: Bibo Mao [PMD: Rebased and simplified] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao --- include/hw/intc/loongarch_ipi.h | 25 ++++++++++++ hw/intc/loongarch_ipi.c | 68 +++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 4 ++ hw/intc/meson.build | 1 + 4 files changed, 98 insertions(+) create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 hw/intc/loongarch_ipi.c diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h new file mode 100644 index 0000000000..d134c9d0c7 --- /dev/null +++ b/include/hw/intc/loongarch_ipi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongarch ipi interrupt header files + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_IPI_H +#define HW_LOONGARCH_IPI_H + +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" + +#define TYPE_LOONGARCH_IPI "loongarch_ipi" +OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) + +struct LoongarchIPIState { + LoongsonIPICommonState parent_obj; +}; + +struct LoongarchIPIClass { + LoongsonIPICommonClass parent_class; +}; + +#endif diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c new file mode 100644 index 0000000000..ccbfad07b7 --- /dev/null +++ b/hw/intc/loongarch_ipi.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongarch ipi interrupt support + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/intc/loongarch_ipi.h" +#include "target/loongarch/cpu.h" + +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ + return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} + +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a = (CPUArchId *)a; + CPUArchId *archid_b = (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, + sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +{ + MachineState *machine = MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid = find_cpu_by_archid(machine, arch_id); + if (archid) { + return CPU(archid->cpu); + } + + return NULL; +} + +static void loongarch_ipi_class_init(ObjectClass *klass, void *data) +{ + LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + + licc->get_iocsr_as = get_iocsr_as; + licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; +} + +static const TypeInfo loongarch_ipi_types[] = { + { + .name = TYPE_LOONGARCH_IPI, + .parent = TYPE_LOONGSON_IPI_COMMON, + .class_init = loongson_ipi_class_init, + } +}; + +DEFINE_TYPES(loongarch_ipi_types) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index a2a0fdca85..dd405bdb5d 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -94,6 +94,10 @@ config LOONGSON_IPI bool select LOONGSON_IPI_COMMON +config LOONGARCH_IPI + bool + select LOONGSON_IPI_COMMON + config LOONGARCH_PCH_PIC bool select UNIMP diff --git a/hw/intc/meson.build b/hw/intc/meson.build index a09a527207..f4d81eb8e4 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -71,6 +71,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c')) From patchwork Thu Jul 18 08:38:40 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-44f96ad324bsi807911cf.762.2024.07.18.01.41.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jul 2024 01:41:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VakErUWC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUMh1-0003Lx-JL; Thu, 18 Jul 2024 04:40:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUMgz-0002ry-KZ for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:49 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sUMgx-0005Qd-PG for qemu-devel@nongnu.org; Thu, 18 Jul 2024 04:40:49 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4266ea6a488so518555e9.1 for ; Thu, 18 Jul 2024 01:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1721292046; x=1721896846; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ro2UkiIljPYm3x7SryacRuC51Y6LajCjN+Iei/DvqiY=; b=VakErUWCn+umKejbK6lmo1TMA5zsrntyFvUF9jSATZ1Sss1P/TJ+1aYugonkCgnQ1L DDT1wpBMF2tiN8051MalXNzynAQjoghAg8vhrk6xhnfnSJ9kYbvmegsqcoFnEd7OMoEo ugV+2x5nHlrdQQZHk1SdOaYWTw0Bigovg0j3fJSAKZ/7bEi0gu+5LHNUYlF7PWvRbehf /3sHnvCExdyCw685504cmGELkqWuHzYH0GetVCQ72itnCHg0sF3HL83Z2Cr1I0TTO2ro xPZPasmrdw1QPBXuIEdSxk1CSbFtlrk8a1Bi9Pdk7QIjlTSZvHpniK6Br0qSkfSS0hAc I7cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721292046; x=1721896846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ro2UkiIljPYm3x7SryacRuC51Y6LajCjN+Iei/DvqiY=; b=bUFyFSY1575ei8de7D/GfXLc8l+NVSgLM/s735O5Ss8OWHEgdzicYGthTs3D0f8vnf ZmDwDE4Z9zs+rwLJUemyg4i3T/ZR9lsz/ckGW+fSm+fIFVhDEYfXDwriiPH/rT5nofX8 S9LBF7L+Gg7deGn2CyE7uDz8oUPRwhnWYx07gTRwVRJJ6McWGHPKUDxY1ovuSQt92CGN HY2ICEDe+rNvHRgSxyRx4kknaTPiL0enSSgfli8jVWwUToxFi6MYnoGHyZzofJdjIOGV 1nV3V8HzIara7jVPpd0WgzOnqhdfmsjJIFZkd6152Vuh2iM2apIkrBQ7xkxUqrfBfHQo FY7A== X-Gm-Message-State: AOJu0Yxz4qCaiNAzF2cA3glrgdotNqMgQOwfRw8PXO0mlMdSXahwI/wV jBA2q/dwepBUfFXpbzIRoSxxu59jBvpPD4XTlrAs3JxHLzdnQHVoUiMgJLwTe7/CU+tA/iVhRH/ Y98s= X-Received: by 2002:a05:600c:1d20:b0:426:6ed5:fcb with SMTP id 5b1f17b1804b1-427c2cad3c2mr34526435e9.4.1721292046177; Thu, 18 Jul 2024 01:40:46 -0700 (PDT) Received: from localhost.localdomain ([176.187.208.21]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427d2b29678sm1385875e9.36.2024.07.18.01.40.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jul 2024 01:40:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 16/18] hw/loongarch/virt: Replace loongson IPI with loongarch IPI Date: Thu, 18 Jul 2024 10:38:40 +0200 Message-ID: <20240718083842.81199-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- include/hw/loongarch/virt.h | 1 - hw/loongarch/virt.c | 4 ++-- hw/loongarch/Kconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..91216418c8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e592b1b6b7..29040422aa 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) */ /* Create IPI device */ - ipi = qdev_new(TYPE_LOONGSON_IPI); + ipi = qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 89be737726..0de713a439 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -12,7 +12,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS - select LOONGSON_IPI + select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI From patchwork Thu Jul 18 08:38:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813148 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp189059wro; Thu, 18 Jul 2024 01:41:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV6rJq8QKLtIOQWNq+rKiGOVl/URZHzz6dQASgAT9kr9bk6HdQjXtBb5XT2i7M8JZjUcV/tgrVStgkLSgss+po6 X-Google-Smtp-Source: AGHT+IGgfW4NaeSJ5NG2Bhk5nFRZ1dBZ0A4fSWAJyr8ZTh1mALezFySC3zs9jjmAogj5xRE/npTg X-Received: by 2002:a05:620a:4541:b0:795:4a3b:3c16 with SMTP id af79cd13be357-7a1874e4538mr450097485a.48.1721292093860; Thu, 18 Jul 2024 01:41:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292093; cv=none; d=google.com; s=arc-20160816; b=Df/k3LMb6QzrShibwzBW2Bsfjc1tQbl9IHYH+W104rOyLEoSeAFbawuDzwjEYgEzEL /54r6bmj9sxupbS8NP6ozqP+jOzaEHQqLpRHSViPpwg5i6Z0cmChdtaG/siZBZ2LuzIg RLxhwTkt0Fg0R8iO3SLURpYgCqCD1w2h/fDZu86xxyJdRBI5whmNNaG6FqaeXZOvNI/n 46RD/9YucEkZUxwzkXD5OtClyTUW5+NwC24wJg4+UdX6vapHNBQLPLswWbePdgAtJ8OJ o0gWZYrzo0P4SUrMm7Hda6kntBg8gvg90G5vvWiQMQ3NC0eWgCQGBpAn+9q8eQ/XuTPo PTVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OMNRRhSeVfqG/kjcaEtJKlT+Vgh7L7Gt4XuPo4Meh2s=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=Vs6r4zjSexfUccnH6u6Lgzu3bxYxJcvo0c9LuwgiRXZ1LvJFpDLulw8rTlFI/GUTYd OZwb9CQ1TmYfYSpJO2CSTornex8rmoC5UpgPN1hywY4ItMLBqVUcSTJWcNa/AkNQ+SVJ 2KbvqPQowZkFEds5SH645LucsYdshh8nF2/LE4wIMv2KnHo9/PUzyZ5kPP+cYM/skkOJ tIRCwh6gVhmk5/L1m+3uRUshD/9Bvq8cE9jSu2yY8uTwfORjkomrQ4DmezHkJc5B63yE 0Xa+hp8v8W2bZk+FUrfi4FgOtXOlepYo8xDIef4wH/XSQawSb+T0r096MqsvTT/EPl7w WPSQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pcmdOx7k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- MAINTAINERS | 2 -- hw/intc/loongson_ipi.c | 14 -------------- 2 files changed, 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a670c8ee67..c2d51b0158 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1250,10 +1250,8 @@ F: hw/loongarch/ F: include/hw/loongarch/virt.h F: include/hw/intc/loongarch_*.h F: include/hw/intc/loongson_ipi_common.h -F: include/hw/intc/loongson_ipi.h F: hw/intc/loongarch_*.c F: hw/intc/loongson_ipi_common.c -F: hw/intc/loongson_ipi.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c F: gdb-xml/loongarch*.xml diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 86badb2972..051e910586 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -16,22 +16,9 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "migration/vmstate.h" -#ifdef TARGET_LOONGARCH64 -#include "target/loongarch/cpu.h" -#endif -#ifdef TARGET_MIPS #include "target/mips/cpu.h" -#endif #include "trace.h" -#ifdef TARGET_LOONGARCH64 -static AddressSpace *get_iocsr_as(CPUState *cpu) -{ - return LOONGARCH_CPU(cpu)->env.address_space_iocsr; -} -#endif - -#ifdef TARGET_MIPS static AddressSpace *get_iocsr_as(CPUState *cpu) { if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { @@ -40,7 +27,6 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } -#endif static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, From patchwork Thu Jul 18 08:38:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 813144 Delivered-To: patch@linaro.org Received: by 2002:adf:f288:0:b0:367:895a:4699 with SMTP id k8csp188973wro; Thu, 18 Jul 2024 01:41:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVOhmOBuTzHsu6PRnaOGNVHsctHwryK38RDf9GfVFDuDBc0nQ80DGDBrxJ7AeJHmdakwk/4lkyLSri2SNEXjH2r X-Google-Smtp-Source: AGHT+IHP+28w1BNY8dAn59aw7zPRuzTcs5rt66UgaoWDzTv76F3f9ModxZ201GvxxYDoK1m1A+So X-Received: by 2002:a05:620a:1aa6:b0:79f:d0f:2b1f with SMTP id af79cd13be357-7a19398e860mr16774085a.61.1721292076588; Thu, 18 Jul 2024 01:41:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721292076; cv=none; d=google.com; s=arc-20160816; b=PymbVrr0giZKkBhqTxIiSmNaSocXTgRqrd+jHVSRl5ZIIzulZZxJjPSZRcXMWKkhV5 /1PWVPijv8YX+Ud1yKs0sfvtQQHmnub/X/3xPPRL7EqGKKXIRR2r3U3TAUCeHaKBJnNj RyPp4xVeVNBTBkW/zhmusKts1ePz/F1sTeEFqeCYlMb0igg5YDwlBw4f4MjAUnRLmDp1 +/VmvrEn9nO61gGu4Ik3LuUrSKGFFTWWfQJ+iFmFTzBYsMmO+9JNEhTG0EzvDuq/BEM0 00UWmIXZWGH/P8rPewtORF5miOvImCnarFvywpHtAIyTo16IpC1ZxZ4bHgeG7sDx472O l1yQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qfZ0l+YnojhbfUi6GMDiZJfhxTY9uxe9srgMx+ZIAtg=; fh=NLZWUfvz+g+MnoIWE6nGov3chqHrPo6wetxAC/CDqtI=; b=K9Hc4RvWo0dfHzD69q5Fq880c3qSyyTUy6abCgvuzOcfNFZGGXcP8xStehPsxlmJhQ 3MGiBR78mO5Iw58jWLefEEik5RK9aO86RFR9zlWVWmefZ8G2DAtmSEAVCEg5OCKDWHwW 90o8dEcvOatar8YylaY9WNvWU3z8yP4MpmsLojIVvb7vJ9TfIUV5f/Uz9C8id5ZRHqc1 IUz5DaLsBdjIr2bGGOT/hnLy23bBWgLWpYaoAgUXjRuGNRb0kyAxeF/yf5xphcKAj5G9 HS+uTYOA9JOBG7ZFMXlGNs8771WtW1+N0EqOTp760BiNLxzEEOdw4SZ5Wre36ZO+I+Nb Rdyg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ULf/oNrr"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 18 Jul 2024 01:40:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bibo Mao , Jiaxun Yang Cc: Song Gao , Xianglai Li , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Xiaojuan Yang , Paolo Bonzini Subject: [PATCH v4 18/18] hw/intc/loongson_ipi: Remove unused headers Date: Thu, 18 Jul 2024 10:38:42 +0200 Message-ID: <20240718083842.81199-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240718083842.81199-1-philmd@linaro.org> References: <20240718083842.81199-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bibo Mao Tested-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/intc/loongson_ipi.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 051e910586..aa1b0a474c 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -6,18 +6,9 @@ */ #include "qemu/osdep.h" -#include "hw/boards.h" -#include "hw/sysbus.h" #include "hw/intc/loongson_ipi.h" -#include "hw/irq.h" -#include "hw/qdev-properties.h" #include "qapi/error.h" -#include "qemu/log.h" -#include "exec/address-spaces.h" -#include "exec/memory.h" -#include "migration/vmstate.h" #include "target/mips/cpu.h" -#include "trace.h" static AddressSpace *get_iocsr_as(CPUState *cpu) {