From patchwork Wed Jul 17 17:03:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 813043 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FCB1182A40; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=RmILnBnkRThLpk/MyQeWwRtPAt5Ed50+KNQwTc6+gWnLvwI+pGZCMlKli3j+mNLpqQfjYpbUwLG2zD0mnwu/KUet4vyJ8BqQeknVCCzec4dIYVs6bt9aQ6v3Hh1kcVSX/EBp980hnOvMJp3Q8Vu/ECsINcjhnJx0jMiiz1pYPDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=8znAZBcirLJ8Efx48e0wAJqyTm86Mv7/PWdHuyyfnFY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nMDTltQ8Osk20IYNK/BXk95GGOcsfdiybFRkRr7i933igH7641TBpbu0tj7owcdvIa1GE69PDOOu02KQnj0gcMYkhSWCBNgcyecQTFW2pvJw2G2UVvcKrHqjH9jAIEUw59TieuBh4vc50TjmpuR9V5J3jDksc2+oyavJe4T6AG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l4WLFn4k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l4WLFn4k" Received: by smtp.kernel.org (Postfix) with ESMTPS id F2D5FC4AF15; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=8znAZBcirLJ8Efx48e0wAJqyTm86Mv7/PWdHuyyfnFY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=l4WLFn4k4kL7R+8+NA2DXQC3rmJonpCPAJhL46vDYEuuAA8BFFnNBupupAPPp+Ko3 Ywh6fF0gk5otvfS+4JNfPuo0q0pLh3dlkE9pLZkhw8pdwUioIhJH7c8dOYsVUQgyD5 KkOt9z+FHmjRe+zj5tRjFk2dC7qBd2D3Ywhw6I5A2mG95k0zBPjcJbSrP/Yj2SD3Z8 Fdnte0yl2lWIDzGSqgkiqBor8IwFnT1unLETVw8JlZfk5xnSl4VhquW5IuqvK3Ctw7 cGa39VKd/R6UBJBAbPCJv6XdvHKW9lltpIESfFErQM8IkGAR+Y4fa8yoKYMc9Sxwqc vFJ+f+edj1Dfg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9070C3DA60; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:09 +0530 Subject: [PATCH v2 04/13] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-4-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2026; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=ZuN+bx8IKdLBF21t1VI/ja/rCNR5Gv+31UWAdkgegn8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lNOungbljczBVTQEbuVGUsSyBz514OTIUe1 XwRJf+2l0mJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TQAKCRBVnxHm/pHO 9W4TB/4+mQi+zmPUNe4N+A+8BE58IM6mcrr1saFbdM8Fgvd2+J60vl8DNlvStJ3ur9oGHtscFmv G6PqO/JxrE92lN2Ele/1qv4qaYEysMGDrMCuBhq2F1kpui1Pp/G9debqLKR0Mr9biZtF7/GZzjv bRhIxErl2K8zifTUeRXkXC1oGUthAW3obCaDd0aqTd7jBFixvasyMhd0zbmeXxKR2mkaQCbdxOs Tje3RIXecdZk4DuWtL+SevmREnYbMIFSF7OGOTAvbc571M67eq3bSPUNm6rF96ooNapgALrXDdY IehQIrNMwRTmhQYH8Bhm8NP9rDoNEZnwoodxn4j12FhcjbJP X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 11 +++++++++++ Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index 0b5456ee21eb..f75000e3093d 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -42,6 +42,17 @@ properties: default: 1 maximum: 16 + linux,pci-domain: + description: + If present this property assigns a fixed PCI domain number to a PCI + Endpoint Controller, otherwise an unstable (across boots) unique number + will be assigned. It is required to either not set this property at all + or set it for all PCI endpoint controllers in the system, otherwise + potentially conflicting domain numbers may be assigned to endpoint + controllers. The domain number for each endpoint controller in the system + must be unique. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..1226ee5d08d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -280,4 +280,5 @@ examples: phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; }; From patchwork Wed Jul 17 17:03:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 813041 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B2AF18306D; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=IS5WDe7xcQGuH+Nn6nXWD7BBtX1SIW4w5maOD/G3FovrlF8NtFibAc+/zYtmN2GXDYLMJlFns41idiIIzACjNIFcUJu2dNuWP/dPW7DyGeFgbQpedtdK897quTHhQDoCWcy6XlMZn8iEFF9OeAfDbm0X35DQSW8eilpBMDaCZUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=0rGn+aPcpL0pLEHeouG5eEtAwVJpEH+6CnS4Upe21fc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dx2WSfEIt/p7zU7rODwmyYlAbTV2rkBYEULHOPmWxw6jatE0RQPS0DD/jzGUaKnht9oKJm6DrSELlXU0r0A/o4edW+ZHUoXki+XAEY4WxTVy+1g+xR+nTWhZYbsUWiyJzAXqp7h1TUGHE4I5cjcElAVOzN22EDfx+ykvZEDZAUU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pY4cL4l3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pY4cL4l3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 15403C4AF1D; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=0rGn+aPcpL0pLEHeouG5eEtAwVJpEH+6CnS4Upe21fc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pY4cL4l3zdbNEZ7t+o1w6YgflZVzGNhFpjj3dzt/QpJ5RKSgj9gUddvDXn2GhXIc0 q9vhZwWrG9aaK7VKUfXop4iOF5bPOwGImb+GR8NLLSRxGWa4nJAQQW9s2GWRx+3LoR xgB/hIRx3CAbpF3e4vfDooH5fkxXL5WTyW4PELr5RdQw+XNjQ0k/Yt7/cV8R82YA2b u6wYgjQayvQDhyDTajrznJ+PRH14V4mSNXuasBMY76LFixpfvVhojwL6He6Cm96ium 9/kDomnK9fy/7pnfPkfiv8AT/43vMIrXWu8GQXQCvdZEQe2s1Es1ycJERoQ2wiTrvi 9nD/4GIsKRS6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 087EAC3DA62; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:10 +0530 Subject: [PATCH v2 05/13] PCI: endpoint: Assign PCI domain number for endpoint controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-5-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3043; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=RgNx60ASNj1W+S8yTFl/XDFmb63UnDz74gKp1lFMkIw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lNJr0HPlA1u3KlDHSrQVmia8YznHXb4MGCI eq+KVVpCtqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TQAKCRBVnxHm/pHO 9c1MCACf1G9ULGICZoGu33tG6Da4yMhnoVZQjnNzAGUwjufpNwuc57Ze/yb8vcYtVdyV2KjvcjX o+sBZj0mbpbo5lOVD3A8/MLJppD2S1Bb3OEmPpHHkS5T8fIDxxgs+RBXEUriO6Ebl1hNkplz/c4 7LT1QmMbpF5+94YFGvgalfAy3rsjOZFp5rVxHC023qBvNY6CAQkjbic6wEFJOgjMsBM9BQA3CdJ w74vH+FZ2zuG3n1wCXTgMQBa9xfgFTuCD3ycjuaS/YzakIwGTi8WNH8s6n62TKSD2Dj7OjTmZXP HEi3phA1+SkPddEz41ZiSCOp0YYI3o5DnWg4FjV1KdJcnBfT X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Right now, PCI endpoint subsystem doesn't assign PCI domain number for the PCI endpoint controllers. But this domain number could be useful to the EPC drivers to uniquely identify each controller based on the hardware instance when there are multiple ones present in an SoC (even multiple RC/EP). So let's make use of the existing pci_bus_find_domain_nr() API to allocate domain numbers based on either Devicetree (linux,pci-domain) property or dynamic domain number allocation scheme. It should be noted that the domain number allocated by this API will be based on both RC and EP controllers in a SoC. If the 'linux,pci-domain' DT property is present, then the domain number represents the actual hardware instance of the PCI endpoint controller. If not, then the domain number will be allocated based on the PCI EP/RC controller probe order. If the architecture doesn't support CONFIG_PCI_DOMAINS_GENERIC (rare), then currently a warning is thrown to indicate that the architecture specific implementation is needed. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 10 ++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 84309dfe0c68..7fa81b91e762 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -838,6 +838,9 @@ void pci_epc_destroy(struct pci_epc *epc) { pci_ep_cfs_remove_epc_group(epc->group); device_unregister(&epc->dev); + + if (IS_ENABLED(CONFIG_PCI_DOMAINS_GENERIC)) + pci_bus_release_domain_nr(NULL, &epc->dev); } EXPORT_SYMBOL_GPL(pci_epc_destroy); @@ -900,6 +903,13 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, epc->dev.release = pci_epc_release; epc->ops = ops; + /* + * TODO: If the architecture doesn't support generic PCI domains, then + * a custom implementation has to be used. + */ + if (!WARN_ON_ONCE(!IS_ENABLED(CONFIG_PCI_DOMAINS_GENERIC))) + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); + ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); if (ret) goto put_dev; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 85bdf2adb760..8e3dcac55dcd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,7 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @domain_nr: PCI domain number of the endpoint controller * @init_complete: flag to indicate whether the EPC initialization is complete * or not */ @@ -145,6 +146,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; + int domain_nr; bool init_complete; }; From patchwork Wed Jul 17 17:03:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 813039 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DE6218306F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pqkUfyQ8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3A15CC4AF68; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=22QF55zGLP92w1/Z+PYK8XSQwdKiIg4NOzO1VfG3i/M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pqkUfyQ8zcUacciepePEdFEY44EiX5ybwY0CB7QGxxP20h9Mfw9gRAdFAsPbznq7X 8syhxChMx1JYXTvlSmFJrI0L7/4gwLaSX/Sgwyx+iL86mGhTjLtfVyXRdXtYJxJ2WC zXTIbzdGNkOh6Yr1MjK0p2zG+Qw7hK5VZlaX25wKgdA4v4STpcdHbzdYZUeqqCA56E EnLR29W3PThiIwE/K/zxnGrymjU15GnU4cS+RlDk+hcSdJVxWz6eTqp2currNoOxtG 8Imsqt+fAi9fra2hvsoQa/zvWnsWbSpedMlSyzqalEwpFY72wjoetkxONTr+y/33gg QAffMFZTGT2bg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E584C3DA60; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:12 +0530 Subject: [PATCH v2 07/13] ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-7-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=986; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+Lb2vcF7RPFdOyct+N0+V3AMTmLDYS+SRQY7Fw3HIuE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lO5lBDAIgog7/DCQS8jI0fHtovZQlYwqd5B WyOgUwNCS+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9drCCACjiN6bdLASGYBDuhq74Vb33fBJv4q/jyLQI7eY1YopkvdioFtdULJXkMXon5Zuk0IaPku kTBOiAX6Fn8kn/Xlj5sScthaADAb3cWT0JlJyEMgcpT52ASfJAroHamUTcqSigY5q4qh+j9yIC9 7BkhTsQjOnd7TLxKYFC4A59LbfM8Rd7loU2mV0Et8D8agByUjG9JrtsxXjxvYhaI+JbV4OBvXrJ qjDsuvabamJDN3ijnuhEeC6DsCu1povehl1QaFsAzAtPJdQ62Kjn6HUiYSBQB3y1PNw7YmwLIkR B3++UcnUscWAB4kR2N2KnO4ZQ5P1Es90cNCEk8EtGiAME9pD X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Jul 17 17:03:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 813042 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E51183065; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=giiUt47IrfGfEwfgz3MhPd5rCPhzBBb4IZzLUKMomo9G5jlwwX6Low4eeQTvkgAxzZc1C7oQOcWSj/ztp55kVczy156Ovn3FK4jRr8XFHv9U15drDX7XamqzLOPA9SJSussVWJHX0W1pWaqtYBi6orGaHMlGZB4v9brp8o+KLNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YDjJkcUNRY3PtLuh2M3wrm5ru1GcPAftALaF7TJb3NsGqyz1OR+9Hoemm5ly0GZCO0UkgwtbBqD8A9I7zebb1nLq1z+hpGGhVaBQSrgXh4ZL68yKqKL8ZZeHmMgNqtsD3iobFvgVPyWNEWsRiwL+Y80Um7Fl13afojHyf1DIbho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DTZ8CXwj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DTZ8CXwj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 491DEC4DDE8; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DTZ8CXwjoQWzwYBGgBSCy0kUhYdWaM+9JZ1kJvMw7qpGQYkViY/95j9XqL0lZIf21 fkwCbS2eucxyXGN12M56HYTtyRSNtC9wgd0LRTITMyLXzjp2Kz4sTrUvMg6xKvXVis lHKS2hYwe6R2x4ln265ZNwRv55G9OyjgMHk2zzayCncSPoHC/X7oEgXDy8nfnKZKSB o7K61yR0rFUgI/SARgIxAIrh1Btg3ilekQ5NMTNPyNwvVEtiG4DaT5xXDjq2UTQgHX eM3eNQTmxlThIHCS1nGsycKYpmFy32Y8rtknl1fsk02h7ScQ+zeSunyZtxpTz6eKWG cR/zBC2kvj4Ow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E64EC3DA64; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:13 +0530 Subject: [PATCH v2 08/13] ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-8-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=961; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=4ksb8gQi6XxtqZHvRIfOuO8m7D/GXep6HzglfrtwSCA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lOaxt8p1VgGOZBseIX6KvazP7qZyjP7I2qJ 67f4dQ5/OCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9dS3B/9Rjk+/ba3zu1H6d/sG4cj9IPKv0Z942GUAmrfXH8YUbpeUaBSFG88mexbV8zlFoZz61wQ 7G1MgSo7bm8JbY/qVmvk0AOxJn/O3y5sW5z5LGupXMkz2ffMp7pN12e9bO8cS3cuaVQll3fVFSr ZLzzhTezyNKcZw22kyRKEQ0F3BSg3kFHWeIDQb9OgjPNTv28OhO6rcnZT2JwcHpVLVimvASPMNR kclkd+tzsE8wIbW7RE5W3UIbvkvWkFYn5VpjcqyTTMTfslxEE6jlphoqh4Dc4GDyqTzVlfyhqm0 2IC950TCA0ZOBe+3E6jyu6sxHb3rrsn23W5BZYFfCk6XloRB X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX65 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..fcfec4228670 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 { max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Jul 17 17:03:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 813040 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C87018306E; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=MmK8FJNUm4m7iryb/H5x6VbbO6IuxHdy015t6T4E5pcUJcFjte8azrmmd+RSOfAZzzxRQDaCQDHh/IMIl3Ifemn/y1TokDuCP40MXa4mvixhStxyqK/29uVGIEpK7uaM29iw70D0cNuvVNIAKeUdHK8uEaPwcrcU1tg1JubZlCA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VIeyRCQkclH2mUPkaR4i5657Z4ya9A/NO1SReiZMd+QD4XyKyU+GB1LuTUeV2XaNlgjlu8kmJ/tABLHIIRWfi3lfgPwa6phViMiYOeXIj0EjwQ36CAPB1333Ekjf30AAEjD2WCsUD7CpoCQI31VuuTGzvLdwN0zZUb3KTWdWXLU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OobH63Br; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OobH63Br" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5E999C4AF1A; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OobH63Brw5e3Wl00GuzcRP2jf+t3XLCUngEkFnINvwfybj6SyL81DSLEUjsHboTeD rnYSeSP7DWb01ej/VkNuPz1UA2tPDCsnBAQ+qa9l/ndtNYkaBv/2PipNSrvmEalpWR TReq7ReTvp9nQebNaCvVnocYWtoOXGvEemi7QXUI4C807+8cqA0RQy4iqqs9xgN/2D CDt9wRFYtQKQqNo26NOYxk+jtoSyHFFjhf1gfmBLW5M/rZ28Dakc43yYVhJINaaewA zFF7eDzXqGl177+jE4X5uZajrlpJWMZ6aa8ki1ADUIlpQ7DKB6mM3L3HCCaTRHCsKu KMY9XKc39cGBw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FCC4C3DA63; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:14 +0530 Subject: [PATCH v2 09/13] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-9-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1289; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=YKSy5vPklQvLJA99UbdPy4mFyoiPQChYvArhByAGkpA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lO0Dmif7USBFz5hYoCiza5W/fd8O+FngHr/ 24+q3osoLiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9awtB/4kSxxPulCuNa6RgrOTzuAeI/hkw6WQQ97HhrEZToQEkUZvp8WMGZ2aQIHLxS2xYUQxE5R EdJWwjl83+26qlrhNwwR60/fltegr6Wyb4g3dhiRBrYGav0cCt7hSwbEatBc5axOyxNNwf80eg3 y4xM9rVaSJICwe8FTw+d4oYXWwcS6HdAR9W8PJpcVI/iFGOr7Dtia2yH1XKywUNyVAdS/JynHxV nQfS2SIHXiCs3b2v6xYBx1NBgGVcKZoh7CM1u0bWJkaY4s+QlWL1QMJEK1JkLAzstaWYk/W2lth pQLivgbf7hZuXjpGbCnm8+FbHBu0Gd3uSXy1T4cSCTa33tsV X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SA8775P SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..198b39abde97 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4618,6 +4618,7 @@ pcie0_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -4775,6 +4776,7 @@ pcie1_ep: pcie-ep@1c10000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; + linux,pci-domain = <1>; status = "disabled"; }; From patchwork Wed Jul 17 17:03:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 813038 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D47B11836C4; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MGyfRJ5J" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8E1E5C4AF4D; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=tX8FTWnGJ7X+iRNoObXaAyTwTcEzujVFSBsB2Q+105U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MGyfRJ5Jd7g/YadOt9hSTfpCj1EtbzvXBf7HXxhwni7rxaoEeH4PS17JfmJww7kbS DHDqSd6HlrjDpfuBJH6CcO9FRmg+61vccQXlcwf/eCwXzgRnX2WPBzh3M7czvrjfwm GVJma5JSgZX5/lqINViIQEarw6IzBPDjWwzHJnoFc3493TdNBKwd5VTFznumaQbZhc iWxZt3iHjPGoXoI5iYY8jEDxTC0LfV8NkYG9XbOfc+l6xXjT2kP89a2dff9POJ0frq Q0oAAfpEdA6UnibyZcdPXFStIIkFe0kdVzFJoA3fa8h4TFVcoAggbBja5i6Uaab3y1 FsvvYTCFJcyuw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82BD3C3DA64; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:17 +0530 Subject: [PATCH v2 12/13] PCI: qcom: Simulate PCIe hotplug using 'global' interrupt Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-12-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4482; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=68qztRW94Mm+gBy+X9dPxpSD+lUfqzlvBoYcBtvmJqE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lPEJGOi6kFsE8LsIiGSGwM+wYh+wGn9MujE sMdM4orBQCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TwAKCRBVnxHm/pHO 9fg+B/46u1JODwRkfF5buuExfQJGr0/s3DMwDLDjRfjyfW4ROXGgoy1YApW/oyVmZGJOgJVxuZT V2BzMYdo/CG3hBYSnmsujZaP6+t7sAi6d8hDrBW3PQHly79yJjMjymrOSsLOQEVJeh1DQsPoXkg 85XqwI8jjp1hnUbjBmhRr/Ync6tq5qhop5lNdc4VfPKJQxtrF/G+Gem0zWJTweg7ued+yvTMePa Xzd9TqwW9LA61rmr0fILas7eNCZ4C3cbyG/ccXN+Y+CY5X6Hp17glTZYGR0zTh9DAkxdhYaUV68 CM7tbd5JzXN5IjPq4lngypuFUmUf75S3isRaVk68Rlk69sNQ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Historically, Qcom PCIe RC controllers lack standard hotplug support. So when an endpoint is attached to the SoC, users have to rescan the bus manually to enumerate the device. But this can be avoided by simulating the PCIe hotplug using Qcom specific way. Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt to the host CPUs. The device driver can use this event to identify events such as PCIe link specific events, safety events etc... One such event is the PCIe Link up event generated when an endpoint is detected on the bus and the Link is 'up'. This event can be used to simulate the PCIe hotplug in the Qcom SoCs. So add support for capturing the PCIe Link up event using the 'global' interrupt in the driver. Once the Link up event is received, the bus underneath the host bridge is scanned to enumerate PCIe endpoint devices, thus simulating hotplug. All of the Qcom SoCs have only one rootport per controller instance. So only a single 'Link up' event is generated for the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 55 +++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..a1d678fe7fa5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -50,6 +50,9 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_INT_ALL_STATUS 0x224 +#define PARF_INT_ALL_CLEAR 0x228 +#define PARF_INT_ALL_MASK 0x22c #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 @@ -121,6 +124,9 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_UP BIT(13) + /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN BIT(1) #define RD_NO_SNOOP_OVERIDE_EN BIT(3) @@ -1488,6 +1494,29 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) qcom_pcie_link_transition_count); } +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) +{ + struct qcom_pcie *pcie = data; + struct dw_pcie_rp *pp = &pcie->pci->pp; + struct device *dev = pcie->pci->dev; + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); + + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); + + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { + dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); + /* Rescan the bus to enumerate endpoint devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(pp->bridge->bus); + pci_unlock_rescan_remove(); + } else { + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); + } + + return IRQ_HANDLED; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1498,7 +1527,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; - int ret; + int ret, irq; + char *name; pcie_cfg = of_device_get_match_data(dev); if (!pcie_cfg || !pcie_cfg->ops) { @@ -1617,6 +1647,27 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", + pci_domain_nr(pp->bridge->bus)); + if (!name) { + ret = -ENOMEM; + goto err_host_deinit; + } + + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) { + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + qcom_pcie_global_irq_thread, + IRQF_ONESHOT, name, pcie); + if (ret) { + dev_err_probe(&pdev->dev, ret, + "Failed to request Global IRQ\n"); + goto err_host_deinit; + } + + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); + } + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) @@ -1624,6 +1675,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) return 0; +err_host_deinit: + dw_pcie_host_deinit(pp); err_phy_exit: phy_exit(pcie->phy); err_pm_runtime_put: