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([203.56.128.103]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc27383sm68131575ad.140.2024.07.16.23.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 23:02:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Daniyal Khan , qemu-stable@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= Subject: [PATCH v2 1/3] target/arm: Use float_status copy in sme_fmopa_s Date: Wed, 17 Jul 2024 16:01:47 +1000 Message-ID: <20240717060149.204788-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240717060149.204788-1-richard.henderson@linaro.org> References: <20240717060149.204788-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Daniyal Khan We made a copy above because the fp exception flags are not propagated back to the FPST register, but then failed to use the copy. Cc: qemu-stable@nongnu.org Fixes: 558e956c719 ("target/arm: Implement FMOPA, FMOPS (non-widening)") Signed-off-by: Daniyal Khan [rth: Split from a larger patch] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- target/arm/tcg/sme_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index e2e0575039..5a6dd76489 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -916,7 +916,7 @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, if (pb & 1) { uint32_t *a = vza_row + H1_4(col); uint32_t *m = vzm + H1_4(col); - *a = float32_muladd(n, *m, *a, 0, vst); + *a = float32_muladd(n, *m, *a, 0, &fpst); } col += 4; pb >>= 4; From patchwork Wed Jul 17 06:01:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 812976 Delivered-To: patch@linaro.org Received: by 2002:a5d:42c4:0:b0:367:895a:4699 with SMTP id t4csp640880wrr; Tue, 16 Jul 2024 23:03:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW9qcLMOYk3tKCicjHTqqyh53M4OycLdTCFmWzrxqf5BY+rBH1NJoRC3ch40uAEPRTzd1+4MJWqvTOKOMQtzQFl X-Google-Smtp-Source: AGHT+IHgOE9++N9HGO1fwfoJ6YTpCTiSVVofihjiujGshdciMnFUgKswvRngnUomsCdA+Z7XgkBW X-Received: by 2002:a05:622a:586:b0:445:624:22ed with SMTP id d75a77b69052e-44f86173781mr7753311cf.9.1721196194772; Tue, 16 Jul 2024 23:03:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721196194; cv=none; d=google.com; s=arc-20160816; b=xqPELpZrAbQtsKX6itBZ5QCva0/uJPlDyFEsV2jTTa3yo3o4OG5QAHbpbJrIZTiE42 S6oZhfiX2XZUcEoCONAMJC+0nxD9OAAOqKkOjW8kR0e4sf3vWNOB87BhkwgaFjHWx8XK 4PUIMfiLnAhwPee91GcPiHRxjZpaEKufsjh5dMrW7g8jUfLJ96+6JOFNWayFAsVPOhJD Z4xQMNYOvpbWC2EcH0rBi8kzgLph4tWrJ12ozMWHFT6Gjxg1xLEraSDpFg4FPsZ4OCC1 BdIQaXYMty89wLVOtgJrj+9hgd2Cg3/eFKGuKmI2omMOJZ3ijL84wB/01sXL9zE9jQzg Woew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+fHVJ4bchQHH074Xsji85kfYExDlNqpEjXJOFYCoInA=; fh=4a914xxHcG3H2SO2cZutR3tz4zHmLw+pQzX8ELB6t6Q=; b=Bccb4vbrzFDJoMvh0b4brVjV7NoRSR7gIFA85AvovgBetsXPLc2aVybFuJIcrQJ5Nt JRsOaHZft3CDi4dN6R2ncYgCs7EXGKu5kM6qCc2/HfGEo5GAsp7vnUWQ4sFRfczaUGQk dLVcjW+byeGkK2ksN53Js0PXk2UlwIuIOQxMOFtdjsyjk6o6pWm2MzlgSs88aZWANvIq QyhpaDD19vjP+w2FYRsUS9oVfTmRpW22YD24vsOdju7uDSMj4fZBTH7rc0xdZ1DhbHSz oWUsiZZK4Xka4PUVQXP1CTUV3687TVFKOCwHSESDw7mPf77RaVSXNcN1j6wM/W2SAvaS 8PZg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gPsEuXWd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([203.56.128.103]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc27383sm68131575ad.140.2024.07.16.23.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 23:02:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org, Daniyal Khan , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v2 2/3] target/arm: Use FPST_F16 for SME FMOPA (widening) Date: Wed, 17 Jul 2024 16:01:48 +1000 Message-ID: <20240717060149.204788-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240717060149.204788-1-richard.henderson@linaro.org> References: <20240717060149.204788-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 16 X-Spam_score: 1.6 X-Spam_bar: + X-Spam_report: (1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This operation has float16 inputs and thus must use the FZ16 control not the FZ control. Cc: qemu-stable@nongnu.org Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)") Reported-by: Daniyal Khan Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2374 Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/tcg/translate-sme.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 46c7fce8b4..185a8a917b 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -304,6 +304,7 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, } static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + ARMFPStatusFlavour e_fpst, gen_helper_gvec_5_ptr *fn) { int svl = streaming_vec_reg_size(s); @@ -319,15 +320,18 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); pm = pred_full_reg_ptr(s, a->pm); - fpst = fpstatus_ptr(FPST_FPCR); + fpst = fpstatus_ptr(e_fpst); fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); return true; } -TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_h) -TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) -TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, + MO_32, FPST_FPCR_F16, gen_helper_sme_fmopa_h) +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, + MO_32, FPST_FPCR, gen_helper_sme_fmopa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, + MO_64, FPST_FPCR, gen_helper_sme_fmopa_d) /* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) From patchwork Wed Jul 17 06:01:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 812978 Delivered-To: patch@linaro.org Received: by 2002:a5d:42c4:0:b0:367:895a:4699 with SMTP id t4csp640984wrr; Tue, 16 Jul 2024 23:03:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV8FkiUXxRIIpSmU07uSE1FTBZsTyEtsnQf3yyayGnqZhz1Db2yOV2dpFD3NHWOBnIHAiifpEbajwIbGGU5oe+M X-Google-Smtp-Source: AGHT+IGLqg5W9YNuvgmEk8xnT3+crFbgeNUQkbNJjGvNIcqtGZlqwcli19cVT4dssOmebwmXpx0N X-Received: by 2002:a05:622a:1a16:b0:447:e562:b64 with SMTP id d75a77b69052e-44f8665f4f2mr6996581cf.64.1721196215338; Tue, 16 Jul 2024 23:03:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1721196215; cv=none; d=google.com; s=arc-20160816; b=MXueLxIa9XUShg/6+Zc/4eG0BhfZ9gm4VVoIIq6/kmtHhLbjgCT51fokCWqbY01KrV oZudwXOZv40G0tqrO4Nls2mxiUqKKGPt5K9dWrIM1dRPAimqdw1HMzlxPnbZqpI2Jl/B q6vRDblgd0utLz3TfcivJqjx3Zot4SmDn84AWi6RO75qFPDlxV/vdzh/ormv3DbOc0nu XUslmNHK25uCc0gRko3EBefdVy5eIpf0helVruKbm75YtVoH6pPcB9zOSqRTNxpB+4EF UjPTWChmi7J8okIdIUQ4a0nuMpsiog4R2gVJNbZbxHhonkoEQf53XacXBa6eOAZ54Ooz irqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KxWo2TuA/jQgHzkRVWBT3lPb6x2Kqd7zGBpsPQ9Mv9Y=; fh=bItpYVfT3BdAR3hnyiwSLGV6OSV04sMX0u6RKRxw3oE=; b=sIbRwWW2N9slzg/KRXD2p/9L//g0erixOHQxEoxSd2LCVLIGBoz3NBpCfv94spELyi ClnKKA8xEBI21aNM5C2Gzt7vFBlgGQhzOyvwbyRHjzIXe3RoBh904BgUB1+idhMjecWT s8tcX6X8HxtVzM6ngbv2z/APt6+KxPv3Kyj4FyLy194Qt4tZZzqNwx4o789TyjgGflTW 07KCU+XCqrkWB5L13iLLtLQBSi3Ib0sDak9zpgUFJ7S7dqdv5m8s93gg1CPlVO8jvsXl ew5okXyKevVKBWvMnESsO8cWyy+TDVaaVNu97e/HDc5CAKYJNY1Wv08rHNk43RbWrH8X qR0w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ziPiMi1a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([203.56.128.103]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc27383sm68131575ad.140.2024.07.16.23.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 23:02:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Daniyal Khan , =?utf-8?q?Ale?= =?utf-8?q?x_Benn=C3=A9e?= Subject: [PATCH v2 3/3] tests/tcg/aarch64: Add test cases for SME FMOPA (widening) Date: Wed, 17 Jul 2024 16:01:49 +1000 Message-ID: <20240717060149.204788-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240717060149.204788-1-richard.henderson@linaro.org> References: <20240717060149.204788-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Daniyal Khan Signed-off-by: Daniyal Khan Message-Id: 172090222034.13953.16888708708822922098-1@git.sr.ht [rth: Split test from a larger patch, tidy assembly] Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- tests/tcg/aarch64/sme-fmopa-1.c | 63 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/sme-fmopa-2.c | 56 +++++++++++++++++++++++++++ tests/tcg/aarch64/sme-fmopa-3.c | 63 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 5 ++- 4 files changed, 185 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/sme-fmopa-1.c create mode 100644 tests/tcg/aarch64/sme-fmopa-2.c create mode 100644 tests/tcg/aarch64/sme-fmopa-3.c diff --git a/tests/tcg/aarch64/sme-fmopa-1.c b/tests/tcg/aarch64/sme-fmopa-1.c new file mode 100644 index 0000000000..652c4ea090 --- /dev/null +++ b/tests/tcg/aarch64/sme-fmopa-1.c @@ -0,0 +1,63 @@ +/* + * SME outer product, 1 x 1. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +static void foo(float *dst) +{ + asm(".arch_extension sme\n\t" + "smstart\n\t" + "ptrue p0.s, vl4\n\t" + "fmov z0.s, #1.0\n\t" + /* + * An outer product of a vector of 1.0 by itself should be a matrix of 1.0. + * Note that we are using tile 1 here (za1.s) rather than tile 0. + */ + "zero {za}\n\t" + "fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n\t" + /* + * Read the first 4x4 sub-matrix of elements from tile 1: + * Note that za1h should be interchangeable here. + */ + "mov w12, #0\n\t" + "mova z0.s, p0/m, za1v.s[w12, #0]\n\t" + "mova z1.s, p0/m, za1v.s[w12, #1]\n\t" + "mova z2.s, p0/m, za1v.s[w12, #2]\n\t" + "mova z3.s, p0/m, za1v.s[w12, #3]\n\t" + /* + * And store them to the input pointer (dst in the C code): + */ + "st1w {z0.s}, p0, [%0]\n\t" + "add x0, x0, #16\n\t" + "st1w {z1.s}, p0, [x0]\n\t" + "add x0, x0, #16\n\t" + "st1w {z2.s}, p0, [x0]\n\t" + "add x0, x0, #16\n\t" + "st1w {z3.s}, p0, [x0]\n\t" + "smstop" + : : "r"(dst) + : "x12", "d0", "d1", "d2", "d3", "memory"); +} + +int main() +{ + float dst[16] = { }; + + foo(dst); + + for (int i = 0; i < 16; i++) { + if (dst[i] != 1.0f) { + goto failure; + } + } + /* success */ + return 0; + + failure: + for (int i = 0; i < 16; i++) { + printf("%f%c", dst[i], i % 4 == 3 ? '\n' : ' '); + } + return 1; +} diff --git a/tests/tcg/aarch64/sme-fmopa-2.c b/tests/tcg/aarch64/sme-fmopa-2.c new file mode 100644 index 0000000000..15f0972d83 --- /dev/null +++ b/tests/tcg/aarch64/sme-fmopa-2.c @@ -0,0 +1,56 @@ +/* + * SME outer product, FZ vs FZ16 + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +static void test_fmopa(uint32_t *result) +{ + asm(".arch_extension sme\n\t" + "smstart\n\t" /* Z*, P* and ZArray cleared */ + "ptrue p2.b, vl16\n\t" /* Limit vector length to 16 */ + "ptrue p5.b, vl16\n\t" + "movi d0, #0x00ff\n\t" /* fp16 denormal */ + "movi d16, #0x00ff\n\t" + "mov w15, #0x0001000000\n\t" /* FZ=1, FZ16=0 */ + "msr fpcr, x15\n\t" + "fmopa za3.s, p2/m, p5/m, z16.h, z0.h\n\t" + "mov w15, #0\n\t" + "st1w {za3h.s[w15, 0]}, p2, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t" + "mov w15, #2\n\t" + "add %0, %0, #16\n\t" + "st1w {za3h.s[w15, 0]}, p2, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t" + "smstop" + : "+r"(result) : + : "x15", "x16", "p2", "p5", "d0", "d16", "memory"); +} + +int main(void) +{ + uint32_t result[4 * 4] = { }; + + test_fmopa(result); + + if (result[0] != 0x2f7e0100) { + printf("Test failed: Incorrect output in first 4 bytes\n" + "Expected: %08x\n" + "Got: %08x\n", + 0x2f7e0100, result[0]); + return 1; + } + + for (int i = 1; i < 16; ++i) { + if (result[i] != 0) { + printf("Test failed: Non-zero word at position %d\n", i); + return 1; + } + } + + return 0; +} diff --git a/tests/tcg/aarch64/sme-fmopa-3.c b/tests/tcg/aarch64/sme-fmopa-3.c new file mode 100644 index 0000000000..3bfec34914 --- /dev/null +++ b/tests/tcg/aarch64/sme-fmopa-3.c @@ -0,0 +1,63 @@ +/* + * SME outer product, [ 1 2 3 4 ] squared + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +static const float i_1234[4] = { + 1.0f, 2.0f, 3.0f, 4.0f +}; + +static const float expected[4] = { + 4.515625f, 5.750000f, 6.984375f, 8.218750f +}; + +static void test_fmopa(float *result) +{ + asm(".arch_extension sme\n\t" + "smstart\n\t" /* ZArray cleared */ + "ptrue p2.b, vl16\n\t" /* Limit vector length to 16 */ + "ld1w {z0.s}, p2/z, [%1]\n\t" + "mov w15, #0\n\t" + "mov za3h.s[w15, 0], p2/m, z0.s\n\t" + "mov za3h.s[w15, 1], p2/m, z0.s\n\t" + "mov w15, #2\n\t" + "mov za3h.s[w15, 0], p2/m, z0.s\n\t" + "mov za3h.s[w15, 1], p2/m, z0.s\n\t" + "msr fpcr, xzr\n\t" + "fmopa za3.s, p2/m, p2/m, z0.h, z0.h\n\t" + "mov w15, #0\n\t" + "st1w {za3h.s[w15, 0]}, p2, [%0]\n" + "add %0, %0, #16\n\t" + "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t" + "mov w15, #2\n\t" + "add %0, %0, #16\n\t" + "st1w {za3h.s[w15, 0]}, p2, [%0]\n\t" + "add %0, %0, #16\n\t" + "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t" + "smstop" + : "+r"(result) : "r"(i_1234) + : "x15", "x16", "p2", "d0", "memory"); +} + +int main(void) +{ + float result[4 * 4] = { }; + int ret = 0; + + test_fmopa(result); + + for (int i = 0; i < 4; i++) { + float actual = result[i]; + if (fabsf(actual - expected[i]) > 0.001f) { + printf("Test failed at element %d: Expected %f, got %f\n", + i, expected[i], actual); + ret = 1; + } + } + return ret; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index b53218e115..8cc62eb456 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -70,8 +70,9 @@ endif # SME Tests ifneq ($(CROSS_AS_HAS_ARMV9_SME),) -AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2 -sme-outprod1 sme-smopa-1 sme-smopa-2: CFLAGS += $(CROSS_AS_HAS_ARMV9_SME) +SME_TESTS = sme-outprod1 sme-smopa-1 sme-smopa-2 sme-fmopa-1 sme-fmopa-2 sme-fmopa-3 +AARCH64_TESTS += $(SME_TESTS) +$(SME_TESTS): CFLAGS += $(CROSS_AS_HAS_ARMV9_SME) endif # System Registers Tests