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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde891cesm7615728f8f.62.2024.07.11.04.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 04:52:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 02/11] i2c: riic: Call pm_runtime_get_sync() when need to access registers Date: Thu, 11 Jul 2024 14:51:58 +0300 Message-Id: <20240711115207.2843133-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> References: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea There is no need to runtime resume the device as long as the IP registers are not accessed. Calling pm_runtime_get_sync() at the register access time leads to a simpler error path. Reviewed-by: Andi Shyti Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v3: - collected tags Changes in v2: - none drivers/i2c/busses/i2c-riic.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index c742ab6106b9..af7edc26462c 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -301,19 +301,15 @@ static const struct i2c_algorithm riic_algo = { static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) { - int ret = 0; unsigned long rate; int total_ticks, cks, brl, brh; struct device *dev = riic->adapter.dev.parent; - pm_runtime_get_sync(dev); - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { dev_err(&riic->adapter.dev, "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); - ret = -EINVAL; - goto out; + return -EINVAL; } rate = clk_get_rate(riic->clk); @@ -351,8 +347,7 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) if (brl > (0x1F + 3)) { dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n", (unsigned long)t->bus_freq_hz); - ret = -EINVAL; - goto out; + return -EINVAL; } brh = total_ticks - brl; @@ -384,6 +379,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) t->scl_fall_ns / (1000000000 / rate), t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); + pm_runtime_get_sync(dev); + /* Changing the order of accessing IICRST and ICE may break things! */ riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); @@ -397,9 +394,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); -out: pm_runtime_put(dev); - return ret; + return 0; } static struct riic_irq_desc riic_irqs[] = { From patchwork Thu Jul 11 11:52:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 812699 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32171158842 for ; Thu, 11 Jul 2024 11:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720698750; cv=none; b=OT/+XhN7TEyydY/JxOuwn1dRvMWgmXD0eejeUSbnkzVHAHFHELQ9hjAbXead9f0TAuEnpJHaeIXYz1vlDx1fa8kRrfaY8V25X8MZLc+2Y9jPkt16yOLgwAFpohbE4J+XsSLKCnu646W/1PPKzOomLOZhr4o67e3UFhW6Rg5O/s8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720698750; c=relaxed/simple; bh=LNIbD0mShRhijjyrncFa/Sfct8EIIrIFNTLpGEmeFOg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bc592r/vXubSx1TDBdaeNqQNM1cUPyxS4mvoHz8ialzFT4tW7r49XdCvE7AYttdQuujW0S9HZYMkVKn2lmk6PSzcofToloZkc5U0JITEA8EsH+vfF9r7C+gd85+952KjorSaKJODGTuVKWR3PmfiKMl4IFTNNM3R05VAgM1b+5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=gErmeWW8; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="gErmeWW8" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-36794da7c96so391644f8f.0 for ; Thu, 11 Jul 2024 04:52:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1720698747; x=1721303547; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3C+MvDdWpXknhzh2+tcBHGd/tUZH0vNFhsggMze/hfU=; b=gErmeWW8eVDwAiXp6aiu2XEy1MSLe9CBSZ9+GDpA7W2DSjeuklvmMM83XouSD4s2wB D26jtlvXgiJMsgKaMdjNKVb4ixXvTt6SvRI+dHmce0UaXUW4oXFjEIrp/fbX02DX1TB/ ntFxJNtICST8HniZPGeQ2TcW/QcuJjt6jkV3TIPQrS+wlbT0esvCSvQERbgt374C8YSl RO8FKaKxp6dWMqvAovMOo0uUg212NlAAQjijpbX4qmF7heynE/c4s80hB5w0R1stqqig J6qLpBA7e4QayXljvU5iMABGr1Wch9CVR10QTOsfEjKSP7lCiuL9W0rwF6o87I/yZ1Vn kOyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720698747; x=1721303547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3C+MvDdWpXknhzh2+tcBHGd/tUZH0vNFhsggMze/hfU=; b=KtFx2tEkhh6yYlzQJJIcMPK+qMtBLkzYQIYxriSRBm11M2is/5DRfHiqEEQ/5Yg9KE iQNKk3KCKWdI59TbXwMx7BPBX8sU5nL2txst+a9JhnyhHr8X/AxdSQ4XsX2D28H6wAoY 4XGWUw7h4DbC9IMIPmsjSmxMynKp8WMxanWKLCFHbT970OBUl99XbZURDnfDl9JfsU/g b2ZU0SqpR7D48Hi5/43ArNKVdOA42TpQ25VA1bZkdGm4AGbyP3v9q3vXv2jIPDWrY0M5 KYRXPPtsjeq1cyoFkL7izxyWaF2TCqyK7kPJ7SSaZg+JT3I6nseXDRrfsq6dtgVdYQT5 J/fA== X-Forwarded-Encrypted: i=1; AJvYcCVZ837Kq8dgxmQB46nfh/FnVKC7Tx4gxyU3BdYyxcUejCerBJfxxkXQjfLegVQM7RawatCW0up4Hdoma4Sg3PWxdywj6bhl1csH X-Gm-Message-State: AOJu0YxLeyzkYE0fUOo50bwWjLrezrAFvgQ59WSh/5POjX3eqdJnamO8 bwDVp0xQg9zg9lwBSujxtMjzWi8AJYaEV7ajVmNBwiOPMhvUc4mkvLo6fD3f2Qmw78z/9fryqkT q X-Google-Smtp-Source: AGHT+IH2hTGLcXrN3uhdyk22JKMZRxxLuK+TCBJEjjs2NDQ/EQ3L1L+BY0g6p7ApgwsOTecou6oDHA== X-Received: by 2002:a5d:47ac:0:b0:367:4384:a572 with SMTP id ffacd0b85a97d-367cea4687amr6873928f8f.9.1720698746729; Thu, 11 Jul 2024 04:52:26 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde891cesm7615728f8f.62.2024.07.11.04.52.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 04:52:26 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 04/11] i2c: riic: Enable runtime PM autosuspend support Date: Thu, 11 Jul 2024 14:52:00 +0300 Message-Id: <20240711115207.2843133-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> References: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable runtime PM autosuspend support for the RIIC driver. With this, in case there are consecutive xfer requests the device wouldn't be runtime enabled/disabled after each consecutive xfer but after the the delay configured by user. With this, we can avoid touching hardware registers involved in runtime PM suspend/resume saving in this way some cycles. The default chosen autosuspend delay is zero to keep the previous driver behavior. Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v3: - none Changes in v2: - none drivers/i2c/busses/i2c-riic.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 068f90ecf27e..46765715d39f 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -171,7 +171,8 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) } out: - pm_runtime_put(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return riic->err ?: num; } @@ -399,7 +400,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); - pm_runtime_put(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); return 0; } @@ -479,6 +481,8 @@ static int riic_i2c_probe(struct platform_device *pdev) i2c_parse_fw_timings(dev, &i2c_t, true); + pm_runtime_set_autosuspend_delay(dev, 0); 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde891cesm7615728f8f.62.2024.07.11.04.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 04:52:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 06/11] i2c: riic: Define individual arrays to describe the register offsets Date: Thu, 11 Jul 2024 14:52:02 +0300 Message-Id: <20240711115207.2843133-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> References: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Define individual arrays to describe the register offsets. In this way we can describe different IP variants that share the same register offsets but have differences in other characteristics. Commit prepares for the addition of fast mode plus. Signed-off-by: Claudiu Beznea Reviewed-by: Wolfram Sang --- Changes in v3: - none Changes in v2: - none drivers/i2c/busses/i2c-riic.c | 58 +++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 5e4f56ee97e3..0019a8e56dbb 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -91,7 +91,7 @@ enum riic_reg_list { }; struct riic_of_data { - u8 regs[RIIC_REG_END]; + const u8 *regs; }; struct riic_dev { @@ -521,36 +521,40 @@ static void riic_i2c_remove(struct platform_device *pdev) pm_runtime_dont_use_autosuspend(dev); } +static const u8 riic_rz_a_regs[RIIC_REG_END] = { + [RIIC_ICCR1] = 0x00, + [RIIC_ICCR2] = 0x04, + [RIIC_ICMR1] = 0x08, + [RIIC_ICMR3] = 0x10, + [RIIC_ICSER] = 0x18, + [RIIC_ICIER] = 0x1c, + [RIIC_ICSR2] = 0x24, + [RIIC_ICBRL] = 0x34, + [RIIC_ICBRH] = 0x38, + [RIIC_ICDRT] = 0x3c, + [RIIC_ICDRR] = 0x40, +}; + static const struct riic_of_data riic_rz_a_info = { - .regs = { - [RIIC_ICCR1] = 0x00, - [RIIC_ICCR2] = 0x04, - [RIIC_ICMR1] = 0x08, - [RIIC_ICMR3] = 0x10, - [RIIC_ICSER] = 0x18, - [RIIC_ICIER] = 0x1c, - [RIIC_ICSR2] = 0x24, - [RIIC_ICBRL] = 0x34, - [RIIC_ICBRH] = 0x38, - [RIIC_ICDRT] = 0x3c, - [RIIC_ICDRR] = 0x40, - }, + .regs = riic_rz_a_regs, +}; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde891cesm7615728f8f.62.2024.07.11.04.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 04:52:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 08/11] i2c: riic: Add support for fast mode plus Date: Thu, 11 Jul 2024 14:52:04 +0300 Message-Id: <20240711115207.2843133-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> References: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Fast mode plus is available on most of the IP variants that RIIC driver is working with. The exception is (according to HW manuals of the SoCs where this IP is available) the Renesas RZ/A1H. For this, patch introduces the struct riic_of_data::fast_mode_plus. Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by instantiating the RIIC frequency to 1MHz and issuing i2c reads on the fast mode plus capable devices (and the i2c clock frequency was checked on RZ/G3S). Signed-off-by: Claudiu Beznea --- Changes in v3: - enabled FM+ for all riic_rz_a_info based platforms except RZ/A1H as requested in review comments; with this, dropped the riic_rz_g2_info and RZ/G2 specific compatibles in riic_i2c_dt_ids[]; Note that it has been tested only on platforms mentioned in commit description (as I don't have all the other RZ/A platforms). Changes in v2: - dropped code that handles the renesas,riic-no-fast-mode-plus - updated commit description drivers/i2c/busses/i2c-riic.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 0019a8e56dbb..ba969ad5f015 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -63,6 +63,8 @@ #define ICMR3_ACKWP 0x10 #define ICMR3_ACKBT 0x08 +#define ICFER_FMPE 0x80 + #define ICIER_TIE 0x80 #define ICIER_TEIE 0x40 #define ICIER_RIE 0x20 @@ -80,6 +82,7 @@ enum riic_reg_list { RIIC_ICCR2, RIIC_ICMR1, RIIC_ICMR3, + RIIC_ICFER, RIIC_ICSER, RIIC_ICIER, RIIC_ICSR2, @@ -92,6 +95,7 @@ enum riic_reg_list { struct riic_of_data { const u8 *regs; + bool fast_mode_plus; }; struct riic_dev { @@ -311,11 +315,14 @@ static int riic_init_hw(struct riic_dev *riic) int total_ticks, cks, brl, brh; struct i2c_timings *t = &riic->i2c_t; struct device *dev = riic->adapter.dev.parent; + const struct riic_of_data *info = riic->info; - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { + if ((!info->fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) || + (info->fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)) { dev_err(&riic->adapter.dev, - "unsupported bus speed (%dHz). %d max\n", - t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); + "unsupported bus speed (%dHz). %d max\n", t->bus_freq_hz, + info->fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ : + I2C_MAX_FAST_MODE_FREQ); return -EINVAL; } @@ -401,6 +408,9 @@ static int riic_init_hw(struct riic_dev *riic) riic_writeb(riic, 0, RIIC_ICSER); riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3); + if (info->fast_mode_plus && t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) + riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER); + riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); pm_runtime_mark_last_busy(dev); @@ -526,6 +536,7 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { [RIIC_ICCR2] = 0x04, [RIIC_ICMR1] = 0x08, [RIIC_ICMR3] = 0x10, + [RIIC_ICFER] = 0x14, [RIIC_ICSER] = 0x18, [RIIC_ICIER] = 0x1c, [RIIC_ICSR2] = 0x24, @@ -537,6 +548,11 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_a_info = { .regs = riic_rz_a_regs, + .fast_mode_plus = true, +}; + +static const struct riic_of_data riic_rz_a1h_info = { + .regs = riic_rz_a_regs, }; static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { @@ -544,6 +560,7 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { [RIIC_ICCR2] = 0x01, [RIIC_ICMR1] = 0x02, [RIIC_ICMR3] = 0x04, + [RIIC_ICFER] = 0x05, [RIIC_ICSER] = 0x06, [RIIC_ICIER] = 0x07, [RIIC_ICSR2] = 0x09, @@ -555,6 +572,7 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_v2h_info = { .regs = riic_rz_v2h_regs, + .fast_mode_plus = true, }; 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([82.78.167.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde891cesm7615728f8f.62.2024.07.11.04.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 04:52:38 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: chris.brandt@renesas.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3 10/11] arm64: dts: renesas: rzg3s-smarc: Enable i2c0 node Date: Thu, 11 Jul 2024 14:52:06 +0300 Message-Id: <20240711115207.2843133-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> References: <20240711115207.2843133-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable i2c0 node. Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index deb2ad37bb2e..7945d44e6ee1 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,7 @@ / { aliases { + i2c0 = &i2c0; serial0 = &scif0; mmc1 = &sdhi1; }; @@ -66,6 +67,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <1000000>; +}; + &pinctrl { key-1-gpio-hog { gpio-hog;