From patchwork Mon Jul 15 17:33:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812849 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFDB55589A; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064829; cv=none; b=QsYUHDOLbKKVhQ/kI64wcxmukJNBLHtr3qjizTYNSv9mcO4nUhMCyWG5oRMEX6Wq2q/hWw6qJRCDYMMmFO8SL7ZX35OYMIRnHQdIvNU4gN6a7A3c00vC+3dRaKNQJD6uv3HosswyAzID202wfb2rUf79e3PkZmvv2bZg388Cnlo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064829; c=relaxed/simple; bh=YrQ8WsJOqwj1JkFZkHzhDi8IflXYH48WlLSKQE4D1GU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cH3jwoukosRVKq4XcibEzKTd6Zczo1ATuQu6kMmeXW7XGalSae/4w7IYRBSZZsdClBwPoCpPIvfJ1z2CsW1aBOjvKPWby1U3x6Y+qUoFDSMI2qMmWKtknBb6HYmm6XGBhT1ZLhTcTqPx1cJFRYzWOV+y5aYY48zpnIJpFMo4HkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s9aZXFw8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s9aZXFw8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 68D68C32782; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064829; bh=YrQ8WsJOqwj1JkFZkHzhDi8IflXYH48WlLSKQE4D1GU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=s9aZXFw8wctgOvDBJaqKS0m1ORY6HA+Ylnh3xgcmak6o/vjVbR7hYySdfv+ZyVgsr IU0VlmW0uEcNQ9URECyvJVhVdooWuWURevEAVj/0gfNaLJhLKGis0DCrM1ncwReX1F LlOhfR/pgKJ+5vsIPBTUwh68VQG+PZCG90nYLKL8LVqttl9DYefe+X7YrxjjNbp92g ywzXn2KG3rULRd1oS6wxEchZ8rAi5wjPQzinq8i4AxTtvvaLjuRTVZHX/AT46F27SV car1XNcekFs8PBW/U0pBvc33c2oV9Adzp11l4B7pdfzV4f6t+OtkUFPeE+dLdtPLLx gQfjyK+kwkQTA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5603BC3DA4A; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:43 +0530 Subject: [PATCH 01/14] PCI: qcom-ep: Drop the redundant masking of global IRQ events Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-1-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1233; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=JFszVo8UdO0gHsfqleLS4i4GCE2Usu+8CNRMErdZNjA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV13rItBTh0MhfAGXPppt1+l62bg/bl8ERcsO VjhnvUm+kSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVddwAKCRBVnxHm/pHO 9SHjB/0e8TptwYDehqnWgRDkRzJphvAZdfwE2hOVtC0royHz/PfPulIXhcGq4MF3RwKOapgTpYz 9i6j9QSlGwFUWACSbhk+dUq0JUicGsDfHBminrfzhTw++hp9lfrcfk6qXwVJWR3eDgw7DrcC5TM li/MLxTXGxCOsk49iE/N1ZbF3BmPgdNN9i/UqkA0Geu1HIItnvDFUe1igXC3OmThfLZ+0luFeER 15yxARvD1+hU37iBQQcppMLRgLIyq8fn6ncavNqxGDMKpDV+CisR3j0GeVaATDtG5XOAyA1cBjK etXlhicihF/z2kRUp8NqGrLFom8F+U2zk+jqMYICoeweseQR X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Once the events are disabled in PARF_INT_ALL_MASK register, only the enabled events will generate global IRQ. So there is no need to do the masking again in the IRQ handler, drop it. If there are any spurious IRQs getting generated, they will be reported using the existing dev_err() in the handler. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..972a90eba494 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -647,11 +647,9 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) struct dw_pcie *pci = &pcie_ep->pci; struct device *dev = pci->dev; u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); - u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); u32 dstate, val; writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); - status &= mask; if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); From patchwork Mon Jul 15 17:33:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812850 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFD8A55896; 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It could mislead the users. Reword it to make it clear that the error message is actually showing the interrupt status register to help debug spurious IRQ events. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 972a90eba494..cda5d8fdc03b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -679,7 +679,8 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dw_pcie_ep_linkup(&pci->ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; } else { - dev_err(dev, "Received unknown event: %d\n", status); + dev_err(dev, "Received unknown event. INT_STATUS: 0x%08x\n", + status); } return IRQ_HANDLED; From patchwork Mon Jul 15 17:33:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812662 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D907155E48; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; cv=none; b=N1zt2OUIMjkU+oAAKaftPb1id0kwLzdaC7gxeFNQZslqU+k1sUe/LzTzfBDQ+vOvrcRAXIkGoknjP9qFrDZ9ScbtOff9cbQ1hI7PnTqJDXNWycvAgULFQIX+gASblLIgeappyDyg355pijpenQT2Z7oKESRI/Cbn98zElDRbvVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; c=relaxed/simple; bh=LRGU1ZUSjT7pMjV8SjmoQEmYcbLwDjL9G1AFtQWIDsM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T3LzI+ZCgUWXu5Zi54HBgKZ6ZsF+ZEWqAX0eUV6VzdcaLpXmbVfOJiXZ7gmujXaR0IbkIvKdcFt8+l0XeP/FjiVQVk/A13U40R3+TUfIa9DW7eqbJrdFWbzhh8IW4VeZkmJW3IasASo0pzcPkuSZZFMu5N2N1JhlHShLIVJVwVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Mzr7uV+8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Mzr7uV+8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8156EC4AF15; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064829; bh=LRGU1ZUSjT7pMjV8SjmoQEmYcbLwDjL9G1AFtQWIDsM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Mzr7uV+8K3jodRpcTwqfKCvE8yCXOXCM4+vRSkV7+Gi/c6Hdg6M9+P2SQzBR/66z4 DpIeYCAdwOcklN9/ymqfaje6Km8qAUxl1lbZqlb76Dh86ikloz59NFCToNV29pRzOq AgKxGtHuJodic4yT5E84FdqN7ximKMLRNqp3YCSOo/FZ3mO5lbD6qXAXRFX62glBys 3/Lg4M8LGOjOEVBgfY7wEXBHZSk29gaTC/OlAN/SOE0j/Ry08tb0RyK1gDod07nqRs xS/F/UdHj+QeyoGOoUzzkzBVQyMzLGavrIzxwnlQNf35CljLj1ijv7z2n3n6rnQ3On IsFtjvBmyhpGg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74851C3DA4B; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:45 +0530 Subject: [PATCH 03/14] dt-bindings: PCI: pci-ep: Update Maintainers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-3-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=988; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=hjExGhGjQYtIRypMJXzdJurZJRAD466HOf0lMqV3fm8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV14KYPtRgTg3g5EoPeN8522vVrQhN1qaY7/c kIik6AD35uJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdeAAKCRBVnxHm/pHO 9eSuB/9x6dRA5UTZGB8p96YqCmsRpqrOTNu+uvJvQVEwqOSETlWw4EnwEpB2LfPMRFLfmvUWBYt wdyMR3qpMNxZgBlhnpz2eD7u0f6c4Mo1xkYKUBMzR4i7+rsGeV2ytOX28WYDiPdXtdF7nt156KJ ExX80HAXszwxIUdGz3aovIr9cZV+xsmPvsLT9rBaXy6ax/2elU8LtYdJTB/fj430YEji5KeBvzc TeBFn9SyiQ4VPaUr88aQht8PvKDy3hupt52CtnHcIWVWi1r+V4M+ZQPqb5WnpRQ5pM33nt32Qfn GJjVn5Kr8wTiI5v920O+QkgudZkDT2he8eJ3xokaafDC7KpE X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Kishon's TI email ID is not active anymore, so use his korg ID. Also, since I've been maintaining the PCI endpoint framework, I'm willing to maintain the DT binding as well. So add myself as the Co-maintainer. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index d1eef4825207..0b5456ee21eb 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -10,7 +10,8 @@ description: | Common properties for PCI Endpoint Controller Nodes. maintainers: - - Kishon Vijay Abraham I + - Kishon Vijay Abraham I + - Manivannan Sadhasivam properties: $nodename: From patchwork Mon Jul 15 17:33:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812848 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D909356440; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nlxo+Aq0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 945E4C4AF16; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064829; bh=JodG2X/6iAMSp3kPrYKmjLQmZw4WuSJ7AGPo4O5dqYE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Nlxo+Aq0mSRrMKNVBH2zTC1llFUIi7qB6dnngDD4S620PDaXF4Ly7qpTBnpWwsZvL Vg7obPVvz+mdrIU70bO5PlIoZ+gbuEY6uNlWgKKFcwJH5QL0erJq6JPNfsAV7B/H2y YsCxrrK+WTZuHkq55ikPVBaFERW5Y62oTYONQ9+hU+/0nYr+CF5+2eQJAY/G0gAl6l OFV4sB+Gb3FT6AgrCZKO42JLiuJ4tytYu+eFrYGrrH6GogWphVZLiLkVI4DqHgHiYP aoFJwMJvxw71h0HVhCZH2SuTwz81/mOQLC2BMvVkEGUv5Fd/z9RZ/bVLfiwlia014O m8Ix561W0PTug== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88090C3DA61; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:46 +0530 Subject: [PATCH 04/14] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-4-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1493; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=AdGl5m97uW0nytJxHIv1uC0b7XTjC/3siXK0QubHe3A=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV14F9MHhAndakYHmQubDUeQEqYLKrlW9Kq/s a1PHQeg2yCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdeAAKCRBVnxHm/pHO 9RR/B/9xARyrbyS7qtcfVGThO0D22TMAVIFcHJjlb98oUOxms57Sz7OYbCh6MVwSk/ZfHGLEEwk uOfxUX/ficqQlv9euJIo2MNUoS/Z9X+/LmQctpOTyRa/DQOb1TQlBQc5mPSQI9JWvAyOuUkc+YM Gscnc/N8+05NATJ+7HOOImp8lvpoyMsQuFnl8Uf/LjNGMLNIBP1qN27ItK03xnozskJeYxPdFnE ftz6QmvjCLR5Fwx1KIsctuIb7Alb2dQhqz4eFZbAyni2Wn0El58ZG9w7wYmzGl6K/eAtsL5sh6z bxX5HVZzv0o0cKb0H5uEwNEYfyF4snrcXdWd9BuPZYwiubI6 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index 0b5456ee21eb..f75000e3093d 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -42,6 +42,17 @@ properties: default: 1 maximum: 16 + linux,pci-domain: + description: + If present this property assigns a fixed PCI domain number to a PCI + Endpoint Controller, otherwise an unstable (across boots) unique number + will be assigned. It is required to either not set this property at all + or set it for all PCI endpoint controllers in the system, otherwise + potentially conflicting domain numbers may be assigned to endpoint + controllers. The domain number for each endpoint controller in the system + must be unique. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible From patchwork Mon Jul 15 17:33:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812660 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 305D37172F; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; cv=none; b=WPePuyjv5sP0GNlTq8Ti0U8TjwZd4RAaaQVdKQI0tnmHovp/5xaPekZ5uDhMVQxfMw/L19NeLILGs+EJJGkXdYNf1wagDi4Ax3znX5qN9sjTYzyHU8H6UKh7sdn3LDtEy9SKE9bxD7yCXL3Kr39Pi4qXJSMTfS2Ba7geWZtQG88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; c=relaxed/simple; bh=VDKSHzhinHhMd2hc1HddY9yOlQzYGMP04iRbR68jXgc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UcJaQZgBwt1ifxG4rX8rOSiVP5eSB/lIKbo7Q/sPWkuRgEYHf9Wz/RaVb15Hq45YMvp5vjpo1HAmDJu6wW/gfpUwKbH7PBYCybVk7Hk8Do9dEPOElJgdJNQL7/ftSXdV5h4Wl6nG8wD5vhL1WKCAIIIJdlmoYf9zhLtNC6yCNH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ou0Pq0AR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ou0Pq0AR" Received: by smtp.kernel.org (Postfix) with ESMTPS id A239AC4AF1C; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064829; bh=VDKSHzhinHhMd2hc1HddY9yOlQzYGMP04iRbR68jXgc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Ou0Pq0ARmDSwfRaqSdp+ax+sOe9Hj3aBWPPm4jJV2JgYSe17rsM1wu6xafLa/eNMT m4qQTHgbN//nMRq7kJvc0cwAO2S32lGNRehX+rzl8E7eoEXAcQR8EGEFYsWKVdRuZr tzxREtUFZPevDr16kmaoL3WExOyKahLKKRcPdWxPCd9Fsz3bqdy9VhtldMf3JbcG1j HCY6Ua/kx+UjYOOMb1pStOxR3uUj5+XA2gb/iZsux4EgEWTxHWmFFGkePYuvbqXHSg xYfrOECZKXOaGb+JfxaTTnFGZTg2rT/GwVyYl2duzSb9Sb+ZIO9jtZWGHhuhwwLK9y U+VK4Fv7iJ6kg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97756C3DA59; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:47 +0530 Subject: [PATCH 05/14] dt-bindings: PCI: qcom-ep: Document "linux,pci-domain" property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-5-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=988; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=4/Y3NDpzD8Z8CE/W/YJnbzDjm+Dvqo0pEX0LWeYt20k=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV14OxNu2Wouvfh0sC2iqACXk4KaF46EPflGP K5SvUq1GKOJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdeAAKCRBVnxHm/pHO 9ZRqB/9aiqXGr2qOBpgTi78f/kJz/f1LUHV2LmgvzXET9Xqx2UNmEVcAilBQQBSZK52d6X4PBxv aWJ1oX8Zue/z2xEAHNwZIjg/wR/hFMku4gJNvheAE3UrigmeKAgd2aiIHEI7FVZ8SbJwCe/5QHT ADzYloawz3PUkbN6zWNY0S1mag5KAW1nWGsjbYfKCx5sNqfTMMFOT1ZdJBpdDXgmLnNuAbEGCnl l0yTmZ0jDL1tYtYO+5AgKlVF7I/3q5GlfL6Ps3EqFVbCT/epaLH0FK2OO1VseRjmrpocaZf89YA YWyMEcgnFosgHbVde+NZnLhEzA36wQHjoVhcHEgvw1CHn9Ci X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in a SoC. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..1226ee5d08d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -280,4 +280,5 @@ examples: phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; }; From patchwork Mon Jul 15 17:33:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812847 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 004AC5EE97; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; cv=none; b=ojzdhOdpX6+B2LQSzc0nhkaG5G/clfVBpnDzjd9PYYql6mD1NLcJGn/Eav6W6SFnZbSQaWYz34DO0uc5mh0SnhJ9FWRXBWzE0xB+vBs/UXO2Mb/HtelrPgGwF8ZWdimFpSbgI2B6T+083a7Qgo/J7WhuUGPIrT93+O097hf8Psk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; c=relaxed/simple; bh=AqLKtDzeOWTpfLlD5Nunw5Lx2M3YMLzkFuSgYFTXBK0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DfSrcdG0C21S+D96Q8kDl4jHZ4DM8cJ2W9v+jpzJjHzU1iKkXcvoznQ8p8hCrZn4mEuFNxZa1RukwCQ2DWIXYPJsnSHpoNobdhDeOAVZ+3m7o3KK+uVsWjIYUO30g4JJWl/7RsZhG6aEPLLtrMddtRU9cBj+C9iyxPwayfz4d3w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cz8UW8mr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cz8UW8mr" Received: by smtp.kernel.org (Postfix) with ESMTPS id AFCCFC4AF68; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064829; bh=AqLKtDzeOWTpfLlD5Nunw5Lx2M3YMLzkFuSgYFTXBK0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Cz8UW8mrn7ilYlUyn/ZEjHnPBbOTbPqmvtEZOEMr0dxoJvZ9/8fIMn8y8VfzPR/nD oKQ7YmIxp281g9QGtVH0EeO+omxQ/AqDv3KJYXLbIiW5GlhzvSSfwHdS1PycRGNW7T rd5QvH4vOwgdI6Cm/Hlibkm2Pqjj1VoBFcQoDLNTAJpUlQexYq7ncADIhpduaUp8IL mu+4VCX4zsIYUjWjonIqDWBnL/6yJ4kEycvP59oX7knbN/hGeLT0eHqPyZ6bewqslF CNZZMdYGYSPLsD4M4VVlSHBuJEXQ9ebGpRjTiDMniwlDpMrGlPao/OENZ7ZZo74jaH Wny2zli0OjYHA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A371EC3DA4A; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:48 +0530 Subject: [PATCH 06/14] PCI: endpoint: Assign PCI domain number for endpoint controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-6-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2371; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=BECkU4Os6kOoCK6Qfv68t/qW5FxIjT+Q5kndhCEtOC8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV15F+kcwS5+/FEQPBlLHWbPgXesdW/M72MTi jRCb9LZ6RqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdeQAKCRBVnxHm/pHO 9RpyCACSS3TlQfGlFVAKsoeJSe8dQG6CTaoBm5QHJxDiod8PIj9/kepgh3unKrlSjKH3NrHA8LW T3mT1GOAXHTeIculrZKZ2LCZSTWEWutKG/mDGXR3oNv2GC5E2EY5cF32Yrwd/RMWpHG0vuKkrpx yKjDMh3zTPOZDOzDIPe1F27RsgmoQVqgxdk9+DwrluZJjz9eXfKaWj76Axnupy6Nc1TPRFbhO53 6zbJvq121HlgtYIRoChhSY0o7vopBiQk74jL4WKtUgZzh336aWq2cUi9+7mjkNaB9zRIV13FAGZ jWFYl5ADIqCZIGgQKl6raghKvnk0G5DqL7/UB1lI+BkxYv7W X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Right now, PCI endpoint subsystem doesn't assign PCI domain number for the PCI endpoint controllers. But this domain number could be useful to the EPC drivers to uniquely identify each controller based on the hardware instance when there are multiple ones present in an SoC (even multiple RC/EP). So let's make use of the existing pci_bus_find_domain_nr() API to allocate domain numbers based on either Devicetree (linux,pci-domain) property or dynamic domain number allocation scheme. It should be noted that the domain number allocated by this API will be based on both RC and EP controllers in a SoC. If the 'linux,pci-domain' DT property is present, then the domain number represents the actual hardware instance of the PCI endpoint controller. If not, then the domain number will be allocated based on the PCI EP/RC controller probe order. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 1 + include/linux/pci-epc.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 84309dfe0c68..7e8bf4ac003a 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -899,6 +899,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, epc->dev.parent = dev; epc->dev.release = pci_epc_release; epc->ops = ops; + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); if (ret) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 85bdf2adb760..8e3dcac55dcd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,7 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @domain_nr: PCI domain number of the endpoint controller * @init_complete: flag to indicate whether the EPC initialization is complete * or not */ @@ -145,6 +146,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; 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Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:49 +0530 Subject: [PATCH 07/14] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-7-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2451; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; 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This causes 2 issues: 1. Pollutes the global IRQ namespace since 'global' is a common name. 2. When more than one EP controller instance is present in the SoC, naming conflict will occur. Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ names to uniquely identify the IRQs and also to fix the above mentioned issues. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index cda5d8fdc03b..a0847eef0645 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -711,8 +711,15 @@ static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { + struct device *dev = pcie_ep->pci.dev; + char *name; int ret; + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); if (pcie_ep->global_irq < 0) return pcie_ep->global_irq; @@ -720,18 +727,23 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, qcom_pcie_ep_global_irq_thread, IRQF_ONESHOT, - "global_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request Global IRQ\n"); return ret; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "perst_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); disable_irq(pcie_ep->global_irq); From patchwork Mon Jul 15 17:33:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812659 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4277C73467; 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a=openpgp-sha256; l=931; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=kwx7QGYogFgH9r43zYyha4gga2vYwsd4o33qhsGds+k=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV15CSE+uo3sq2/IU8wwhr3HPQhoooREAXiTf 2moyV4AIy6JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdeQAKCRBVnxHm/pHO 9euhB/9SeAVltwvnAJZ+YRfNlsDMbN7Uj/QBB1xmDKKYJ1sL5L26gF9CoVkGnA6K8E0SXy9Gc+A NTb8XstE7UvbNDOMutorOlKNUIXv+K1/lxQkbT1xZIxKhqO7R5TGH9+IkEmHMDkr7P7hHoIuXdm JPWPepg3a0a78frM+9WUf6zIvSzTh/VL3fTomMstjc/k4BH+mLwhJ/9i6dJLyXCf72NPjX5r+iP UuS+5RRveledStbcaGGWSg6crWKVO4ewA8oWBNiR/tlFNBv2BY7Hlo7hx89SafZT70tCDpRczmB ze8I8CbxVJS84qqvpCnThxQj8Pd09GoBt8yxELZyQfO0qUzQ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Mon Jul 15 17:33:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812845 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 403CF73462; Mon, 15 Jul 2024 17:33:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; cv=none; b=n+6fo1ZholsGqIkfnE817biJhe7tINOYVXaB5r9OyDqQSvZKThjCY1XGHTMP3+mVevQw19QLZ8Yees8jpwUN5tPBfTfoG7GjOLos0oChFqo2JWH7M4OeCX3GAqiA/ebB+UAkdCqAHpFFh+qsdhZxHG8RgNxtdiM0NV1fTKA0pmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; c=relaxed/simple; bh=uf2gmip5094Xe/ELLjWs+bvQfphMpBDzXrzLLgYLAUE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qXcnBsnmKxLuQRV2su/TWkkmb6akZMHZ+3NaLvhv91v6rE+vkqwYcgXMXtBendCG9do76P5G4LJ0BEEusknzxDXU6PJNKRga8MMyWzAVRNEKwcEyUXgAsrmMpLB/w4F7IVl1pcAfLJNTOSvrp3+UeHjOMfrOJ2/IImsnMY+hvV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZeAHLaQK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZeAHLaQK" Received: by smtp.kernel.org (Postfix) with ESMTPS id D8905C4DDF1; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064829; bh=uf2gmip5094Xe/ELLjWs+bvQfphMpBDzXrzLLgYLAUE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZeAHLaQKECA6DixHkpXmrQd3abxj3/ZpiFkmEL9SuZBsg+pb4Y0raxj+Onj7rf+nl Xof8UTC4q2eKMc++EypFRE6WuLkrdfiXpECnsOcL+j0V8F9V7xs12Zxq3rq8nyZY8Q 9J2hr+r+15XReB/tD5EZtvuopbmftKzB6aUSzBE3AUZi9+JTqIPXo9G9RyEnM5Ximb WaAYd9ndBsuSXRYzAkdjw5LTpS+p2b9SfcRI8or6zXdWk3r4gq57F/QSg09VbkLo5C eqHXOCmgX16d4wk/JzNXkObtWCHHd4OV2fhS3+eSU8itZkcLnRhEXueNz73tNmN095 aMoctYu49hEGw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D017DC3DA59; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:51 +0530 Subject: [PATCH 09/14] ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-9-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=906; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=csDoZP2OLES7tPZyHjq00PkbEc3m+4OOmtcZKbO5fqQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV15ILF+SBcNiGMrBAY25nZOAZu7j9Kv2LBvw ZMFFcRVTL6JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdeQAKCRBVnxHm/pHO 9Sv8B/4yrtadvSEQqOUXqW6F0dvNf6+Zln9x+SGI/lNhwGwZqkjc55QHUCEyTPwRmWWUB89jP78 q0a/m4kXRCkrAYxsPcLRwJmyUY2zqh2/k5Cih1iFqcNbqALrMSRxQ9rXxNbQ7uKkbOZsRCS6lsB YkfrQbRNZouw7BU7+FRVa1y1NQdCMVbKIdoJVD9XeD2xVFg0v9RrpIssIZ6WTmoAgyOFq6EEr3D rzbwgTcqBSwcFaW5M+oKVS8BLg73fwMqX6+ZofQH5DNK2mhRVUHfwiGyjV2M56z/3hlzvbTqe3a 9wZ5g8IytbMFVCnWUEEFo+0xViAHeDhrpmr8nN6BOeWNSu7f X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX65 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..fcfec4228670 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 { max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Mon Jul 15 17:33:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812658 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64E8B78C6C; Mon, 15 Jul 2024 17:33:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; cv=none; b=lVeO3Ybl2K2ulbMAWbQvQTYj33aqsHzmp6CrDMBi/bXSxnKu4gvscVlMAbZgMjvPrdgt9RsDXjgALMIFKpYU985TXWgTCH3WVeKYnJZJyAC5hCDk6+A/Y4pRm7dE2GgMnjkVBT7s9fZi06/eVmy+OyM0dDUvt4R5LxwcLCTHtZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; c=relaxed/simple; bh=RQxgelkyLN8Ts/HTeZBS0QZuoUf1hPKhZohT5VJ5sqM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FHK1/z9YvaJ1qnq/vxKpaCSTBUhuVWA346REul5KdC2aaXTpAWVmHjWojW2BuZgJYJGj32HeSDRipP4NRD4PQD/BjSj4Xw58Wu0oLbWWpE56/hD02YeF1zUxqwKWixFophY+tl7FatZip1qYN5Hi4yTrE5Jk6sM9kj775OcS/pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B+RknX5M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B+RknX5M" Received: by smtp.kernel.org (Postfix) with ESMTPS id EF8D3C4AF0D; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721064830; bh=RQxgelkyLN8Ts/HTeZBS0QZuoUf1hPKhZohT5VJ5sqM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=B+RknX5MeQRmZ/kd4fnU8RSCgroHa5yOjbwuvrY2cGaBWA/OP2FNJfxMYi5ja0RBM qQDS9FSLzfwMH1p9y8PwK/jE51VRxvxW22RkDRot5gxLLJq2HZewK0SGJStNJAeeyS B+vZNzU2ba3Z5Sbw+cggFsGxjpjf3idAlgswRl79e5Klku87E8Ir5exBQG1m9S/jgy 5wY2B896UYNw7erCblX9hqzrQWPLZKBirShHc8CBZkAOQmfUS9NrMu7r369a1kvtsY vpSh6ARjR6MIgKhJAjK3leDN2ofZxOzeOb5RsGdgFzZgXDhWotiKan3mERRlXvlz6J /0v0etCAQTLyw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3A5DC3DA60; Mon, 15 Jul 2024 17:33:49 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:52 +0530 Subject: [PATCH 10/14] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-10-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1234; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=yEgvSXmb27DZa3gudFLW4zQMizODQlbDCoGJB1twpkY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmlV16mrEo9NAV0hiS5F8uIuEUCRNSQ3KaNpcjJ xlqNZmego+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpVdegAKCRBVnxHm/pHO 9a0UB/9rL1u5DYb4E5GiDOZUSXZC+9jk0Sxesl5D3WH2U2toRZncQIw6kUqORTEnnyoTGA/gYsr DpZJ3HVigPzTH4uJIwNDKBX+9/9CaaPfkfXbxMBhix1cI0dbX1NJ4QXSAkQhAsbk+qt+pZNBSMa 7oTrmIgYW0Ptw/LQ0pdXv5dYsg2JX20BMyYhl500pLJj8CPzihAb+7qgFgR5IgjuYdSW4H3OYkV yUt4wSE9GhhGCT3D9Clor1IvW0sPTeaVv8udq5s0QeX6zsREGU57pF1ozrWsXqVBgD9MpNsY0WZ OF2AcDFy4RofVwZ6G2h3zxK4W90JPVcMpqBOEC6vqbB5H2k4 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SA8775P SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..198b39abde97 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4618,6 +4618,7 @@ pcie0_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -4775,6 +4776,7 @@ pcie1_ep: pcie-ep@1c10000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; + linux,pci-domain = <1>; status = "disabled"; }; From patchwork Mon Jul 15 17:33:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812846 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3930B71750; 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This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0a39bbfcb28b..704c0f58eea5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -21,11 +21,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 From patchwork Mon Jul 15 17:33:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812843 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B9F9770EB; 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This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index d8c0afaa4b19..0d68ce073383 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -55,11 +55,12 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 interrupt-names: items: + - const: global - const: msi0 - const: msi1 - const: msi2 @@ -142,7 +143,8 @@ examples: "aggre0", "aggre1"; - interrupts = , + interrupts = , + , , , , @@ -150,7 +152,7 @@ examples: , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", + interrupt-names = "global", "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; 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Mon, 15 Jul 2024 17:33:50 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:55 +0530 Subject: [PATCH 13/14] PCI: qcom: Simulate PCIe hotplug using 'global' interrupt Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-13-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4567; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; 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So when an endpoint is attached to the SoC, users have to rescan the bus manually to enumerate the device. But this can be avoided by simulating the PCIe hotplug using Qcom specific way. Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt to the host CPUs. The device driver can use this event to identify events such as PCIe link specific events, safety events etc... One such event is the PCIe Link up event generated when an endpoint is detected on the bus and the Link is 'up'. This event can be used to simulate the PCIe hotplug in the Qcom SoCs. So add support for capturing the PCIe Link up event using the 'global' interrupt in the driver. Once the Link up event is received, the bus underneath the host bridge is scanned to enumerate PCIe endpoint devices, thus simulating hotplug. All of the Qcom SoCs have only one rootport per controller instance. So only a single 'Link up' event is generated for the PCIe controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 55 ++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..38ed411d2052 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -50,6 +50,9 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_INT_ALL_STATUS 0x224 +#define PARF_INT_ALL_CLEAR 0x228 +#define PARF_INT_ALL_MASK 0x22c #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 @@ -121,6 +124,9 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_UP BIT(13) + /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN BIT(1) #define RD_NO_SNOOP_OVERIDE_EN BIT(3) @@ -260,6 +266,7 @@ struct qcom_pcie { struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; + int global_irq; bool suspended; }; @@ -1488,6 +1495,29 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) qcom_pcie_link_transition_count); } +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) +{ + struct qcom_pcie *pcie = data; + struct dw_pcie_rp *pp = &pcie->pci->pp; + struct device *dev = pcie->pci->dev; + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); + + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); + + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { + dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); + /* Rescan the bus to enumerate endpoint devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(pp->bridge->bus); + pci_unlock_rescan_remove(); + } else { + dev_err(dev, "Received unknown event. INT_STATUS: 0x%08x\n", + status); + } + + return IRQ_HANDLED; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1498,6 +1528,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; + char *name; int ret; pcie_cfg = of_device_get_match_data(dev); @@ -1617,6 +1648,28 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", + pci_domain_nr(pp->bridge->bus)); + if (!name) { + ret = -ENOMEM; + goto err_host_deinit; + } + + pcie->global_irq = platform_get_irq_byname_optional(pdev, "global"); + if (pcie->global_irq > 0) { + ret = devm_request_threaded_irq(&pdev->dev, pcie->global_irq, + NULL, + qcom_pcie_global_irq_thread, + IRQF_ONESHOT, name, pcie); + if (ret) { + dev_err_probe(&pdev->dev, ret, + "Failed to request Global IRQ\n"); + goto err_host_deinit; + } + + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); + } + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) @@ -1624,6 +1677,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) return 0; +err_host_deinit: + dw_pcie_host_deinit(pp); err_phy_exit: phy_exit(pcie->phy); err_pm_runtime_put: From patchwork Mon Jul 15 17:33:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 812657 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DDB38528F; Mon, 15 Jul 2024 17:33:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721064830; cv=none; b=pu6rVq6xU/rXTkhdz5FO5uwpYZ5ddfdhESXPzhfJd/rpAE77CZUnk0Z7uz0B9TxHKVIb75KMLQ2tyyRiOKzn0f9s8d3KI8wz1kfWU1YzPfvc9wPNRnCp17TgmowXPm3yB6BkDrY5oTzmYmgWXiOmzQgWQ7qcE/B0KP88pWf+B4I= ARC-Message-Signature: i=1; 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b=qdkYlrCwtSFUJC9ZJszIIbObJkcdGSkfQwpJ7/80dapQsO6O+uD3nYiDn0VHOLl1q Q5Vix4ZfHiNboEpxWkDFLz/qPTt+YckjPj1HMVlSEeEmk15creJo5d+7wg7ba3INbd 33UvqaD6Fxhb1DIQYKWTN2Izv/AUxZRk2IR8d2YWt+73fVluo/BwKCVinhfAZeU63c LYch3u7NAJmRMm+0d7/ZbS3/7f0P7bQivcyYbQTH2xN6/ZjRuuH9raIMPWalcLABtv q+AafLHVo4kNTd+GZMrFQ4AJcOKdxTDEaOG59KVkKF6H5KFf8WGSrlU1FAfexPfPgO hlambGgdUYdlQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48D0FC3DA59; Mon, 15 Jul 2024 17:33:50 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 15 Jul 2024 23:03:56 +0530 Subject: [PATCH 14/14] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240715-pci-qcom-hotplug-v1-14-5f3765cc873a@linaro.org> References: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> In-Reply-To: <20240715-pci-qcom-hotplug-v1-0-5f3765cc873a@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2237; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=gNxsaYyTdguve7w+Y8w7ph9rzM45Fb14SQIqKjXqzUk=; b=owGbwMvMwMUYOl/w2b+J574ynlZLYkibGlsd3Gj04rNd09RrIryyaw6cU5eY9bfz5ialA+ovz lRdvH2LvZPRmIWBkYtBVkyRJX2ps1ajx+kbSyLUp8MMYmUCmcLAxSkAFznC/r+ePWP2j8B7p3wk PzIz1LC/Xi9r7d5W8cTtt2fkowOvbjN+ff98NePf7fbPls/k+8bYGCtsMOXYshu6sl+L0wrCvKz CVG0/KYVFhkgdLWXf5iERxvt2mYXe3INmfCVFwlNiL4otsYuvNvVdWZb47/JGB0d+4dJt7QtiTv qq2yjdWWrsFOZvGSJ3+nHM9nQL78+dJwp0+7vLL093z/e3mKJ645ri0qnny4JLJtp8dZgwkVudf b7MvNrPl6oPVFyctifC3e9agEpIQVPeYzHfyLCyGt8vt39X8rqfVT92ZKczy5KyF6fT6+eZnllz fdd8y5sPYtz0Szx/9d8tOLLKtJY1P8er33DezpkeHbPbAQ== X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..90d16cb83669 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1780,7 +1780,8 @@ pcie0: pcie@1c00000 { msi-map = <0x0 &gic_its 0x5980 0x1>, <0x100 &gic_its 0x5981 0x1>; msi-map-mask = <0xff00>; - interrupts = , + interrupts = , + , , , , @@ -1788,7 +1789,8 @@ pcie0: pcie@1c00000 { , , ; - interrupt-names = "msi0", + interrupt-names = "global", + "msi0", "msi1", "msi2", "msi3", @@ -1942,7 +1944,8 @@ pcie1: pcie@1c08000 { msi-map = <0x0 &gic_its 0x5a00 0x1>, <0x100 &gic_its 0x5a01 0x1>; msi-map-mask = <0xff00>; - interrupts = , + interrupts = , + , , , , @@ -1950,7 +1953,8 @@ pcie1: pcie@1c08000 { , , ; - interrupt-names = "msi0", + interrupt-names = "global", + "msi0", "msi1", "msi2", "msi3",