From patchwork Fri Jul 12 02:25:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Li X-Patchwork-Id: 812382 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF4228F40 for ; Fri, 12 Jul 2024 02:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720751124; cv=none; b=rN+lt819pMYmTAbXasbILIaTGvLroe/bwycXyDjMQiIxy5OswYYewFZZxpXv4M9tJYJl4PfkC2kKtQhw4Dt4BsKjZCKI4k0lHRNCgez3GedBoTOzS5SpFYqXBJ/xBo/V4eVu2xpIAbnv2XduhzTZZoxLkNFjJz82HFoNl9yJN8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720751124; c=relaxed/simple; bh=aGd1sizhcooFMgmr3C2yds60hHkkCWf39YYSay86y8E=; h=From:To:CC:Subject:Date:Message-ID:Content-Type:MIME-Version; b=pBmZpeRRB6M71T952OgWnaWPqNQvs/S5nfIDKvZ4dqgKkCamc8Yqxm7qWBio6I+z7a41jP2GVTW14CpaZzZyfk4XncJSjRBfGpC03Rd7QDBAHfHe0rGo68luSdEa6yOFApuivjxGZ05jwgVgkhnKSvePOSdBe4hpn0NS+KbkB58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=Xp5X9jWa; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="Xp5X9jWa" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 863FA2C04A8 for ; Fri, 12 Jul 2024 14:25:17 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1720751117; bh=+m9eddoablMJb5kAuCTNXGFBZi9G2XML0AsbSpml5d0=; h=From:To:CC:Subject:Date:From; b=Xp5X9jWaZ3jpYV0VoienNoe3f+5GmesuDQU7VyEiIN8bP7tfuMXH73vGjtmd9hXiE p6UeEVsEFCWRLdwTtstKP4nJSY/2+cDYICCLfcnREguAs2B3+z2faEr3OiR/xOHaoL Qt9VPK/Av5doPGT8jYEL9NBB3+QgdMSP3HEGpJ3Y77yl70nf7n0Zj1oDJK7pr5769V X36zH9EJVBizrX7garMUUVmvtxjsrV7JUigtibzhf9SN86FbzsRha5fewzpnYv/DYz urfV8u6h5DK5rV2QWEEbqTSPELXghhH17aPm/2WhkXCKF77CW5WvrdvEgzMokKRLcH h0DehJg7zJNmA== Received: from svr-chch-ex2.atlnz.lc (Not Verified[2001:df5:b000:bc8::76]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 12 Jul 2024 14:25:17 +1200 Received: from svr-chch-ex2.atlnz.lc (2001:df5:b000:bc8::76) by svr-chch-ex2.atlnz.lc (2001:df5:b000:bc8::76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 12 Jul 2024 14:25:17 +1200 Received: from svr-chch-ex2.atlnz.lc ([fe80::a9eb:c9b7:8b52:9567]) by svr-chch-ex2.atlnz.lc ([fe80::a9eb:c9b7:8b52:9567%15]) with mapi id 15.02.1544.011; Fri, 12 Jul 2024 14:25:17 +1200 From: Bruce Li To: "linux-i2c@vger.kernel.org" CC: John Thompson , Joshua Scott Subject: [PATCH] i2c: designware: Adjust LOW period of the SCL clock Thread-Topic: [PATCH] i2c: designware: Adjust LOW period of the SCL clock Thread-Index: AQHa1AJ+qtQNOJ23kkKxXnIe8dOh8w== Date: Fri, 12 Jul 2024 02:25:17 +0000 Message-ID: <7bb85fcde1dc477bb897d89dd0ddeb3b@alliedtelesis.co.nz> Accept-Language: en-GB, en-NZ, en-US Content-Language: en-GB X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=PIKs+uqC c=1 sm=1 tr=0 ts=6690940d a=Xf/6aR1Nyvzi7BryhOrcLQ==:117 a=xqWC_Br6kY4A:10 a=oKJsc7D3gJEA:10 a=4kmOji7k6h8A:10 a=kU-gcKmB2DDcT0F4TUAA:9 a=wPNLvfGTeEIA:10 a=A7ShnFVUAiA_a_dl:21 a=frz4AuCg-hUA:10 a=_W_S_7VecoQA:10 a=v_9zwqxW9pQmHRz0AkQA:9 a=B2y7HmGcmWMA:10 a=rVnDm9A_-c-k2ki-JAcA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 Hi i2c list maintainers, This patch adjusted the LOW period of the SCL clock for a more accurate i2c bus speed frequency. The given LOW period of the SCL clock 4.7us would result an i2c bus speed of 105kHz (observed by oscilloscope). Using 5.2us will have i2c bus speed frequency of 100kHz that match the setting of I2C_MAX_STANDARD_MODE_FREQ 100 kHz. Thanks BruceL >From a83ed73f0a17eefea6a39d4723b6247612550ad1 Mon Sep 17 00:00:00 2001 From: Bruce Li Date: Fri, 12 Jul 2024 14:12:14 +1200 Subject: [PATCH] i2c: designware: Adjust LOW period of the SCL clock This patch adjusted the LOW period of the SCL clock for a more accurate i2c bus speed frequency. The given LOW period of the SCL clock 4.7us would result an i2c bus speed of 105kHz (observed by oscilloscope). Using 5.2us will have i2c bus speed frequency of 100kHz that match the setting of I2C_MAX_STANDARD_MODE_FREQ 100 kHz. Signed-off-by: Bruce Li --- drivers/i2c/busses/i2c-designware-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index c7e56002809a..ec731390947c 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -71,7 +71,7 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 0); /* No offset */ dev->ss_lcnt = i2c_dw_scl_lcnt(ic_clk, - 4700, /* tLOW = 4.7 us */ + 5200, /* tLOW = 5.2 us */ scl_falling_time, 0); /* No offset */ } -- 2.45.2