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Tue, 9 Jul 2024 14:54:04 GMT Received: from tengfan-gv.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 9 Jul 2024 07:53:58 -0700 From: Tengfei Fan Date: Tue, 9 Jul 2024 22:53:44 +0800 Subject: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240709-add_qcs9100_pcie_ep_compatible-v2-2-217742eac32b@quicinc.com> References: <20240709-add_qcs9100_pcie_ep_compatible-v2-0-217742eac32b@quicinc.com> In-Reply-To: <20240709-add_qcs9100_pcie_ep_compatible-v2-0-217742eac32b@quicinc.com> To: Manivannan Sadhasivam , "Lorenzo Pieralisi" , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley CC: , , , , , Tengfei Fan X-Mailer: b4 0.15-dev-a66ce X-Developer-Signature: v=1; a=ed25519-sha256; t=1720536832; l=1616; i=quic_tengfan@quicinc.com; s=20240709; h=from:subject:message-id; bh=q183F0/HFGC/8U/gLjzUqH8Bv64w+2hrHp8UiRG815A=; b=x91GX2Ia9pAYVTMaewFVd/hPIWWGFBfLU9N3N31guIhozOdaji+JGEv53rHm2j57YMAwZaRjQ bxidEQXStQACkxrVqP4TSNMgIABdpoeiMlDzBCF8kmH5q0o8gWmFTuS X-Developer-Key: i=quic_tengfan@quicinc.com; a=ed25519; pk=4VjoTogHXJhZUM9XlxbCAcZ4zmrLeuep4dfOeKqQD0c= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AA7X_SZwvdZ6RL3bOpGGaLv4OhPi776m X-Proofpoint-ORIG-GUID: AA7X_SZwvdZ6RL3bOpGGaLv4OhPi776m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-09_04,2024-07-09_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 mlxlogscore=970 priorityscore=1501 malwarescore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407090097 QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, so add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device match table. Signed-off-by: Tengfei Fan --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..e2775f4ca7ee 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { }; static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", },