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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a1f22acsm210426605e9.24.2024.07.09.06.45.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 06:45:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: Fix handling of LDAPR/STLR with negative offset Date: Tue, 9 Jul 2024 14:45:03 +0100 Message-Id: <20240709134504.3500007-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240709134504.3500007-1-peter.maydell@linaro.org> References: <20240709134504.3500007-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we converted the LDAPR/STLR instructions to decodetree we accidentally introduced a regression where the offset is negative. The 9-bit immediate field is signed, and the old hand decoder correctly used sextract32() to get it out of the insn word, but the ldapr_stlr_i pattern in the decode file used "imm:9" instead of "imm:s9", so it treated the field as unsigned. Fix the pattern to treat the field as a signed immediate. Cc: qemu-stable@nongnu.org Fixes: 2521b6073b7 ("target/arm: Convert LDAPR/STLR (imm) to decodetree") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2419 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 223eac3cac2..f873e8bc8b9 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -520,7 +520,7 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm &ldapr_stlr_i rn rt imm sz sign ext -@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i +@ldapr_stlr_i .. ...... .. . imm:s9 .. rn:5 rt:5 &ldapr_stlr_i STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 From patchwork Tue Jul 9 13:45:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 811439 Delivered-To: patch@linaro.org Received: by 2002:adf:ee12:0:b0:367:895a:4699 with SMTP id y18csp297527wrn; Tue, 9 Jul 2024 06:46:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVGhICppXl4Z/U95hRai1xpbTNu56RVYAqoElyEHWhX33HpdZW6egVe9N5sJuTPq/FU1zAARynzPMZwmc/sFGRo X-Google-Smtp-Source: AGHT+IERpamFhqCI5nylQXINMB6OVoAINpJ5YWnBIhMTqpZXHBi7IJiS9+BV15ARveQrgEjMI0tW X-Received: by 2002:a05:620a:916:b0:795:2307:97ef with SMTP id af79cd13be357-79f19a35f20mr302332085a.6.1720532803010; Tue, 09 Jul 2024 06:46:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1720532802; cv=none; d=google.com; s=arc-20160816; b=T9fmVRRsya5smo2vj36JW5xpN+JYdf6Fnkk+agM2c+pB+cQcxB9GEpYfrlVqnU3VdA q65qvEwmGvdT1HGTd9ziCbPe5RP5nN5/Zewq+9Zz7ImSc3Uw2YJyAOYJgG25uAvcMVhE nMN4aTXOOKeQTyB0d4DvhLswyw4BwbVEFt+VxN6k5L5yzVsfmTbSq6sQbDAZEL9tmT+Z ++rEG7O4DNDxWXdbZ4V2sjcI9Ij9YtxRfw/spb8Zz6oMwG0f/JP4BI9osMxogw5rR+qd bsA/IhchisKvON57c9gIB/pH1NzsAT7RVKSbfZL6PzQQOW0kNRTxwmtBJKhHP5NIPYVo /++g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6Dy9tTmWCONrl3V4OHSFlfMTEYKzq0YJeFJJEkMNS3s=; fh=PKc78taz+PkHZ2YeWQxRxAfC6k/pKJ2Mpxr0X2gP9ao=; b=z7T0BgbFSUr/Uwp4sMIrhKeFBmBVWObJEATX76L7kdfG3fVBAFm1jUc9/KC0B1L4v4 CHgr/itULvw1i8+RCEdrsNKbLj1Ucg8mwLONejilvybKALQU1xBUQyxFFmyMqwlka+cp bdkLERiU+XI/1AUkO53pwaPsisgY+Mz5dsEaJaxqGyaLVALjmvHK2x+dAm/o5S+CMxhj R4XOmCBiRbrFL/yd9rYcYHsB1MNMSrjQaDxpvgDKYgqK8pzWgkzaYAUipSLNlMMGw/Xk kBAcnbdo2/L+B65xF6/eK7uec19dkmRYKA8zb52cAcBxRYDQStqnvnB9fCrIhwSbAwib 01bg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=alWsvwfh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4264a1f22acsm210426605e9.24.2024.07.09.06.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 06:45:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/arm: LDAPR should honour SCTLR_ELx.nAA Date: Tue, 9 Jul 2024 14:45:04 +0100 Message-Id: <20240709134504.3500007-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240709134504.3500007-1-peter.maydell@linaro.org> References: <20240709134504.3500007-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit c1a1f80518d360b when we added the FEAT_LSE2 relaxations to the alignment requirements for atomic and ordered loads and stores, we didn't quite get it right for LDAPR/LDAPRH/LDAPRB with no immediate offset. These instructions were handled in the old decoder as part of disas_ldst_atomic(), but unlike all the other insns that function decoded (LDADD, LDCLR, etc) these insns are "ordered", not "atomic", so they should be using check_ordered_align() rather than check_atomic_align(). Commit c1a1f80518d360b used check_atomic_align() regardless for everything in disas_ldst_atomic(). We then carried that incorrect check over in the decodetree conversion, where LDAPR/LDAPRH/LDAPRB are now handled by trans_LDAPR(). The effect is that when FEAT_LSE2 is implemented, these instructions don't honour the SCTLR_ELx.nAA bit and will generate alignment faults when they should not. (The LDAPR insns with an immediate offset were in disas_ldst_ldapr_stlr() and then in trans_LDAPR_i() and trans_STLR_i(), and have always used the correct check_ordered_align().) Use check_ordered_align() in trans_LDAPR(). Cc: qemu-stable@nongnu.org Fixes: c1a1f80518d360b ("target/arm: Relax ordered/atomic alignment checks for LSE2") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6c07aeaf3bd..5ea204d5009 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3543,7 +3543,7 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) if (a->rn == 31) { gen_check_sp_alignment(s); } - mop = check_atomic_align(s, a->rn, a->sz); + mop = check_ordered_align(s, a->rn, 0, false, a->sz); clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, a->rn != 31, mop); /*