From patchwork Mon Jul 8 11:18:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 811267 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B46A79B99; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=Ge8UloQQxdPN7YESdkNrCgSW4B43ehlMSVbXEHjst/Go5KIC9EFxe7e3w1em8UvEA+DFWq/K/8gbqplpuX/83mqLqfsZTYbdgwzMYM71O0rR/XZp4bKquUtr++KraQbA6Fdohfdt9iecmSaylpcWzr4Ow6U0dp5e8W1UJdYHYHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=JWDF3uYI/wZ37tgeaDZgy9qmXzyOCRUzF9V3nIAkQKQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=moceSbInNBpgSXTW7NEwEfODNlCxmYZ4v1v0LFh566sH6YPjEaXtAEn6WcR7PhI2rHTm7+26eVqhkDVvgs/NjLyynTyafnEtcxLpormoc9sRWiqKyxvdfP10c6fY+qKuFchLeNgtqF8WMvjkj9mfnd2uwzXJMAgf1mZAQ5GBvAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uqnjomc/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uqnjomc/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09B2BC4AF0E; Mon, 8 Jul 2024 11:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=JWDF3uYI/wZ37tgeaDZgy9qmXzyOCRUzF9V3nIAkQKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uqnjomc/HoOLZmpDetAlgAqPTNWzFNB5H6+GGvWxjZC09QQmeFEdWsmuZNS5P9og0 9usjO/l0OkjCZq5vy6mjtNI0X0pzy+bGlAfmosepEfwfQhvJRJQhMzLyYnGqwbrXLf azKPZQbACKqpyruGDAFMJbYGvl5/DBFhqc5T3SZUNQfahLZ8b0+s8hX0wGWog2ESVP l5Vrc3YvLIue6Yc8+Hjm/9VRWRIEDZcN8+tSmg97gKsy3lXXt2223+DqeSCelrhRs0 mBv4yZoGTWtwXCBL4mk8YD37kdBDVVWIFV1fHyH1/lXTM0Ssy0+KaJq4Y26Z7cFFds ShvBgtTqDvApA== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQZ-2GDO; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Daniel Ferguson , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Dan Williams , Dave Jiang , Ira Weiny , Shuai Xue , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH 1/6] RAS: ACPI: APEI: add conditional compilation to ARM error report functions Date: Mon, 8 Jul 2024 13:18:10 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab From: Daniel Ferguson This prevents the unnecessary inclusion of ARM specific RAS error handling routines in non-ARM platforms. [mchehab: avoid unneeded ifdefs and fix coding style issues] Signed-off-by: Daniel Ferguson Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron --- drivers/acpi/apei/ghes.c | 13 ++++++------- drivers/ras/ras.c | 2 ++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 623cc0cb4a65..2589a3536d91 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -529,11 +529,12 @@ static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata, } static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, - int sev, bool sync) + int sev, bool sync) { + bool queued = false; +#if defined(CONFIG_ARM) || defined (CONFIG_ARM64) struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); int flags = sync ? MF_ACTION_REQUIRED : 0; - bool queued = false; int sec_sev, i; char *p; @@ -570,7 +571,7 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, error_type); p += err_info->length; } - +#endif return queued; } @@ -773,11 +774,9 @@ static bool ghes_do_proc(struct ghes *ghes, arch_apei_report_mem_error(sev, mem_err); queued = ghes_handle_memory_failure(gdata, sev, sync); - } - else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { + } else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { ghes_handle_aer(gdata); - } - else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { + } else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { queued = ghes_handle_arm_hw_error(gdata, sev, sync); } else if (guid_equal(sec_type, &CPER_SEC_CXL_GEN_MEDIA_GUID)) { struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata); diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index a6e4792a1b2e..5d94ab79c8c3 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -54,7 +54,9 @@ void log_non_standard_event(const guid_t *sec_type, const guid_t *fru_id, void log_arm_hw_error(struct cper_sec_proc_arm *err) { +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) trace_arm_event(err); +#endif } static int __init ras_init(void) From patchwork Mon Jul 8 11:18:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 812374 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D85F7E107; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=DDM+Co+5twKbZ+nB0U0cZtaOKJpVjmLkAEWlicbm25aQMR8YP7o8DoW2e8rM7wAiv8pbZwdGrESh4caEHvtrsZIUeoQbCKNXbsT37v6iqmHEufiw9MCelVsB/5GJr5O/8vbC47fsnMMA/F1kxjzwA+um5sybm7mJFSBFx7BZ0bI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=gQA/pDZl+o/citIm68eR2hril/7u79ybBuHKsJuPcVw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QJvMh39C027YiOnX33phnzrAi2telqz4TD7P8nFU0NYbMbylkvgo8p6W7xxlEhASq4NExtXYsPBpwETt2HjqnLV0ZLpvfVwvwBy7uYQuwIYX5+QszZ3HPBxu2ugRxRqmpx8Jj69qgqWIDLTOVqR/Z5WmLwKA823YWrY4L7OZW54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tgg2D+9i; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tgg2D+9i" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03F3DC4AF0C; Mon, 8 Jul 2024 11:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=gQA/pDZl+o/citIm68eR2hril/7u79ybBuHKsJuPcVw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tgg2D+9i7kSqyhLURWyMO5seZpWkrgd/DKdpH9rEA32ypvFJGfAffwqKe8ywpgSzL fYQnpZ+Qe7RVzwMixwElk9vcMwDFpvKTC3Uv6z5vPVG2MYUg25S/RTnPzP6D36m0st 2UC61DlJOkaiadEPxstgsjxCSpMxL3UNLg615Q4ysrhaDkT5EGaKSLxShsurjbw8Qa rAxi6KJQMBnUt4BBXiW38jllZz0tI0/xR8pWWIRgHyUnZaN61dsXFqUjaV9eDso4SX 1Sb5HbogIBdbEGZL7EDc8KQpARQ5jleN+ExNYxVJf3IRzl7PMJk/fCDIwNi1c4D/EF FQG5P0yreK2jA== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQc-2NnM; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Shengwei Luo , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Dan Williams , Dave Jiang , Ira Weiny , Shuai Xue , Steven Rostedt , Tyler Baicar , Will Deacon , Xie XiuQi , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, Jason Tian , Daniel Ferguson , Mauro Carvalho Chehab Subject: [PATCH 2/6] RAS: Report all ARM processor CPER information to userspace Date: Mon, 8 Jul 2024 13:18:11 +0200 Message-ID: <48ed5eb4448d85ccb5503335087a3e6a5159ca1e.1720436039.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab From: Shengwei Luo The ARM processor CPER record was added at UEFI 2.6, and hasn't any changes up to UEFI 2.10 on its struct. Yet, the original arm_event trace code added on changeset e9279e83ad1f ("trace, ras: add ARM processor error trace event") is incomplete, as it only traces some fields of UAPI 2.6 table N.16, not exporting at all any information from tables N.17 to N.29 of the record. This is not enough for user to take appropriate action or to log what exactly happened. According to UEFI_2_9 specification chapter N2.4.4, the ARM processor error section includes: - several (ERR_INFO_NUM) ARM processor error information structures (Tables N.17 to N.20); - several (CONTEXT_INFO_NUM) ARM processor context information structures (Tables N.21 to N.29); - several vendor specific error information structures. The size is given by Section Length minus the size of the other fields. In addition to those data, it also exports two fields that are parsed by the GHES driver when firmware reports it, e. g.: - error severity - cpu logical index Report all of these information to userspace via trace uAPI, So that userspace can properly record the error and take decisions related to cpu core isolation according to error severity and other info. After this patch, all the data from ARM Processor record from table N.16 are directly or indirectly visible on userspace: ====================================== ============================= UEFI field on table N.16 ARM Processor trace fields ====================================== ============================= Validation handled when filling data for affinity MPIDR and running state. ERR_INFO_NUM pei_len CONTEXT_INFO_NUM ctx_len Section Length indirectly reported by pei_len, ctx_len and oem_len Error affinity level affinity MPIDR_EL1 mpidr MIDR_EL1 midr Running State running_state PSCI State psci_state Processor Error Information Structure pei_err - count at pei_len Processor Context ctx_err- count at ctx_len Vendor Specific Error Info oem - count at oem_len ====================================== ============================= It should be noticed that decoding of tables N.17 to N.29, if needed, will be handled on userspace. That gives more flexibility, as there won't be any need to flood the Kernel with micro-architecture specific error decoding). Also, decoding the other fields require a complex logic, and should be done for each of the several values inside the record field. So, let userspace daemons like rasdaemon decode them, parsing such tables and having vendor-specific micro-architecture-specific decoders. [mchehab: modified patch description and fix coding style] Fixes: e9279e83ad1f ("trace, ras: add ARM processor error trace event") Signed-off-by: Shengwei Luo Signed-off-by: Jason Tian Signed-off-by: Daniel Ferguson Tested-by: Shiju Jose Signed-off-by: Mauro Carvalho Chehab Cc: "Rafael J. Wysocki" Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-section --- drivers/acpi/apei/ghes.c | 3 +-- drivers/ras/ras.c | 45 +++++++++++++++++++++++++++++++++++-- include/linux/ras.h | 16 ++++++++++---- include/ras/ras_event.h | 48 +++++++++++++++++++++++++++++++++++----- 4 files changed, 99 insertions(+), 13 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 2589a3536d91..90efca025d27 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -538,9 +538,8 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, int sec_sev, i; char *p; - log_arm_hw_error(err); - sec_sev = ghes_severity(gdata->error_severity); + log_arm_hw_error(err, sec_sev); if (sev != GHES_SEV_RECOVERABLE || sec_sev != GHES_SEV_RECOVERABLE) return false; diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index 5d94ab79c8c3..75acc09bc96a 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -52,10 +52,51 @@ void log_non_standard_event(const guid_t *sec_type, const guid_t *fru_id, trace_non_standard_event(sec_type, fru_id, fru_text, sev, err, len); } -void log_arm_hw_error(struct cper_sec_proc_arm *err) +void log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev) { #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) - trace_arm_event(err); + struct cper_arm_err_info *err_info; + struct cper_arm_ctx_info *ctx_info; + u8 *ven_err_data; + u32 ctx_len = 0; + int n, sz, cpu; + s32 vsei_len; + u32 pei_len; + u8 *pei_err; + u8 *ctx_err; + + pei_len = sizeof(struct cper_arm_err_info) * err->err_info_num; + pei_err = (u8 *)err + sizeof(struct cper_sec_proc_arm); + + err_info = (struct cper_arm_err_info *)(err + 1); + ctx_info = (struct cper_arm_ctx_info *)(err_info + err->err_info_num); + ctx_err = (u8 *)ctx_info; + for (n = 0; n < err->context_info_num; n++) { + sz = sizeof(struct cper_arm_ctx_info) + ctx_info->size; + ctx_info = (struct cper_arm_ctx_info *)((long)ctx_info + sz); + ctx_len += sz; + } + + vsei_len = err->section_length - (sizeof(struct cper_sec_proc_arm) + + pei_len + ctx_len); + if (vsei_len < 0) { + pr_warn(FW_BUG + "section length: %d\n", err->section_length); + pr_warn(FW_BUG + "section length is too small\n"); + pr_warn(FW_BUG + "firmware-generated error record is incorrect\n"); + vsei_len = 0; + } + ven_err_data = (u8 *)ctx_info; + + cpu = GET_LOGICAL_INDEX(err->mpidr); + /* when return value is invalid, set cpu index to -1 */ + if (cpu < 0) + cpu = -1; + + trace_arm_event(err, pei_err, pei_len, ctx_err, ctx_len, + ven_err_data, (u32)vsei_len, sev, cpu); #endif } diff --git a/include/linux/ras.h b/include/linux/ras.h index a64182bc72ad..6025afe5736a 100644 --- a/include/linux/ras.h +++ b/include/linux/ras.h @@ -24,8 +24,7 @@ int __init parse_cec_param(char *str); void log_non_standard_event(const guid_t *sec_type, const guid_t *fru_id, const char *fru_text, const u8 sev, const u8 *err, const u32 len); -void log_arm_hw_error(struct cper_sec_proc_arm *err); - +void log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev); #else static inline void log_non_standard_event(const guid_t *sec_type, @@ -33,7 +32,7 @@ log_non_standard_event(const guid_t *sec_type, const u8 sev, const u8 *err, const u32 len) { return; } static inline void -log_arm_hw_error(struct cper_sec_proc_arm *err) { return; } +log_arm_hw_error(struct cper_sec_proc_arm *err, const u8 sev) { return; } #endif struct atl_err { @@ -52,5 +51,14 @@ static inline void amd_retire_dram_row(struct atl_err *err) { } static inline unsigned long amd_convert_umc_mca_addr_to_sys_addr(struct atl_err *err) { return -EINVAL; } #endif /* CONFIG_AMD_ATL */ - +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) +#include +/* + * Include ARM specific SMP header which provides a function mapping mpidr to + * cpu logical index. + */ +#define GET_LOGICAL_INDEX(mpidr) get_logical_index(mpidr & MPIDR_HWID_BITMASK) +#else +#define GET_LOGICAL_INDEX(mpidr) -EINVAL +#endif /* CONFIG_ARM || CONFIG_ARM64 */ #endif /* __RAS_H__ */ diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index 7c47151d5c72..ce5214f008eb 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -168,11 +168,24 @@ TRACE_EVENT(mc_event, * This event is generated when hardware detects an ARM processor error * has occurred. UEFI 2.6 spec section N.2.4.4. */ +#define APEIL "ARM Processor Err Info data len" +#define APEID "ARM Processor Err Info raw data" +#define APECIL "ARM Processor Err Context Info data len" +#define APECID "ARM Processor Err Context Info raw data" +#define VSEIL "Vendor Specific Err Info data len" +#define VSEID "Vendor Specific Err Info raw data" TRACE_EVENT(arm_event, - TP_PROTO(const struct cper_sec_proc_arm *proc), + TP_PROTO(const struct cper_sec_proc_arm *proc, const u8 *pei_err, + const u32 pei_len, + const u8 *ctx_err, + const u32 ctx_len, + const u8 *oem, + const u32 oem_len, + u8 sev, + int cpu), - TP_ARGS(proc), + TP_ARGS(proc, pei_err, pei_len, ctx_err, ctx_len, oem, oem_len, sev, cpu), TP_STRUCT__entry( __field(u64, mpidr) @@ -180,6 +193,14 @@ TRACE_EVENT(arm_event, __field(u32, running_state) __field(u32, psci_state) __field(u8, affinity) + __field(u32, pei_len) + __dynamic_array(u8, buf, pei_len) + __field(u32, ctx_len) + __dynamic_array(u8, buf1, ctx_len) + __field(u32, oem_len) + __dynamic_array(u8, buf2, oem_len) + __field(u8, sev) + __field(int, cpu) ), TP_fast_assign( @@ -199,12 +220,29 @@ TRACE_EVENT(arm_event, __entry->running_state = ~0; __entry->psci_state = ~0; } + __entry->pei_len = pei_len; + memcpy(__get_dynamic_array(buf), pei_err, pei_len); + __entry->ctx_len = ctx_len; + memcpy(__get_dynamic_array(buf1), ctx_err, ctx_len); + __entry->oem_len = oem_len; + memcpy(__get_dynamic_array(buf2), oem, oem_len); + __entry->sev = sev; + __entry->cpu = cpu; ), - TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; " - "running state: %d; PSCI state: %d", + TP_printk("cpu: %d; error: %d; affinity level: %d; MPIDR: %016llx; MIDR: %016llx; " + "running state: %d; PSCI state: %d; " + "%s: %d; %s: %s; %s: %d; %s: %s; %s: %d; %s: %s", + __entry->cpu, + __entry->sev, __entry->affinity, __entry->mpidr, __entry->midr, - __entry->running_state, __entry->psci_state) + __entry->running_state, __entry->psci_state, + APEIL, __entry->pei_len, APEID, + __print_hex(__get_dynamic_array(buf), __entry->pei_len), + APECIL, __entry->ctx_len, APECID, + __print_hex(__get_dynamic_array(buf1), __entry->ctx_len), + VSEIL, __entry->oem_len, VSEID, + __print_hex(__get_dynamic_array(buf2), __entry->oem_len)) ); /* From patchwork Mon Jul 8 11:18:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 811265 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DB8F7D071; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=e016QIZA/AeCOhB4K8l+7ZytiOppgatTcaLcdW48cGPDxZpoIFkTcfwkLFTjzxR/t1PTcvmJQyV27KEYR5Payi/as5pyaMuPV027S9QXfheGVlYHF56Pw2Qvn+nlqFn45uf7FJl9uTOvBIoh7neh+jCwhMs4ASh6SWWUJQaliqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=LayJjNlHt7RdDKs2eSpJizuqfyzjoPSkSmmLznNH6CU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RKaFZb7nPaCJ2bK0us17fIg1MPn/jMhVkTTS4/JiP8eQlof9s7IrlAQPRz3RULfq+NRU3aSrsTwEK2By7h9j5/YN4pgsG4MijxxSB78jY7qAZnEwsuowsip1z/VgNec6jEcPd6eWFSF57jkpPNrkH3OwnaRZDm0Jz2+mo5OItSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b7WLQ8y3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b7WLQ8y3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C582C4AF0D; Mon, 8 Jul 2024 11:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=LayJjNlHt7RdDKs2eSpJizuqfyzjoPSkSmmLznNH6CU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b7WLQ8y3V6z35YgPXrUddX2093d7ag6CcVlwWEHIs93bLNTIMgKtd9532Co8hkIMf tFEIfalAYtwVOSydYXrinjxrIIM3jecLhvqVseWPYVXpCvQcJe1UkBb1WGRtSFNM3a gKXoBHKoBmiON4k+MVvnvUlEfydjlpdAKqOBwVxQVj0XnsOymexP3/cdSkHapNW51i PG15i0P8XQxQtpVjXE1sz4vMvUb1f8i5A//Qwlezy9Y55Ka6J9qiw8Uq7OnQ0EfOTr MQiJnGxKHTKptsT1ecl6Ad9/+vhIIbV3rh6hShZtGmzCHo5GZCIjSvssjEXAc86hlQ zV0cmHSkatvyQ== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQf-2UoA; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Mauro Carvalho Chehab , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] efi/cper: Adjust infopfx size to accept an extra space Date: Mon, 8 Jul 2024 13:18:12 +0200 Message-ID: <020925baf424b46adc350c14584f4ef609613c5d.1720436039.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Compiling with W=1 with werror enabled produces an error: drivers/firmware/efi/cper-arm.c: In function ‘cper_print_proc_arm’: drivers/firmware/efi/cper-arm.c:298:64: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] 298 | snprintf(infopfx, sizeof(infopfx), "%s ", newpfx); | ^ drivers/firmware/efi/cper-arm.c:298:25: note: ‘snprintf’ output between 2 and 65 bytes into a destination of size 64 298 | snprintf(infopfx, sizeof(infopfx), "%s ", newpfx); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ As the logic there adds an space at the end of infopx buffer. Add an extra space to avoid such warning. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron --- drivers/firmware/efi/cper-arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/efi/cper-arm.c b/drivers/firmware/efi/cper-arm.c index fa9c1c3bf168..eb7ee6af55f2 100644 --- a/drivers/firmware/efi/cper-arm.c +++ b/drivers/firmware/efi/cper-arm.c @@ -240,7 +240,7 @@ void cper_print_proc_arm(const char *pfx, int i, len, max_ctx_type; struct cper_arm_err_info *err_info; struct cper_arm_ctx_info *ctx_info; - char newpfx[64], infopfx[64]; + char newpfx[64], infopfx[ARRAY_SIZE(newpfx) + 1]; printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); From patchwork Mon Jul 8 11:18:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 812377 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D24D39FD7; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=pRWq2imM3r/Ms0ynZJSAoctMt84TlOGt5jz8pTvQP8wowAtfH1ZlXOKnTRAaHKAMn7hRqgS8Gf7ZO7aPvnNkfTthfIldn0/+YnA+LIBVipHsV377qoICHHIBoyvi2Wu7PnBNAbK7mSkcZAl7G4I1k0Qt2rQvmfxfii6iq4NQ428= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=jPOSGw8h3LTxme7xAjF29NTRuS0fIgaE9Bx1xOw0o50=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fL6U7JJLX+FiSbuJKZJKhw74+F3gTHndVN0RZmJt67Hs84JoGT+QijNWpXo+D6DUTo9SUwpbJFuMAPju0H/Ia68ne8wPZztDgwo1UBZx78ouPsY1oP7ymOpGB0VgMqbsYPnrFeO/8G2NhGjgFntrguXc1g42esinAzw+/AD8eFw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=maSieSA3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="maSieSA3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0198FC4AF0A; Mon, 8 Jul 2024 11:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=jPOSGw8h3LTxme7xAjF29NTRuS0fIgaE9Bx1xOw0o50=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=maSieSA3JmSQKEQVd7NmXYm1z4re/L6AIb6EHSiN4eX+qAitt8hy9+nXm8Bcf7j14 CakCb7I8I6AAFmIYk/Ycj26X/VRL3fV+qiiTf8ubDflqrnqCeH6U3ZZ1UodHie5msR IexZlvcwsr8bOdGQPDNqNiQP2YQaSxLMYNqKWeVH8lBnn+kHkZFEQ/nPu2r+1QZvMC merwvShAHvMZhGqjnBREw2V+sTg6A0XClU47gJpfb4VCtMcfLu3UlAGWABQuOkT1Xe 4/C/lIgHPmLPz4FXF257dTTHueBafdXcBAqSrXaM9L4Ju6tcrKqnjqpC2rtqj/zUdM AiidmZoznoy7g== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQl-2bki; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Mauro Carvalho Chehab , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , Alison Schofield , Ira Weiny , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] efi/cper: Add a new helper function to print bitmasks Date: Mon, 8 Jul 2024 13:18:13 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Sometimes it is desired to produce a single log line for errors. Add a new helper function for such purpose. Signed-off-by: Mauro Carvalho Chehab --- drivers/firmware/efi/cper.c | 43 +++++++++++++++++++++++++++++++++++++ include/linux/cper.h | 2 ++ 2 files changed, 45 insertions(+) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index 7d2cdd9e2227..f8c8a15cd527 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -106,6 +106,49 @@ void cper_print_bits(const char *pfx, unsigned int bits, printk("%s\n", buf); } +/* + * cper_bits_to_str - return a string for set bits + * @buf: buffer to store the output string + * @buf_size: size of the output string buffer + * @bits: bit mask + * @strs: string array, indexed by bit position + * @strs_size: size of the string array: @strs + * @mask: a continuous bitmask used to detect the first valid bit of the + * bitmap. + * + * Add to @buf the bitmask in hexadecimal. Then, for each set bit in @bits + * mask, add the corresponding string describing the bit in @strs to @buf. + */ +char *cper_bits_to_str(char *buf, int buf_size, unsigned long bits, + const char * const strs[], unsigned int strs_size) +{ + int len = buf_size; + char *str = buf; + int i, size; + + *buf = '\0'; + + for_each_set_bit(i, &bits, strs_size) { + if (!(bits & (1U << (i)))) + continue; + + if (*buf && len > 0) { + *str = '|'; + len--; + str++; + } + + size = strscpy(str, strs[i], len); + if (size < 0) + break; + + len -= size; + str += size; + } + return buf; +} +EXPORT_SYMBOL_GPL(cper_bits_to_str); + static const char * const proc_type_strs[] = { "IA32/X64", "IA64", diff --git a/include/linux/cper.h b/include/linux/cper.h index 265b0f8fc0b3..c2f14b916bfb 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -584,6 +584,8 @@ const char *cper_mem_err_type_str(unsigned int); const char *cper_mem_err_status_str(u64 status); void cper_print_bits(const char *prefix, unsigned int bits, const char * const strs[], unsigned int strs_size); +char *cper_bits_to_str(char *buf, int buf_size, unsigned long bits, + const char * const strs[], unsigned int strs_size); void cper_mem_err_pack(const struct cper_sec_mem_err *, struct cper_mem_err_compact *); const char *cper_mem_err_unpack(struct trace_seq *, From patchwork Mon Jul 8 11:18:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 812375 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6874F7D06E; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=MZK9dZOMndPsMtkarJnBpOR9hJaamz/Wsus/ip74QfbrxREwORYpGdTsMJUHbcNdvoesWz0IGW2mLGjYCm8rgvma/Kbx67iMMGSv447xnuAhT1ztRpP9pds/e1ZTbtkmB9q83mKrLL14pQaBhzcijOWpfzoOCsEHsW5UExFQLWg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=6zeKktLBxvGVhQx+TZOJafFPKQrmsZYPJP+g/sKx30k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=amzGOxVdOvDZLuE5I1vRWFe/IfLHq4Re0C+lbANVMSkbNrrDJLeEXxgm5HSWHvM3fsgweJUN1wRoC7jyXomi4U5HoL4cCybBAU3PZPWyDJNT/36nFMs75mkrfgzqgzFPS3sfGOU0Lk572WtOZSTyGH3Az66SRw/XLDAXxuqffns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qqocIwNf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qqocIwNf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0EB01C4AF10; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=6zeKktLBxvGVhQx+TZOJafFPKQrmsZYPJP+g/sKx30k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qqocIwNfR/jgQhwDXse5JckjIub1RpNN2L/UiAHX+ATt1a/kbgcpd4A2bhtAYOMwx YI72b5bTHLQshswE3CgJRB/W3NlY9WPfHYLqhtODYcGuZPljAQtr/vuLuMemE6fApw cwjNXriGHt2oV2VED58VMaha6XVcqnlmsDwpZeKFCmSb1BGIxoZDMpVO5K4vhIPa3m WQblPD4EjFBmVMv3cojTmzwMiQl6ioeuaCGEUBjp9FJ7Mf6NwdFcOADgY2woFEopZm Fm45kDl/UwwJ+OsSsYG6QSBi/zszw47Qp1gXkUCkr4Ng/usYlblNm0V05lCN6YBEFD 85I5vqArT0qow== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQp-2jes; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Mauro Carvalho Chehab , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Alison Schofield , Dan Williams , Dave Jiang , Ira Weiny , Shuai Xue , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] efi/cper: align ARM CPER type with UEFI 2.9A/2.10 specs Date: Mon, 8 Jul 2024 13:18:14 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Up to UEFI spec, the type byte of CPER struct for ARM processor was defined simply as: Type at byte offset 4: - Cache error - TLB Error - Bus Error - Micro-architectural Error All other values are reserved Yet, there was no information about how this would be encoded. Spec 2.9A errata corrected it by defining: - Bit 1 - Cache Error - Bit 2 - TLB Error - Bit 3 - Bus Error - Bit 4 - Micro-architectural Error All other values are reserved That actually aligns with the values already defined on older versions at N.2.4.1. Generic Processor Error Section. Spec 2.10 also preserve the same encoding as 2.9A Adjust CPER and GHES handling code for both generic and ARM processors to properly handle UEFI 2.9A and 2.10 encoding. Link: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-information Signed-off-by: Mauro Carvalho Chehab --- drivers/acpi/apei/ghes.c | 15 ++++++---- drivers/firmware/efi/cper-arm.c | 50 ++++++++++++++++----------------- include/linux/cper.h | 10 +++---- 3 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 90efca025d27..e796140d93f0 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -535,6 +535,7 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, #if defined(CONFIG_ARM) || defined (CONFIG_ARM64) struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); int flags = sync ? MF_ACTION_REQUIRED : 0; + char error_type[120]; int sec_sev, i; char *p; @@ -546,9 +547,8 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, p = (char *)(err + 1); for (i = 0; i < err->err_info_num; i++) { struct cper_arm_err_info *err_info = (struct cper_arm_err_info *)p; - bool is_cache = (err_info->type == CPER_ARM_CACHE_ERROR); + bool is_cache = err_info->type & CPER_ARM_CACHE_ERROR; bool has_pa = (err_info->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR); - const char *error_type = "unknown error"; /* * The field (err_info->error_info & BIT(26)) is fixed to set to @@ -562,12 +562,15 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, continue; } - if (err_info->type < ARRAY_SIZE(cper_proc_error_type_strs)) - error_type = cper_proc_error_type_strs[err_info->type]; + cper_bits_to_str(error_type, sizeof(error_type), + FIELD_GET(CPER_ARM_ERR_TYPE_MASK, err_info->type), + cper_proc_error_type_strs, + ARRAY_SIZE(cper_proc_error_type_strs)); pr_warn_ratelimited(FW_WARN GHES_PFX - "Unhandled processor error type: %s\n", - error_type); + "Unhandled processor error type 0x%02x: %s%s\n", + err_info->type, error_type, + (err_info->type & ~CPER_ARM_ERR_TYPE_MASK) ? " with reserved bit(s)" : ""); p += err_info->length; } #endif diff --git a/drivers/firmware/efi/cper-arm.c b/drivers/firmware/efi/cper-arm.c index eb7ee6af55f2..52d18490b59e 100644 --- a/drivers/firmware/efi/cper-arm.c +++ b/drivers/firmware/efi/cper-arm.c @@ -93,15 +93,11 @@ static void cper_print_arm_err_info(const char *pfx, u32 type, bool proc_context_corrupt, corrected, precise_pc, restartable_pc; bool time_out, access_mode; - /* If the type is unknown, bail. */ - if (type > CPER_ARM_MAX_TYPE) - return; - /* * Vendor type errors have error information values that are vendor * specific. */ - if (type == CPER_ARM_VENDOR_ERROR) + if (type & CPER_ARM_VENDOR_ERROR) return; if (error_info & CPER_ARM_ERR_VALID_TRANSACTION_TYPE) { @@ -116,43 +112,38 @@ static void cper_print_arm_err_info(const char *pfx, u32 type, if (error_info & CPER_ARM_ERR_VALID_OPERATION_TYPE) { op_type = ((error_info >> CPER_ARM_ERR_OPERATION_SHIFT) & CPER_ARM_ERR_OPERATION_MASK); - switch (type) { - case CPER_ARM_CACHE_ERROR: + if (type & CPER_ARM_CACHE_ERROR) { if (op_type < ARRAY_SIZE(arm_cache_err_op_strs)) { - printk("%soperation type: %s\n", pfx, + printk("%scache error, operation type: %s\n", pfx, arm_cache_err_op_strs[op_type]); } - break; - case CPER_ARM_TLB_ERROR: + } + if (type & CPER_ARM_TLB_ERROR) { if (op_type < ARRAY_SIZE(arm_tlb_err_op_strs)) { - printk("%soperation type: %s\n", pfx, + printk("%sTLB error, operation type: %s\n", pfx, arm_tlb_err_op_strs[op_type]); } - break; - case CPER_ARM_BUS_ERROR: + } + if (type & CPER_ARM_BUS_ERROR) { if (op_type < ARRAY_SIZE(arm_bus_err_op_strs)) { - printk("%soperation type: %s\n", pfx, + printk("%sbus error, operation type: %s\n", pfx, arm_bus_err_op_strs[op_type]); } - break; } } if (error_info & CPER_ARM_ERR_VALID_LEVEL) { level = ((error_info >> CPER_ARM_ERR_LEVEL_SHIFT) & CPER_ARM_ERR_LEVEL_MASK); - switch (type) { - case CPER_ARM_CACHE_ERROR: + if (type & CPER_ARM_CACHE_ERROR) printk("%scache level: %d\n", pfx, level); - break; - case CPER_ARM_TLB_ERROR: + + if (type & CPER_ARM_TLB_ERROR) printk("%sTLB level: %d\n", pfx, level); - break; - case CPER_ARM_BUS_ERROR: + + if (type & CPER_ARM_BUS_ERROR) printk("%saffinity level at which the bus error occurred: %d\n", pfx, level); - break; - } } if (error_info & CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT) { @@ -241,6 +232,7 @@ void cper_print_proc_arm(const char *pfx, struct cper_arm_err_info *err_info; struct cper_arm_ctx_info *ctx_info; char newpfx[64], infopfx[ARRAY_SIZE(newpfx) + 1]; + char error_type[120]; printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); @@ -289,9 +281,15 @@ void cper_print_proc_arm(const char *pfx, newpfx); } - printk("%serror_type: %d, %s\n", newpfx, err_info->type, - err_info->type < ARRAY_SIZE(cper_proc_error_type_strs) ? - cper_proc_error_type_strs[err_info->type] : "unknown"); + cper_bits_to_str(error_type, sizeof(error_type), + FIELD_GET(CPER_ARM_ERR_TYPE_MASK, err_info->type), + cper_proc_error_type_strs, + ARRAY_SIZE(cper_proc_error_type_strs)); + + printk("%serror_type: 0x%02x: %s%s\n", newpfx, err_info->type, + error_type, + (err_info->type & ~CPER_ARM_ERR_TYPE_MASK) ? " with reserved bit(s)" : ""); + if (err_info->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) { printk("%serror_info: 0x%016llx\n", newpfx, err_info->error_info); diff --git a/include/linux/cper.h b/include/linux/cper.h index c2f14b916bfb..fc62a80575e8 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -293,11 +293,11 @@ enum { #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) -#define CPER_ARM_CACHE_ERROR 0 -#define CPER_ARM_TLB_ERROR 1 -#define CPER_ARM_BUS_ERROR 2 -#define CPER_ARM_VENDOR_ERROR 3 -#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR +#define CPER_ARM_ERR_TYPE_MASK GENMASK(4,1) +#define CPER_ARM_CACHE_ERROR BIT(1) +#define CPER_ARM_TLB_ERROR BIT(2) +#define CPER_ARM_BUS_ERROR BIT(3) +#define CPER_ARM_VENDOR_ERROR BIT(4) #define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0) #define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1) From patchwork Mon Jul 8 11:18:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 812376 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B4AB7A715; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=pzC8QDLw84t4FWXd7X3uXgV5waCuhNTjTVQEwjPk3wcumJfSPGqkI7vAqh2HN8Ma8EcIcMjYZ+oj33Sg05QGuTdYT1X3P/5lQtzWV7YHXwmN6Nl7hDerq1BgAp6mr09EQxLqt72iQrSIs3+fap4ksThAZBtD6c0pgpgBPRoNZLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=SghajJ93+iIxp1CCEYJcx9SzDpum+6rkVLD7R4JlgPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rr3/KYAVGZWYNgpYzKAUvVi75aruJbARKqygcZm91EGufEFTXjhc1Kskum1Z9JAkUrjrR0y2q+t1F7KuLG1Lu5hICqljPx76pkP4gHCbt/N5WMY3vsLrqn/o/tp58CQ08jvFLffAoW4hBqaRAH99I+2EsJk38I6m54uVjiENmi4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fhs5TBEz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fhs5TBEz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2508C116B1; Mon, 8 Jul 2024 11:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=SghajJ93+iIxp1CCEYJcx9SzDpum+6rkVLD7R4JlgPU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fhs5TBEz2JYV0lD8FKDqRKZhZmtCaLbzHlQgRf34jJzjM1eNk2yFwAnNv0AQkG6g0 YazbqT+fHQ+ZjkWucYkTCnLkcz22a3IjoFCXFsQ98Poe6LoNqRUkZqGwYsYQIAYCbG tvY9LoyMsXSr1LY5iR+oHOZp1LhAeZbJu+eO2Jny6paEqmm2fKM3xmPH8ljTEWqdFh f15paEdtYMe4ZCLuAmtSqu12nNJx1lXsUK1t5p2j30pueGUGLHxhTlWjoO6LGH6fkW kpSnP2j+Vgg8cN6b/Z4yyw9MVMNOSaQV6XUuquKKq09DFvFqYBF1zXgx8JEq/SCUeR Poq8jQE/qM6xQ== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQt-2qde; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Mauro Carvalho Chehab , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , Jonathan Corbet , linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] docs: efi: add CPER functions to driver-api Date: Mon, 8 Jul 2024 13:18:15 +0200 Message-ID: <2d0e11752d2bde41b61822b04b5b6f839d46b998.1720436039.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab There are two kernel-doc like descriptions at cper, which is used by other parts of cper and on ghes driver. They both have kernel-doc like descriptions. Change the tags for them to be actual kernel-doc tags and add them to the driver-api documentaion at the UEFI section. Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/firmware/efi/index.rst | 11 ++++++++--- drivers/firmware/efi/cper.c | 10 ++++------ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/Documentation/driver-api/firmware/efi/index.rst b/Documentation/driver-api/firmware/efi/index.rst index 4fe8abba9fc6..5a6b6229592c 100644 --- a/Documentation/driver-api/firmware/efi/index.rst +++ b/Documentation/driver-api/firmware/efi/index.rst @@ -1,11 +1,16 @@ .. SPDX-License-Identifier: GPL-2.0 -============ -UEFI Support -============ +==================================================== +Unified Extensible Firmware Interface (UEFI) Support +==================================================== UEFI stub library functions =========================== .. kernel-doc:: drivers/firmware/efi/libstub/mem.c :internal: + +UEFI Common Platform Error Record (CPER) functions +================================================== + +.. kernel-doc:: drivers/firmware/efi/cper.c diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index f8c8a15cd527..2785c8ea8ad8 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -69,7 +69,7 @@ const char *cper_severity_str(unsigned int severity) } EXPORT_SYMBOL_GPL(cper_severity_str); -/* +/** * cper_print_bits - print strings for set bits * @pfx: prefix for each line, including log level and prefix string * @bits: bit mask @@ -106,18 +106,16 @@ void cper_print_bits(const char *pfx, unsigned int bits, printk("%s\n", buf); } -/* +/** * cper_bits_to_str - return a string for set bits * @buf: buffer to store the output string * @buf_size: size of the output string buffer * @bits: bit mask * @strs: string array, indexed by bit position * @strs_size: size of the string array: @strs - * @mask: a continuous bitmask used to detect the first valid bit of the - * bitmap. * - * Add to @buf the bitmask in hexadecimal. Then, for each set bit in @bits - * mask, add the corresponding string describing the bit in @strs to @buf. + * Add to @buf the bitmask in hexadecimal. Then, for each set bit in @bits, + * add the corresponding string describing the bit in @strs to @buf. */ char *cper_bits_to_str(char *buf, int buf_size, unsigned long bits, const char * const strs[], unsigned int strs_size)