From patchwork Fri Jul 5 09:00:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 810831 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2B4F147C98; Fri, 5 Jul 2024 09:01:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720170091; cv=none; b=d57mhoXJ1QFshQFdb/Y9g9jDdrL1x+C3resxJmZaW7GeU6IgctbtWZ8BLZgqbmrmVc0bDcQiFjvQCNTaSm9PHXaLbk9TQiqEp3bN/zCLIYS+U6P3LB7usVY7j8yHJBlZgDcHDggx9wymUxebGvcVWuU/jkuz/DIE53OK5TiOOII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720170091; c=relaxed/simple; bh=dpvJsotTlf2F20+vfVrd9BHYvcDbLIvbg+Ptj/TKSMU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O3B8baEjSl+W2JRjgDYM5/JBns2IeXDOVrh7is4y4HySTTfLeUHrqsdMky/D8BDHsXOBlvsmUoeL4yBycYyH1Bi8CAA7oxN3fCsUgdDN3gTvR/oEbcVKQScB+GMfuvgAll57isWEN9M8OJJDMqAOYrs91iyfYy6rMI5R7805CyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GuyC0ydx; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GuyC0ydx" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4657wqXS019699; Fri, 5 Jul 2024 09:01:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= k4gPMBPyOu/SDiEN+2zLfapTfSYnZYBZm0EALm3x4FY=; b=GuyC0ydxt4i+wcmd IcNYIL5UrbhF4Ols1s439T+zh5CcGq+4vs1WW5MngqfRz2tnjBONXFCqn3XCRLiC IfEptWbOL9O30OV4MN8ben8EuukEmq1nFynwGWbwmBnccCYbOr0Cvt8RtY+9LsnT x2CWWTUZr8IT9YdmoInx2S2TkeCZ2/bAFZceNR/S21impPDiclJQ5uWi+xypq0d+ WmAKkU1H54HWfdyUlFqf8UCal8RrqGkeA7Oqq9PLdO6sG3/X8PByLYzZ9+sDndr3 2Nnjn8AmEgLKHxE96Z+XEVYKu97mTX/Aj6BVCQp0f9KVbh8vxSI/c9oZl60VMUCm J9fMsQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 406cww85nv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 Jul 2024 09:01:17 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46591FHe030477 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 5 Jul 2024 09:01:15 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 5 Jul 2024 02:01:10 -0700 From: Jie Gan To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Mike Leach , "Rob Herring" , Krzysztof Kozlowski , James Clark CC: Jinlong Mao , Leo Yan , , , , , Tingwei Zhang , Yuanfang Zhang , "Tao Zhang" , Trilok Soni , "Song Chai" , Subject: [PATCH v2 1/4] Coresight: Add trace_id function to collect trace ID Date: Fri, 5 Jul 2024 17:00:46 +0800 Message-ID: <20240705090049.1656986-2-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240705090049.1656986-1-quic_jiegan@quicinc.com> References: <20240705090049.1656986-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Jm5fZexhbs2XaKMCgtjxON1TJ7mYFhNM X-Proofpoint-GUID: Jm5fZexhbs2XaKMCgtjxON1TJ7mYFhNM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-05_05,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 mlxlogscore=861 lowpriorityscore=0 mlxscore=0 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407050067 Add 'trace_id' function pointer in ops. It's responsible for collect the trace ID of the device. Add 'struct cs_sink_data' to store the data used by coresight_enable_path/ coresight_disable_path. The structure will be transmitted to the helper and sink device. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 53 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etb10.c | 3 +- .../hwtracing/coresight/coresight-etm-perf.c | 34 ++++++++++-- .../coresight/coresight-etm3x-core.c | 14 +++++ .../coresight/coresight-etm4x-core.c | 13 +++++ drivers/hwtracing/coresight/coresight-priv.h | 12 ++++- drivers/hwtracing/coresight/coresight-stm.c | 13 +++++ drivers/hwtracing/coresight/coresight-sysfs.c | 24 +++++++-- .../hwtracing/coresight/coresight-tmc-etf.c | 3 +- .../hwtracing/coresight/coresight-tmc-etr.c | 6 ++- drivers/hwtracing/coresight/coresight-tpda.c | 13 +++++ drivers/hwtracing/coresight/coresight-trbe.c | 4 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 3 +- include/linux/coresight.h | 4 ++ 14 files changed, 174 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 9fc6f6b863e0..f414e66f4cda 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -297,12 +297,12 @@ static int coresight_enable_helper(struct coresight_device *csdev, return helper_ops(csdev)->enable(csdev, mode, data); } -static void coresight_disable_helper(struct coresight_device *csdev) +static void coresight_disable_helper(struct coresight_device *csdev, void *data) { - helper_ops(csdev)->disable(csdev, NULL); + helper_ops(csdev)->disable(csdev, data); } -static void coresight_disable_helpers(struct coresight_device *csdev) +static void coresight_disable_helpers(struct coresight_device *csdev, void *data) { int i; struct coresight_device *helper; @@ -310,7 +310,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) for (i = 0; i < csdev->pdata->nr_outconns; ++i) { helper = csdev->pdata->out_conns[i]->dest_dev; if (helper && coresight_is_helper(helper)) - coresight_disable_helper(helper); + coresight_disable_helper(helper, data); } } @@ -327,7 +327,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) void coresight_disable_source(struct coresight_device *csdev, void *data) { source_ops(csdev)->disable(csdev, data); - coresight_disable_helpers(csdev); + coresight_disable_helpers(csdev, NULL); } EXPORT_SYMBOL_GPL(coresight_disable_source); @@ -337,7 +337,8 @@ EXPORT_SYMBOL_GPL(coresight_disable_source); * disabled. */ static void coresight_disable_path_from(struct list_head *path, - struct coresight_node *nd) + struct coresight_node *nd, + void *sink_data) { u32 type; struct coresight_device *csdev, *parent, *child; @@ -382,13 +383,13 @@ static void coresight_disable_path_from(struct list_head *path, } /* Disable all helpers adjacent along the path last */ - coresight_disable_helpers(csdev); + coresight_disable_helpers(csdev, sink_data); } } -void coresight_disable_path(struct list_head *path) +void coresight_disable_path(struct list_head *path, void *sink_data) { - coresight_disable_path_from(path, NULL); + coresight_disable_path_from(path, NULL, sink_data); } EXPORT_SYMBOL_GPL(coresight_disable_path); @@ -468,10 +469,42 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, out: return ret; err: - coresight_disable_path_from(path, nd); + coresight_disable_path_from(path, nd, sink_data); goto out; } +int coresight_read_traceid(struct list_head *path) +{ + int trace_id, type; + struct coresight_device *csdev; + struct coresight_node *nd; + + list_for_each_entry(nd, path, link) { + csdev = nd->csdev; + type = csdev->type; + + switch(type) { + case CORESIGHT_DEV_TYPE_SOURCE: + if (source_ops(csdev)->trace_id != NULL) { + trace_id = source_ops(csdev)->trace_id(csdev); + if (trace_id > 0) + return trace_id; + } + break; + case CORESIGHT_DEV_TYPE_LINK: + if (link_ops(csdev)->trace_id != NULL) { + trace_id = link_ops(csdev)->trace_id(csdev); + if (trace_id > 0) + return trace_id; + } + break; + default: + break; + } + } + return -EINVAL; +} + struct coresight_device *coresight_get_sink(struct list_head *path) { struct coresight_device *csdev; diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 7edd3f1d0d46..05e620529c14 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -173,7 +173,8 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data) pid_t pid; unsigned long flags; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index c0c60e6a1703..8b155765b959 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -452,6 +452,7 @@ static void etm_event_start(struct perf_event *event, int flags) struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); struct list_head *path; + struct cs_sink_data *sink_data = NULL; u64 hw_id; if (!csdev) @@ -490,9 +491,18 @@ static void etm_event_start(struct perf_event *event, int flags) if (WARN_ON_ONCE(!sink)) goto fail_end_stop; + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) + goto fail_end_stop; + + sink_data->sink = sink; + sink_data->traceid = coresight_read_traceid(path); + sink_data->handle = handle; /* Nothing will happen without a path */ - if (coresight_enable_path(path, CS_MODE_PERF, handle)) + if (coresight_enable_path(path, CS_MODE_PERF, sink_data)) { + kfree(sink_data); goto fail_end_stop; + } /* Finally enable the tracer */ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) @@ -511,6 +521,7 @@ static void etm_event_start(struct perf_event *event, int flags) perf_report_aux_output_id(event, hw_id); } + kfree(sink_data); out: /* Tell the perf core the event is alive */ event->hw.state = 0; @@ -519,7 +530,8 @@ static void etm_event_start(struct perf_event *event, int flags) return; fail_disable_path: - coresight_disable_path(path); + coresight_disable_path(path, sink_data); + kfree(sink_data); fail_end_stop: /* * Check if the handle is still associated with the event, @@ -544,6 +556,7 @@ static void etm_event_stop(struct perf_event *event, int mode) struct perf_output_handle *handle = &ctxt->handle; struct etm_event_data *event_data; struct list_head *path; + struct cs_sink_data *sink_data = NULL; /* * If we still have access to the event_data via handle, @@ -588,6 +601,10 @@ static void etm_event_stop(struct perf_event *event, int mode) if (!sink) return; + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) + return; + /* stop tracer */ coresight_disable_source(csdev, event); @@ -601,12 +618,16 @@ static void etm_event_stop(struct perf_event *event, int mode) * have to do anything here. */ if (handle->event && (mode & PERF_EF_UPDATE)) { - if (WARN_ON_ONCE(handle->event != event)) + if (WARN_ON_ONCE(handle->event != event)) { + kfree(sink_data); return; + } /* update trace information */ - if (!sink_ops(sink)->update_buffer) + if (!sink_ops(sink)->update_buffer) { + kfree(sink_data); return; + } size = sink_ops(sink)->update_buffer(sink, handle, event_data->snk_config); @@ -627,8 +648,11 @@ static void etm_event_stop(struct perf_event *event, int mode) WARN_ON(size); } + sink_data->sink = sink; + sink_data->traceid = coresight_read_traceid(path); /* Disabling the path make its elements available to other sessions */ - coresight_disable_path(path); + coresight_disable_path(path, sink_data); + kfree(sink_data); } static int etm_event_add(struct perf_event *event, int mode) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 8b362605d242..27e973749050 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -696,10 +696,24 @@ static void etm_disable(struct coresight_device *csdev, coresight_set_mode(csdev, CS_MODE_DISABLED); } +static int etm_trace_id(struct coresight_device *csdev) +{ + struct etm_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return etm_read_alloc_trace_id(drvdata); +} + + static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, .enable = etm_enable, .disable = etm_disable, + .trace_id = etm_trace_id, }; static const struct coresight_ops etm_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bf01f01964cf..8c3e9bfb9a9c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1024,10 +1024,23 @@ static void etm4_disable(struct coresight_device *csdev, coresight_set_mode(csdev, CS_MODE_DISABLED); } +static int etm4_trace_id(struct coresight_device *csdev) +{ + struct etmv4_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return etm4_read_alloc_trace_id(drvdata); +} + static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, .enable = etm4_enable, .disable = etm4_disable, + .trace_id = etm4_trace_id, }; static const struct coresight_ops etm4_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 61a46d3bdcc8..e2576531f796 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -105,6 +105,15 @@ struct cs_buffers { void **data_pages; }; +/** + * struct cs_sink_data - data used by coresight_enable_path/coresight_disable_path + */ +struct cs_sink_data { + struct perf_output_handle *handle; + struct coresight_device *sink; + u32 traceid; +}; + static inline void coresight_insert_barrier_packet(void *buf) { if (buf) @@ -129,9 +138,10 @@ static inline void CS_UNLOCK(void __iomem *addr) } while (0); } -void coresight_disable_path(struct list_head *path); +void coresight_disable_path(struct list_head *path, void *sink_data); int coresight_enable_path(struct list_head *path, enum cs_mode mode, void *sink_data); +int coresight_read_traceid(struct list_head *path); struct coresight_device *coresight_get_sink(struct list_head *path); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 117dbb484543..3817743fc0c6 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -280,9 +280,22 @@ static void stm_disable(struct coresight_device *csdev, } } +static int stm_trace_id(struct coresight_device *csdev) +{ + struct stm_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return drvdata->traceid; +} + static const struct coresight_ops_source stm_source_ops = { .enable = stm_enable, .disable = stm_disable, + .trace_id = stm_trace_id, }; static const struct coresight_ops stm_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index 1e67cc7758d7..a95afc890587 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -167,6 +167,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev) int cpu, ret = 0; struct coresight_device *sink; struct list_head *path; + struct cs_sink_data *sink_data; enum coresight_dev_subtype_source subtype; u32 hash; @@ -208,7 +209,14 @@ int coresight_enable_sysfs(struct coresight_device *csdev) goto out; } - ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL); + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) { + ret = -ENOMEM; + goto out; + } + sink_data->traceid = coresight_read_traceid(path); + sink_data->sink = sink; + ret = coresight_enable_path(path, CS_MODE_SYSFS, sink_data); if (ret) goto err_path; @@ -245,15 +253,17 @@ int coresight_enable_sysfs(struct coresight_device *csdev) break; } + kfree(sink_data); out: mutex_unlock(&coresight_mutex); return ret; err_source: - coresight_disable_path(path); + coresight_disable_path(path, sink_data); err_path: coresight_release_path(path); + kfree(sink_data); goto out; } EXPORT_SYMBOL_GPL(coresight_enable_sysfs); @@ -262,6 +272,7 @@ void coresight_disable_sysfs(struct coresight_device *csdev) { int cpu, ret; struct list_head *path = NULL; + struct cs_sink_data *sink_data = NULL; u32 hash; mutex_lock(&coresight_mutex); @@ -273,6 +284,10 @@ void coresight_disable_sysfs(struct coresight_device *csdev) if (!coresight_disable_source_sysfs(csdev, NULL)) goto out; + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); + if (!sink_data) + goto out; + switch (csdev->subtype.source_subtype) { case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: cpu = source_ops(csdev)->cpu_id(csdev); @@ -296,8 +311,11 @@ void coresight_disable_sysfs(struct coresight_device *csdev) break; } - coresight_disable_path(path); + sink_data->sink = coresight_find_activated_sysfs_sink(csdev); + sink_data->traceid = coresight_read_traceid(path); + coresight_disable_path(path, sink_data); coresight_release_path(path); + kfree(sink_data); out: mutex_unlock(&coresight_mutex); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d4f641cd9de6..7dc536eba3e2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -250,7 +250,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index e75428fa1592..0c24520645e2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1253,7 +1253,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data) { - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct etr_perf_buffer *etr_perf; switch (mode) { @@ -1647,7 +1648,8 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index bfca103f9f84..20f0ab73159c 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -232,9 +232,22 @@ static void tpda_disable(struct coresight_device *csdev, dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); } +static int tpda_trace_id(struct coresight_device *csdev) +{ + struct tpda_drvdata *drvdata; + + if (csdev == NULL) + return -EINVAL; + + drvdata = dev_get_drvdata(csdev->dev.parent); + + return drvdata->atid; +} + static const struct coresight_ops_link tpda_link_ops = { .enable = tpda_enable, .disable = tpda_disable, + .trace_id = tpda_trace_id, }; static const struct coresight_ops tpda_cs_ops = { diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 96a32b213669..7f4560b067a8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -21,6 +21,7 @@ #include "coresight-self-hosted-trace.h" #include "coresight-trbe.h" +#include "coresight-priv.h" #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) @@ -1012,7 +1013,8 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode, { struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct trbe_buf *buf = etm_perf_sink_config(handle); WARN_ON(cpudata->cpu != smp_processor_id()); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c index f9ebf20c91e6..92d8a9fb844e 100644 --- a/drivers/hwtracing/coresight/ultrasoc-smb.c +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -217,7 +217,8 @@ static void smb_enable_sysfs(struct coresight_device *csdev) static int smb_enable_perf(struct coresight_device *csdev, void *data) { struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle = data; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + struct perf_output_handle *handle = sink_data->handle; struct cs_buffers *buf = etm_perf_sink_config(handle); pid_t pid; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f09ace92176e..fb1c225076a5 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -344,6 +344,7 @@ struct coresight_ops_sink { * Operations available for links. * @enable: enables flow between iport and oport. * @disable: disables flow between iport and oport. + * @trace_id: Collect the traceid. */ struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, @@ -352,6 +353,7 @@ struct coresight_ops_link { void (*disable)(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out); + int (*trace_id)(struct coresight_device *csdev); }; /** @@ -361,6 +363,7 @@ struct coresight_ops_link { * is associated to. * @enable: enables tracing for a source. * @disable: disables tracing for a source. + * @trace_id: collect the traceid. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); 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Fri, 5 Jul 2024 09:01:25 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 5 Jul 2024 02:01:20 -0700 From: Jie Gan To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Mike Leach , "Rob Herring" , Krzysztof Kozlowski , James Clark CC: Jinlong Mao , Leo Yan , , , , , Tingwei Zhang , Yuanfang Zhang , "Tao Zhang" , Trilok Soni , "Song Chai" , Subject: [PATCH v2 3/4] Coresight: Add Coresight Control Unit driver Date: Fri, 5 Jul 2024 17:00:48 +0800 Message-ID: <20240705090049.1656986-4-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240705090049.1656986-1-quic_jiegan@quicinc.com> References: <20240705090049.1656986-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EwiRMf6LzYG2O_9pcCzF9VOtqr-RIv0I X-Proofpoint-ORIG-GUID: EwiRMf6LzYG2O_9pcCzF9VOtqr-RIv0I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-05_05,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407050067 The Coresight Control Unit hosts miscellaneous configuration registers which control various features related to TMC ETR sink. Based on the trace ID, which is programmed in the related CCU ATID register of a specific ETR, trace data with that trace ID gets into the ETR buffer, while other trace data gets dropped. Enabling source device sets one bit of the ATID register based on source device's trace ID. Disabling source device resets the bit according to the source device's trace ID. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/Kconfig | 6 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-ccu.c | 290 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-ccu.h | 18 ++ 4 files changed, 315 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-ccu.c create mode 100644 drivers/hwtracing/coresight/coresight-ccu.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 06f0a7594169..a36934daa505 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -133,6 +133,12 @@ config CORESIGHT_STM To compile this driver as a module, choose M here: the module will be called coresight-stm. +config CORESIGHT_CCU + tristate "CoreSight Control Unit driver" + help + This driver provides support for CoreSight Control Unit block + that hosts miscellaneous configuration registers. + config CORESIGHT_CPU_DEBUG tristate "CoreSight CPU Debug driver" depends on ARM || ARM64 diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..a668cdba926f 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o +obj-$(CONFIG_CORESIGHT_CCU) += coresight-ccu.o diff --git a/drivers/hwtracing/coresight/coresight-ccu.c b/drivers/hwtracing/coresight/coresight-ccu.c new file mode 100644 index 000000000000..30faf87b1a28 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ccu.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-ccu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" +#include "coresight-trace-id.h" + +DEFINE_CORESIGHT_DEVLIST(ccu_devs, "ccu"); + +#define ccu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset) +#define ccu_readl(drvdata, offset) __raw_readl(drvdata->base + offset) + +/* The Coresight Control Unit uses four ATID registers to control the data filter function based + * on the trace ID for each TMC ETR sink. The length of each ATID register is 32 bits. Therefore, + * the ETR has a related field in CCU that is 128 bits long. Each trace ID is represented by one bit in that filed. + * e.g. ETR0ATID0 layout, set bit 5 for traceid 5 + * bit5 + * ------------------------------------------------------ + * | |28| |24| |20| |16| |12| |8| 1|4| |0| + * ------------------------------------------------------ + * + * e.g. ETR0: + * 127 0 from ATID_offset for ETR0ATID0 + * ------------------------- + * |ATID3|ATID2|ATID1|ATID0| + * + */ +#define CCU_ATID_REG_OFFSET(traceid, atid_offset) \ + ((traceid / 32) * 4 + atid_offset) + +#define CCU_ATID_REG_BIT(traceid) (traceid % 32) +#define CCU_ATID_REG_SIZE 0x10 + +/* + * __ccu_set_etr_traceid: Set bit in the ATID register based on trace ID when enable is true. + * Reset the bit of the ATID register based on trace ID when enable is false. + * + * @csdev: coresight_device struct related to the device + * @traceid: trace ID of the source tracer. + * @enable: True for set bit and false for reset bit. + * + * Returns 0 indicates success. Non-zero result means failure. + */ +static int __ccu_set_etr_traceid(struct coresight_device *csdev, + uint32_t traceid, bool enable) +{ + uint32_t atid_offset = 0; + struct ccu_drvdata *drvdata; + unsigned long flags; + uint32_t reg_offset; + int bit; + uint32_t val; + + drvdata = dev_get_drvdata(csdev->dev.parent); + if (IS_ERR_OR_NULL(drvdata)) + return -EINVAL; + + atid_offset = drvdata->atid_offset; + if (((traceid < 0) && (traceid >= CORESIGHT_TRACE_IDS_MAX)) || atid_offset <= 0) + return -EINVAL; + + spin_lock_irqsave(&drvdata->spin_lock, flags); + CS_UNLOCK(drvdata->base); + + reg_offset = CCU_ATID_REG_OFFSET(traceid, atid_offset); + bit = CCU_ATID_REG_BIT(traceid); + if (reg_offset - atid_offset >= CCU_ATID_REG_SIZE + || bit >= CORESIGHT_TRACE_IDS_MAX) { + CS_LOCK(drvdata); + spin_unlock_irqrestore(&drvdata->spin_lock, flags); + return -EINVAL; + } + + val = ccu_readl(drvdata, reg_offset); + if (enable) + val = val | BIT(bit); + else + val = val & ~BIT(bit); + ccu_writel(drvdata, val, reg_offset); + + CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spin_lock, flags); + return 0; +} + +/* + * ccu_set_atid_offset: Retrieve the offset of the CCU ATID register and store it in the driver data of ETR. + * + * Returns 0 indicates success. If the result is less than zero, it means + * failure. + */ +static int __ccu_set_atid_offset(struct device_node *helper_node, struct coresight_device *helper, int port) +{ + int atid_offset = 0; + struct device_node *node = helper_node; + struct device_node *child_node = NULL; + struct fwnode_handle *child_fwnode = NULL; + struct ccu_drvdata *drvdata; + + if (!helper_node || !helper) + return -EINVAL; + + drvdata = dev_get_drvdata(helper->dev.parent); + if (IS_ERR_OR_NULL(drvdata)) + return -EINVAL; + + child_node = of_get_child_by_name(node, "in-ports"); + if (!child_node) + return -EINVAL; + + child_fwnode = fwnode_graph_get_endpoint_by_id(&child_node->fwnode, port, 0, 0); + if (!child_fwnode) + return -EINVAL; + + fwnode_property_read_u32(child_fwnode, "qcom,ccu-atid-offset", &atid_offset); + drvdata->atid_offset = atid_offset; + dev_dbg(&helper->dev, "atid_offset:0x%x\n", atid_offset); + + return 0; +} + +static int ccu_set_atid_offset(struct coresight_device *sink, struct coresight_device *helper) +{ + int port, i, ret = 0; + struct device_node *node; + + for (i = 0; i < sink->pdata->nr_outconns; ++i) { + if (sink->pdata->out_conns[i]->dest_dev) { + port = sink->pdata->out_conns[i]->dest_port; + node = sink->pdata->out_conns[i]->dest_fwnode->dev->of_node; + ret = __ccu_set_atid_offset(node, helper, port); + return ret; + } + } + + return -EINVAL; +} + +/* + * ccu_set_etr_traceid: Retrieve the ATID offset and trace ID. + * + * Returns 0 indicates success. None-zero result means failure. + */ +static int ccu_set_etr_traceid(struct coresight_device *csdev, struct cs_sink_data *sink_data, bool enable) +{ + if ((sink_data->traceid < 0) || (csdev == NULL) || (sink_data->sink == NULL)) { + dev_dbg(&csdev->dev, "Invalid parameters\n"); + return -EINVAL; + } + + if (ccu_set_atid_offset(sink_data->sink, csdev)) + return -EINVAL; + + dev_dbg(&csdev->dev, "traceid is %d\n", sink_data->traceid); + + return __ccu_set_etr_traceid(csdev, sink_data->traceid, enable); +} + +static int ccu_enable(struct coresight_device *csdev, enum cs_mode mode, + void *data) +{ + int ret = 0; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + + ret = ccu_set_etr_traceid(csdev, sink_data, true); + if (ret) + dev_dbg(&csdev->dev,"enable data filter failed\n"); + + return 0; +} + +static int ccu_disable(struct coresight_device *csdev, void *data) +{ + int ret = 0; + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; + + ret = ccu_set_etr_traceid(csdev, sink_data, false); + if (ret) + dev_dbg(&csdev->dev,"disable data filter failed\n"); + + return 0; +} + +static const struct coresight_ops_helper ccu_helper_ops = { + .enable = ccu_enable, + .disable = ccu_disable, +}; + +static const struct coresight_ops ccu_ops = { + .helper_ops = &ccu_helper_ops, +}; + +static int ccu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct coresight_platform_data *pdata; + struct ccu_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + struct resource *res; + + desc.name = coresight_alloc_device_name(&ccu_devs, dev); + if (!desc.name) + return -ENOMEM; + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + pdev->dev.platform_data = pdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + drvdata->dev = &pdev->dev; + drvdata->atid_offset = 0; + platform_set_drvdata(pdev, drvdata); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ccu-base"); + if (!res) + return -ENODEV; + drvdata->pbase = res->start; + + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); + if (!drvdata->base) + return -ENOMEM; + + desc.type = CORESIGHT_DEV_TYPE_HELPER; + desc.pdata = pdev->dev.platform_data; + desc.dev = &pdev->dev; + desc.ops = &ccu_ops; + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + dev_dbg(dev, "CCU initialized: %s\n", desc.name); + return 0; +} + +static void ccu_remove(struct platform_device *pdev) +{ + struct ccu_drvdata *drvdata = platform_get_drvdata(pdev); + + coresight_unregister(drvdata->csdev); +} + +static const struct of_device_id ccu_match[] = { + {.compatible = "qcom,coresight-ccu"}, + {} +}; + +static struct platform_driver ccu_driver = { + .probe = ccu_probe, + .remove = ccu_remove, + .driver = { + .name = "coresight-ccu", + .of_match_table = ccu_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init ccu_init(void) +{ + return platform_driver_register(&ccu_driver); +} +module_init(ccu_init); + +static void __exit ccu_exit(void) +{ + platform_driver_unregister(&ccu_driver); +} +module_exit(ccu_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CoreSight Control Unit driver"); diff --git a/drivers/hwtracing/coresight/coresight-ccu.h b/drivers/hwtracing/coresight/coresight-ccu.h new file mode 100644 index 000000000000..d2895d288c88 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ccu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CCU_H +#define _CORESIGHT_CCU_H + +struct ccu_drvdata { + void __iomem *base; + phys_addr_t pbase; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spin_lock; + uint32_t atid_offset; +}; + +#endif