From patchwork Thu Jun 27 18:03:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 807902 Delivered-To: patch@linaro.org Received: by 2002:adf:e842:0:b0:362:4979:7f74 with SMTP id d2csp937511wrn; Thu, 27 Jun 2024 11:05:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWQM3MmDj5cg3oaKXKk5/LTYTeQ4BQ6vhQT6m04LsfJyA9b1oeVH0SoqxObRrEqdkI+4QlBD0H28Iymorg6CcB2 X-Google-Smtp-Source: AGHT+IGBYnxeJrPWS7HceaYLijZYBS3l8HQORH36snU15QkPRX06czUP2uAmPFWIkul5Y+KF22qF X-Received: by 2002:a05:6214:19ea:b0:6b4:febe:e86b with SMTP id 6a1803df08f44-6b54099c35amr208569136d6.4.1719511515124; Thu, 27 Jun 2024 11:05:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1719511515; cv=none; d=google.com; s=arc-20160816; b=IGwXBCFRgCgR1D6ifXiyhQuvYPFLyChSh0twFKJKwoUtrcjMgOngTkBYMQ4NjsWICH o+w4I+sjpZjOxT9JLVxzxZvJ7hx3dvpmKUt1GySfxBGy8GXaSV+2B3l10IdopitJ+5R+ 6n4wGRodZI8BmtvdylGSZepDkMf584HunQXgbIxXTSXObK8dVVgN71agKg/NazjwV02M Ohf4fb9prJxZOETKPBimj4SIHJywtcGWyqIKPLsPDeVxFGaI7TPyXiwnINYuwP2hdKrI UonUe6euqytYCnVaXtaSgc0Czqo9BZoB0X8fjEp9l6W3urYUa3Gpl1kcUgwPIhVTtrM9 tSGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AX9ylv1erEuktvBeFNptQKlvwEwxi/3GoH2xuhP/ArI=; fh=kyPrIR1BE4roCkZQ1B6IGIhtuBXZ6jnqUwWV6BJmstw=; b=HsVqpr3Letf/7xEJL3g5978unxIhuUGXALP+MZvWCYCHddc59+ezC3VkQ8WWBqsHX5 fEKsAXqpLxqgerCMjSYZV8anplXm59bcUfOY/xbrrk1UVh+TMVCHrMs2vch3waiV/lF1 xCIbeq1yD/8uE8gigGYOelHdQAYMF1ErIp7IgQMnT0pEcnclNstZ8r13U5T0Shjhvzzj xisu4mi1dvYZZBu1mNiDuA6fkoTFpFL9K1rnMz8z+M4s9saYe7yiyqDrqjcdFuLxOOWC wWNBCCCzl14dq68hA6NdUI8tfqWQLEE1AnTrSEPruB8y4GM/H+QxJjoVOC8bBLQBXvs4 jhtQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IIO7iMVn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6b59e622efdsi1593796d6.595.2024.06.27.11.05.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Jun 2024 11:05:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IIO7iMVn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sMtTY-000199-Ay; Thu, 27 Jun 2024 14:04:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sMtTR-00017u-MB for qemu-devel@nongnu.org; Thu, 27 Jun 2024 14:03:57 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sMtTO-0001Li-KO for qemu-devel@nongnu.org; Thu, 27 Jun 2024 14:03:57 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-707040e3018so5698911a12.1 for ; Thu, 27 Jun 2024 11:03:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719511433; x=1720116233; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AX9ylv1erEuktvBeFNptQKlvwEwxi/3GoH2xuhP/ArI=; b=IIO7iMVnToUFvBd407vOVyVNp0avbXKunS2TebnfsQVD2Awckcxn5UmXhzj8Eqc1Wx LyZkDQUkJTlyhPhIsMKctGVi5lxHF42ySXngDsLJ6nPWRdhmDYu7THgeMAFPRSdFiK7U 4gMpFDwlv9ehZm+4oUtrGNwuDVXj2nZ0Mm+W13C/rfcVis+2NuYE02/izD+ih9JwA2g+ IbxzI9Sfp43rGLLJq0I1j8oC8/MKXw0M9dnwlJ8rS3KJwG0b/MvE3LxsdgL/V+AA7ivH wNcdmeQ1y1K8y4eKTH++lpH28b8ZGDezjbxIPE8JT0Aum7qGj5IbKW7/0TexPAQWGbKP HkgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719511433; x=1720116233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AX9ylv1erEuktvBeFNptQKlvwEwxi/3GoH2xuhP/ArI=; b=rkuS1pQztqa5l6oBPgco5X8gtATeEhfAcUf5hdOURW1bsfpD2cKeLRLPgN1KVu8Oca HIGKdxyBEI5rnvKt1GQeMc8sP1OieMUVHtC/sw0Joz7r4KiAFKNlkkSo5Z/Zl9ndd6fQ DWBOZedWyzuAvunX1jCbwoDsDw0yzll+JolVpz4SyEvgqaEnU63g4If4WGWNz6JUDTPd ZGJeIUw9UKnJ82sByfaHgDx240rvisggamhYy6tdMG2nDLM4As8laTDTgJGBKtR6UQS2 hB4XNvtyZJ3nNa3gU4RepQSnWKIb0sNZep/TLvcjarvb3RnyDKq3/8ur3WT98KLwy5HH KQYQ== X-Gm-Message-State: AOJu0Ywq7E6wHD9Om3eLOCV4tzkCQ2BLwglclt4mCIKitF+7K7J4vFmZ f8Eiq8XLP0lNhJfLxIfyfJf6CneVMK/7WMXPPkBbY1qVPh/elypY1QmLRb5YACZmdWcarsNtHCD V X-Received: by 2002:a05:6a20:3016:b0:1be:c551:b74a with SMTP id adf61e73a8af0-1bec551b9femr4738440637.59.1719511432866; Thu, 27 Jun 2024 11:03:52 -0700 (PDT) Received: from stoup.. (174-21-76-141.tukw.qwest.net. [174.21.76.141]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70803ecf764sm2170b3a.106.2024.06.27.11.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 11:03:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: brad@comstyle.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, qemu-riscv@nongnu.org Subject: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv Date: Thu, 27 Jun 2024 11:03:48 -0700 Message-Id: <20240627180350.128575-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240627180350.128575-1-richard.henderson@linaro.org> References: <20240627180350.128575-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move detection code out of tcg, similar to other hosts. Signed-off-by: Richard Henderson --- host/include/riscv/host/cpuinfo.h | 23 +++++++++ tcg/riscv/tcg-target.h | 46 ++++++++--------- util/cpuinfo-riscv.c | 85 +++++++++++++++++++++++++++++++ tcg/riscv/tcg-target.c.inc | 84 +++--------------------------- util/meson.build | 2 + 5 files changed, 139 insertions(+), 101 deletions(-) create mode 100644 host/include/riscv/host/cpuinfo.h create mode 100644 util/cpuinfo-riscv.c diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h new file mode 100644 index 0000000000..2b00660e36 --- /dev/null +++ b/host/include/riscv/host/cpuinfo.h @@ -0,0 +1,23 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu identification for RISC-V. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_ZBA (1u << 1) +#define CPUINFO_ZBB (1u << 2) +#define CPUINFO_ZICOND (1u << 3) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 2c1b680b93..1a347eaf6e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,6 +25,8 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H +#include "host/cpuinfo.h" + #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) @@ -80,18 +82,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#if defined(__riscv_arch_test) && defined(__riscv_zbb) -# define have_zbb true -#else -extern bool have_zbb; -#endif - /* optional instructions */ #define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_div2_i32 0 -#define TCG_TARGET_HAS_rot_i32 have_zbb +#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 @@ -106,17 +102,17 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 #define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_bswap16_i32 have_zbb -#define TCG_TARGET_HAS_bswap32_i32 have_zbb +#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_andc_i32 have_zbb -#define TCG_TARGET_HAS_orc_i32 have_zbb -#define TCG_TARGET_HAS_eqv_i32 have_zbb +#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_clz_i32 have_zbb -#define TCG_TARGET_HAS_ctz_i32 have_zbb -#define TCG_TARGET_HAS_ctpop_i32 have_zbb +#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 @@ -125,7 +121,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_div2_i64 0 -#define TCG_TARGET_HAS_rot_i64 have_zbb +#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 @@ -137,18 +133,18 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ext8u_i64 1 #define TCG_TARGET_HAS_ext16u_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_bswap16_i64 have_zbb -#define TCG_TARGET_HAS_bswap32_i64 have_zbb -#define TCG_TARGET_HAS_bswap64_i64 have_zbb +#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_andc_i64 have_zbb -#define TCG_TARGET_HAS_orc_i64 have_zbb -#define TCG_TARGET_HAS_eqv_i64 have_zbb +#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 have_zbb -#define TCG_TARGET_HAS_ctz_i64 have_zbb -#define TCG_TARGET_HAS_ctpop_i64 have_zbb +#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) +#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c new file mode 100644 index 0000000000..6b97100620 --- /dev/null +++ b/util/cpuinfo-riscv.c @@ -0,0 +1,85 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu identification for RISC-V. + */ + +#include "qemu/osdep.h" +#include "host/cpuinfo.h" + +unsigned cpuinfo; +static volatile sig_atomic_t got_sigill; + +static void sigill_handler(int signo, siginfo_t *si, void *data) +{ + /* Skip the faulty instruction */ + ucontext_t *uc = (ucontext_t *)data; + uc->uc_mcontext.__gregs[REG_PC] += 4; + + got_sigill = 1; +} + +/* Called both as constructor and (possibly) via other constructors. */ +unsigned __attribute__((constructor)) cpuinfo_init(void) +{ + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND; + unsigned info = cpuinfo; + + if (info) { + return info; + } + + /* Test for compile-time settings. */ +#if defined(__riscv_arch_test) && defined(__riscv_zba) + info |= CPUINFO_ZBA; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zbb) + info |= CPUINFO_ZBB; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zicond) + info |= CPUINFO_ZICOND; +#endif + left &= ~info; + + if (left) { + struct sigaction sa_old, sa_new; + + memset(&sa_new, 0, sizeof(sa_new)); + sa_new.sa_flags = SA_SIGINFO; + sa_new.sa_sigaction = sigill_handler; + sigaction(SIGILL, &sa_new, &sa_old); + + if (left & CPUINFO_ZBA) { + /* Probe for Zba: add.uw zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" + : : : "memory"); + info |= !got_sigill * CPUINFO_ZBA; + left &= ~CPUINFO_ZBA; + } + + if (left & CPUINFO_ZBB) { + /* Probe for Zba: andn zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" + : : : "memory"); + info |= !got_sigill * CPUINFO_ZBB; + left &= ~CPUINFO_ZBB; + } + + if (left & CPUINFO_ZICOND) { + /* Probe for Zicond: czero.eqz zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" + : : : "memory"); + info |= !got_sigill * CPUINFO_ZICOND; + left &= ~CPUINFO_ZICOND; + } + + sigaction(SIGILL, &sa_old, NULL); + assert(left == 0); + } + + info |= CPUINFO_ALWAYS; + cpuinfo = info; + return info; +} diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 639363039b..d334857226 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,20 +113,6 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_A7, }; -#ifndef have_zbb -bool have_zbb; -#endif -#if defined(__riscv_arch_test) && defined(__riscv_zba) -# define have_zba true -#else -static bool have_zba; -#endif -#if defined(__riscv_arch_test) && defined(__riscv_zicond) -# define have_zicond true -#else -static bool have_zicond; -#endif - static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); @@ -594,7 +580,7 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) { - if (have_zbb) { + if (cpuinfo & CPUINFO_ZBB) { tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO); } else { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); @@ -604,7 +590,7 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { - if (have_zba) { + if (cpuinfo & CPUINFO_ZBA) { tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO); } else { tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); @@ -614,7 +600,7 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - if (have_zbb) { + if (cpuinfo & CPUINFO_ZBB) { tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0); } else { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); @@ -624,7 +610,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { - if (have_zbb) { + if (cpuinfo & CPUINFO_ZBB) { tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0); } else { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); @@ -1080,7 +1066,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, int tmpflags; TCGReg t; - if (!have_zicond && (!c_cmp2 || cmp2 == 0)) { + if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) { tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, val1, c_val1, val2, c_val2); return; @@ -1089,7 +1075,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2); t = tmpflags & ~SETCOND_FLAGS; - if (have_zicond) { + if (cpuinfo & CPUINFO_ZICOND) { if (tmpflags & SETCOND_INV) { tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1); } else { @@ -1304,7 +1290,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, /* TLB Hit - translate address using addend. */ if (addr_type != TCG_TYPE_I32) { tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); - } else if (have_zba) { + } else if (cpuinfo & CPUINFO_ZBA) { tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); } else { @@ -1335,7 +1321,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, if (addr_type != TCG_TYPE_I32) { tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG); - } else if (have_zba) { + } else if (cpuinfo & CPUINFO_ZBA) { tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG); } else { @@ -2110,62 +2096,8 @@ static void tcg_out_tb_start(TCGContext *s) /* nothing to do */ } -static volatile sig_atomic_t got_sigill; - -static void sigill_handler(int signo, siginfo_t *si, void *data) -{ - /* Skip the faulty instruction */ - ucontext_t *uc = (ucontext_t *)data; - uc->uc_mcontext.__gregs[REG_PC] += 4; - - got_sigill = 1; -} - -static void tcg_target_detect_isa(void) -{ -#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond) - /* - * TODO: It is expected that this will be determinable via - * linux riscv_hwprobe syscall, not yet merged. - * In the meantime, test via sigill. - */ - - struct sigaction sa_old, sa_new; - - memset(&sa_new, 0, sizeof(sa_new)); - sa_new.sa_flags = SA_SIGINFO; - sa_new.sa_sigaction = sigill_handler; - sigaction(SIGILL, &sa_new, &sa_old); - -#ifndef have_zba - /* Probe for Zba: add.uw zero,zero,zero. */ - got_sigill = 0; - asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory"); - have_zba = !got_sigill; -#endif - -#ifndef have_zbb - /* Probe for Zba: andn zero,zero,zero. */ - got_sigill = 0; - asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory"); - have_zbb = !got_sigill; -#endif - -#ifndef have_zicond - /* Probe for Zicond: czero.eqz zero,zero,zero. */ - got_sigill = 0; - asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory"); - have_zicond = !got_sigill; -#endif - - sigaction(SIGILL, &sa_old, NULL); -#endif -} - static void tcg_target_init(TCGContext *s) { - tcg_target_detect_isa(); - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; diff --git a/util/meson.build b/util/meson.build index 72b505df11..5d8bef9891 100644 --- a/util/meson.build +++ b/util/meson.build @@ -127,4 +127,6 @@ elif cpu == 'loongarch64' util_ss.add(files('cpuinfo-loongarch.c')) elif cpu in ['ppc', 'ppc64'] util_ss.add(files('cpuinfo-ppc.c')) +elif cpu in ['riscv32', 'riscv64'] + util_ss.add(files('cpuinfo-riscv.c')) endif From patchwork Thu Jun 27 18:03:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 807903 Delivered-To: patch@linaro.org Received: by 2002:adf:e842:0:b0:362:4979:7f74 with SMTP id d2csp937596wrn; Thu, 27 Jun 2024 11:05:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXi2gkgyOVreN8/hefA7oO0Xi5V799NXihnaI4MynT7KVBVzjsVCwAXqMC/gv/u99qmFE2q3cl2auY+mrePD/ZB X-Google-Smtp-Source: AGHT+IEvNIU3uY87PpADygsF8f7GFO5sEPyjKhsyah4FCA1eajequTg1IPdb+8r1XXBbSo/dyzdn X-Received: by 2002:a4a:a54f:0:b0:5c2:2033:db19 with SMTP id 006d021491bc7-5c22033dcf0mr7909743eaf.5.1719511524569; Thu, 27 Jun 2024 11:05:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1719511524; cv=none; d=google.com; s=arc-20160816; b=PT6WSpcpzUlrog57xXoOg19M891Gk60ADEjNyVsLBJDuP6OYLl5TSYPn1ve8HwOuwv I4mGKFE13H1ZtjfpX33ap08DhjMqibaf1g8pPDfBAW9EvpWsP4QOp+FBVUx4gCxD3f8S 68QHnPDYUIMAbFTLH3OSEIRuryTiKwk+6WoYNuxyAD6SesHW65IMpMRdWq3Cqwh1BeTf 5A2451SzTH+VaiVwriih4OG8COgupqDWm6mtjBjLL3e5ls6fcyWchi21waH9lwnoQOJt YjPv81il4w6TZPm8DRY/iUizYL/hJDdjxI5nRL5FKlHT7NjorFOeO8Z09mnwUM8/oO9F WTAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TAEbuMWRBzQhtzD9qy0BIESVSrOd35nsQcBa/S7f+Kw=; fh=kyPrIR1BE4roCkZQ1B6IGIhtuBXZ6jnqUwWV6BJmstw=; b=Ho7o+CZ0tnoLrN4MvchL4P1CWU3Ju8jGP2agHhw0UIc+fSmRxU6rurjYoYjCx27lyk x1JodK8reXO2shD6CnDQ+k7p6fIrwy1mmT5Zpi/gx4KprCyA4G9E4KEsiM5dksRQn7MI A04UbXoxtmJ/l4TNYDnJq0G9gIqK64UOG4sSkH7jopb6fVZLaj04UfUA22glky94+By4 0GgOfYMR8XAxDwepkyOfdXedQnq9s4hdH5qR9pyyY5DhDfFDdCUwV9KWrA46iAh+zQdc Vq7djhJ/9i9JHFP0dsmwmCTV/I4Txlg6mF7e0yHeJaXp9jl5gLr+/K5J8cIJJ0hMIq7A O2eA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ucUhODRp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 71dfb90a1353d-4f29224e45asi44668e0c.140.2024.06.27.11.05.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Jun 2024 11:05:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ucUhODRp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sMtTh-0001Ad-Ch; Thu, 27 Jun 2024 14:04:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sMtTe-0001A1-8V for qemu-devel@nongnu.org; Thu, 27 Jun 2024 14:04:10 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sMtTP-0001M1-8j for qemu-devel@nongnu.org; Thu, 27 Jun 2024 14:04:09 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-7178ba1c24bso4587360a12.3 for ; Thu, 27 Jun 2024 11:03:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719511434; x=1720116234; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TAEbuMWRBzQhtzD9qy0BIESVSrOd35nsQcBa/S7f+Kw=; b=ucUhODRpQUnzl5mVD1nKMZl4ptEf1xudg8JOp+PRtq1tiVI6X6bZmfMDY90U7y82iG topoq18AfXYQEaym2iTKmSaAzus09cUqEor2k41CHxEVJyghRVIGowz9WiGxCFUJbtCI MUpV+9/SdL13cjZtM403LEKGVzjYxOlcV4djUkVgCKj9Vu16VW6Z8Y/yP4cG2aYH2AvR ODk5GpU27rY7MzUtJfhwUhjSmNFlctplOatV1HXsvkc1xsYU/sDYRsyj2Ch3SDrXUtCL 7s+euDVusjhGT92ZW6et+Ui6/Wu01JC9Xby1MWmX7fgvR/qopbLUy6MWFi5VdGXeGY1U J79w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719511434; x=1720116234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TAEbuMWRBzQhtzD9qy0BIESVSrOd35nsQcBa/S7f+Kw=; b=oVyB2UtvjEHGTyqx+0cBoiGn5/+by7Mijxbzk7fXNDFbAINN130wurSfC6hp1KgxBY 4JDFTlhyWEjeLXHU+Je28lItBAkFVvoovlz+C8+VCTI2a+5x6c5Ct8NqlAD1Js6NK+5i N3IFfULC4N4i50Oj6VfSKIhRWu75HBLIsqoN37iXiDJFuvIlZggqhYeK5E8MhWtVDP25 BFsLpou8B5pB2cHeNOOGCPM3yoU8DGjCYZ6us1OSClnQ3kRy4wNLdUd9RrT9trd/Y/16 wILUl5OmWPt+9YnTLPPJk4ZVS8Y0w65jwHgCDcqEe6wH4wbymmZn7/YbfBaPH1dRWzHv t/vg== X-Gm-Message-State: AOJu0Yz2HRMtcufPbSR4soC6ghiM7q6onh90074Yz+lC7mrcPYDz/w/p 27D0s/60eQ1TwymDr5qtEkiA7VadzgHWPGlQU/JfZrdCoPecVvqjGhFfnO1Ytda1dd2htmlOO82 m X-Received: by 2002:a05:6a21:3289:b0:1be:cea5:c77e with SMTP id adf61e73a8af0-1becea5cf6fmr3546140637.7.1719511433704; Thu, 27 Jun 2024 11:03:53 -0700 (PDT) Received: from stoup.. (174-21-76-141.tukw.qwest.net. [174.21.76.141]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70803ecf764sm2170b3a.106.2024.06.27.11.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 11:03:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: brad@comstyle.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, qemu-riscv@nongnu.org Subject: [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame Date: Thu, 27 Jun 2024 11:03:49 -0700 Message-Id: <20240627180350.128575-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240627180350.128575-1-richard.henderson@linaro.org> References: <20240627180350.128575-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reported-by: Brad Smith Signed-off-by: Richard Henderson --- util/cpuinfo-riscv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 6b97100620..abf799794f 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -13,7 +13,14 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) { /* Skip the faulty instruction */ ucontext_t *uc = (ucontext_t *)data; + +#ifdef __linux__ uc->uc_mcontext.__gregs[REG_PC] += 4; +#elif defined(__OpenBSD__) + uc->sc_sepc += 4; +#else +# error Unsupported OS +#endif got_sigill = 1; } From patchwork Thu Jun 27 18:03:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 807901 Delivered-To: patch@linaro.org Received: by 2002:adf:e842:0:b0:362:4979:7f74 with SMTP id d2csp937500wrn; Thu, 27 Jun 2024 11:05:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWCfBJFVkAHpd9TBIG2hvuU+pFGytl/7/RCwxcT1rP+iafW5iLAlUrtXosWgI5t9x/fUc6rU2pZTzI5u5eGvhPL X-Google-Smtp-Source: AGHT+IHOtoRtA14bF2JUNWeiCyA6Q6DCpNYwpr0DPknkzPuRf7ZWaDM1PcbAh5ZsopBJkVAyi97B X-Received: by 2002:a05:622a:5689:b0:445:320:d92f with SMTP id d75a77b69052e-4450320da3cmr95842721cf.26.1719511514226; Thu, 27 Jun 2024 11:05:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1719511514; cv=none; d=google.com; s=arc-20160816; b=thLw3RSV6bNmYFTjS+3+tEmZh++fPoWhURDYR512dXmvWFgr5frhDhkI7pm/JadiGt +H4W9pS447Tw6lAWgZp0z8OiyomlFRX3ojKWi3VCmFN0VSBL7Td5lby/41YPdnm3p1hk 5NN+B7p9WTXozGLppzFH9UeNf+j55wzUVkveFINEucj2A9SDOWpsylCw1iGt68L6RpRO YzISHl1SOAE+DSBmFd1BrjOhw3F/4ij3tceERmjfvOSBt+6rn8meh3MkmV8x1B2y7lDM WDd48nVAq8GP1DeTd+Elsjdy8t1tiogFqDANz+zC3PRf5tWpo0k7oCIxUs7OPQ2Xqe3m D6KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S0iy7OmdnIv4vhHrmSzHh4pajG0G9qYEbVVtDoAkstk=; fh=kyPrIR1BE4roCkZQ1B6IGIhtuBXZ6jnqUwWV6BJmstw=; b=U+7k5SbTpfIvDUng14gezktN0rjVWO7bBt2qAOuafxPVHvFanqbOgpktX1aVlqJPAr ghxKryhkbBwXaLIwhdKbIuYmC2/tJhRH1gtCVGMvzWe/E+rNkCj7hN0swESCP7s/xoxe hw+Re4ZQx1GedccbUQFxxfTQ/+DXk2BuehYd6ZzJileCLOz/OAgpTDIM65ysZkuRh05H PXGlPLIotAudw2K/fxaan8yuw8FDR70E68r6rl0hTj0KvgKJwrJBn4sChzVqfyMtwG3/ 3ZoQeSZytZGignF7xONRGw6pZy1DBk3AeqmJRt5UsfMgJDVqBeCW5MVVwYh2GDhGg6EA kqsQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZaugFMYc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-446514c24e2si1111461cf.569.2024.06.27.11.05.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Jun 2024 11:05:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZaugFMYc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sMtTl-0001B5-Oq; Thu, 27 Jun 2024 14:04:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sMtTf-0001AB-9f for qemu-devel@nongnu.org; Thu, 27 Jun 2024 14:04:12 -0400 Received: from mail-io1-xd2d.google.com ([2607:f8b0:4864:20::d2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sMtTP-0001MF-Tr for qemu-devel@nongnu.org; Thu, 27 Jun 2024 14:04:10 -0400 Received: by mail-io1-xd2d.google.com with SMTP id ca18e2360f4ac-7eb5dd9f994so292552139f.2 for ; Thu, 27 Jun 2024 11:03:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719511434; x=1720116234; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S0iy7OmdnIv4vhHrmSzHh4pajG0G9qYEbVVtDoAkstk=; b=ZaugFMYcZ7claEq9OHpyKX+bjT48BmPQLLfq0DN8n3zBtGzw9dOQGLbJN3S+8a5G2k auBHqLBPgl983D/zaSh7+En+D1NddLtmz/8fWTcb0aZhXSLKV3rPb4FDavZSo2JULwmT dK/0Niv53hWues1fFLDXyq8e1sPV0A4r6z/ZOZ4JF8u8DWGX/virs1m+H9uv6LbDwDjA TRyHbweLoAYuDNkER3tmsZTCfeXX9BPT7c/08MVFZcfKPXTUJ2XO5Wy91LeUm4WHLzoz Cc6yWy61s+0R9bG35HbULfdv1vshB2MZyrrnAccbHGI4EyNjVZlYv2QSLGte80sBBXf6 tUWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719511434; x=1720116234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S0iy7OmdnIv4vhHrmSzHh4pajG0G9qYEbVVtDoAkstk=; b=ZgdNsfOjDC6IjE8gyfJGWz2DRwv3eif0mvbU9Hc4WofivH/xe29S4CZ1Vvm8bs1ErA TAwrk76zbIp9rlCqDIaAOmNtw3CVXtkIBH5YkewNA7MbSFFns+GiQG3UZBEATbuvd1db tThh/Juu4g9YlJ9C83JKvmz6W3V56+rXsOvd9zXfCBbhNQJbjhIeZu0BGwQVjsWypCRE esu6agCouvMsFql3vnY6q7hGTLYfSYmOXUYAlHiZKy8AhGQv0VU13kxTXwHnTrGGL++T sicHSUoHLsNeAOSGrEqrqBUgdOF/IDz4XCJVQ1x4lBhRXXgvZwJujJACTa4DKZ9v8Yin z6lw== X-Gm-Message-State: AOJu0YyoDf+Lx6ARjhB5IhWlFstme8tYn3LzrudYrLBOjxkfOYEvS7Zs CX09/dRI0+c8p8eIj/IdyOp5JfUCKl0fjBcU6C2gwQ2Pr1Lj7mYY/n1kxOvjPkneVWuqPILP180 S X-Received: by 2002:a05:6602:3f8a:b0:7f1:3ad1:2341 with SMTP id ca18e2360f4ac-7f3a13db517mr1966042139f.7.1719511434499; Thu, 27 Jun 2024 11:03:54 -0700 (PDT) Received: from stoup.. (174-21-76-141.tukw.qwest.net. [174.21.76.141]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70803ecf764sm2170b3a.106.2024.06.27.11.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 11:03:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: brad@comstyle.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, qemu-riscv@nongnu.org Subject: [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall Date: Thu, 27 Jun 2024 11:03:50 -0700 Message-Id: <20240627180350.128575-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240627180350.128575-1-richard.henderson@linaro.org> References: <20240627180350.128575-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With recent linux kernels, there is a syscall to probe for various ISA extensions. These bits were phased in over several kernel releases, so we still require checks for symbol availability. Signed-off-by: Richard Henderson --- meson.build | 6 ++++++ util/cpuinfo-riscv.c | 26 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/meson.build b/meson.build index 97e00d6f59..58afd0125d 100644 --- a/meson.build +++ b/meson.build @@ -2837,6 +2837,12 @@ have_cpuid_h = cc.links(''' }''') config_host_data.set('CONFIG_CPUID_H', have_cpuid_h) +# Don't bother to advertise asm/hwprobe.h for old versions that do +# not contain RISCV_HWPROBE_EXT_ZBA. +config_host_data.set('CONFIG_ASM_HWPROBE_H', + cc.has_header_symbol('asm/hwprobe.h', + 'RISCV_HWPROBE_EXT_ZBA')) + config_host_data.set('CONFIG_AVX2_OPT', get_option('avx2') \ .require(have_cpuid_h, error_message: 'cpuid.h not available, cannot enable AVX2') \ .require(cc.links(''' diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index abf799794f..cf59ce83a3 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -6,6 +6,11 @@ #include "qemu/osdep.h" #include "host/cpuinfo.h" +#ifdef CONFIG_ASM_HWPROBE_H +#include +#include +#endif + unsigned cpuinfo; static volatile sig_atomic_t got_sigill; @@ -47,6 +52,27 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif left &= ~info; +#ifdef CONFIG_ASM_HWPROBE_H + if (left) { + /* + * TODO: glibc 2.40 will introduce , which + * provides __riscv_hwprobe and __riscv_hwprobe_one, + * which is a slightly cleaner interface. + */ + struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 }; + if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0 + && pair.key >= 0) { + info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; + info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); +#ifdef RISCV_HWPROBE_EXT_ZICOND + info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; + left &= ~CPUINFO_ZICOND; +#endif + } + } +#endif /* CONFIG_ASM_HWPROBE_H */ + if (left) { struct sigaction sa_old, sa_new;