From patchwork Wed Jun 26 21:45:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 807547 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7FF2191476 for ; Wed, 26 Jun 2024 21:46:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438367; cv=none; b=AifJspkJlcPAoT9+sD4X2oVhOvOfv7bfBDqFUXv8Bv+M6FctlBROoG47Fen75f60K613wtF1s9HoBrWIoYRWkohGTxeNueyz7ABFEN24KzVN8c7cBKrlRdssZxGrUnlenP2CzWu/Ule0yPVp7uvn++kgMeSJQ6eJiZI9X19B9JM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438367; c=relaxed/simple; bh=AABfn+5Wuop9C4JWNFNmkXvAwigJm3H71KL3fIC108U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QzcfadXjImI1XH5cfrEUmn/i0PoHXJ+OCYu0fkZ4kNabvBZ7EXCcsG9LcYSmy0Fvam4HM24OQp3sOyiPsPLHqQFoNuq04ZG6vPs7hFOuzfz0l5v8DbxNI/ZLgNGBMdzbiWj6QhGEOlJSYo6PZYUXK6aigfGJ1CxPpZW7SQumjJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Tfk0DhDL; arc=none smtp.client-ip=209.85.208.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Tfk0DhDL" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2ebe40673d8so83558981fa.3 for ; Wed, 26 Jun 2024 14:46:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719438364; x=1720043164; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BJ6Ofnj59KCGRdS4jKTFy4IIJWcn+np9cmCpcqde7DA=; b=Tfk0DhDLygVFcIGK46HWyPy0W4e1eYg135Es0v17QKfK5NR1e9KgEz19wxS9kXtYVA 2T554x85LNsAFD8dtzjUfC/kbE+WhMnvnYg2/XePE2RHIPIGZChGGl5ygOVYOvnpjpJR FFy0G5bz9PauaBcBWHM5DHkk/JjrqWo9lebsOYPxKgAysei6Yr9m6y3fVy8J7WZoSsSN nYTP4Ew0AUF9gYCKfP4ru6bdAZ/slqE98XaiZjwhK7uu96ywQC6CMnG2pP2I++mvCcsq rQ3n6TVVSZowndHPc/YCE8T6iwwz+kcgR/JfFg3DyBg+YwzFL2JgvAd0+d4cNRdhVRar i9mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719438364; x=1720043164; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BJ6Ofnj59KCGRdS4jKTFy4IIJWcn+np9cmCpcqde7DA=; b=BSgJkGOZYdoU5VZ92raOoJVqYn+uCKkL38R7RuUihaBCm+GHd1At4oZFjmoQH0F9rO HK+VtlDui4qtgzWrzDwA8qFWynOUoSrNMmrDK6xRbGvMN0ed/L+8GLnWx8xZpVirlsko KE/TI6JM+3e2myfF/RmiMXA2aOmvLYcUtIpGN10Qu0/FKndNlDa9jQrwOItZpfkQHlSq wWrVeRCKxbRMx/ZqYU1uCSu6gvBBsuT9HnSHGoIlMy5ocDEuWtldLwPysVdCUbwkQYLG EiblxvChSNH5ML/nXrCjeFe+aT2Fnw4EtEFvPbcBRvoPBRt8kK3/rCpZS8GyIr8voYKN wv2A== X-Gm-Message-State: AOJu0YwA4jQLtlr56K/HQgtLwt+4bBnHt/kekb97FE4GdfpVwjLHZ4Ef hfvsL+D7CzgPLPVmYPEKVedTf8taEgeMNYylk076u2SMeO2BiT7qGLYtGDwU4b4= X-Google-Smtp-Source: AGHT+IE915cZlH9nn699bYkq4F+smrZwnMAUSpyQaKba2INNBB2cS3+zbtnje0X61BPw/JSw3562AA== X-Received: by 2002:a2e:3218:0:b0:2ec:55f3:40d with SMTP id 38308e7fff4ca-2ec5b346102mr69215361fa.30.1719438363820; Wed, 26 Jun 2024 14:46:03 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ee4a350d96sm23201fa.49.2024.06.26.14.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 14:46:03 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 27 Jun 2024 00:45:55 +0300 Subject: [PATCH v5 01/12] drm/msm/dpu: limit QCM2290 to RGB formats only Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240627-dpu-virtual-wide-v5-1-5efb90cbb8be@linaro.org> References: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> In-Reply-To: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1074; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=AABfn+5Wuop9C4JWNFNmkXvAwigJm3H71KL3fIC108U=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmfIwYuYOCQf2HImzQBD039gclCXtQ4YiEg+N93 3Wd7KLe4NaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnyMGAAKCRCLPIo+Aiko 1fffB/9KorMTaducYeo1F664LtegB//a9stV/tH9mH/NDSIYmWWPJ9YXsFT2gqxLjyDT4BqDsQT 6byaCMtuVkc4sv5GWZ5KVzmJ5gKEiB6ionJJ9qeB4cphW7FC1ZnXiTzW+ZOi3dElbqHialO9juO SjAynXEHeTCZtxCf0R3td/h4hiD6MaAEmsKdTUpdfZgYVHZAcs3tqCDPT5HlrmcKBsdmwwYcY0H SEvg2QSTf3JFVUV0qhJCKXf3Ytfg/KzF+XUsLUPIReTKyjTZbmjcKQoifYaBYNdoLybFTe1IWs0 5126eGHKCLripRExohwWuUcv5rEA2Ro3zpdgjrOq7UXOLpIQ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QCM2290 doesn't have CSC blocks, so it can not support YUV formats even on ViG blocks. Fix the formats declared by _VIG_SBLK_NOSCALE(). Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index fc178ec73907..648c8d0a4c36 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -308,8 +308,8 @@ static const u32 wb2_formats_rgb_yuv[] = { { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ - .format_list = plane_formats_yuv, \ - .num_formats = ARRAY_SIZE(plane_formats_yuv), \ + .format_list = plane_formats, \ + .num_formats = ARRAY_SIZE(plane_formats), \ .virt_format_list = plane_formats, \ .virt_num_formats = ARRAY_SIZE(plane_formats), \ } From patchwork Wed Jun 26 21:45:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 807546 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EAB3194080 for ; Wed, 26 Jun 2024 21:46:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438368; cv=none; b=nmADveIIBmBGCXf9CTHkaFb5B0JZZCMgrDkfpTz9jXLMrfQCN7sBVQ1I9HT6dql9kFcm+sYrwRvNfolpoYYjcoAC8RWxhPB6sScT4WxaKXeCwy1SaqLRLWv5wyVwfdcGednF8xMvDKPYDHYN0fijb38xIFh4FzruL1BL03eNmrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438368; c=relaxed/simple; bh=oZ0yq3Zy7nCQNd1WNthf0ukdXl1hN+VK6wuUcAguRdA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LKH8Dm6wyeuJ9iYXL6RqjtSmxGBjeTc0VC4pNEgmT7rf4yN3bMzmvMzgqw6zeGoMLEyP9m4WBbZ2zIJTn0OIlNc21A0YdTQ0Vzoz+MM/jO3jyRf561++/GkSbkI/O7YetYrM+8xcCirs2XkVzjKFY8Oh0Bw8aTo4AJkvIeXgCOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GEhANpdb; arc=none smtp.client-ip=209.85.208.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GEhANpdb" Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2ebe40673e8so80491811fa.3 for ; Wed, 26 Jun 2024 14:46:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719438365; x=1720043165; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=U+y9Jw/2GdJnbAqYZ072LCGScq8Q/W2kfxFZFo/y7qQ=; b=GEhANpdbhymBJOrUzBSYab+RkqTZ2hmiWCOeb5TZZDgw6N0GVoIUOMxp6Y9iSgoT2G J8VYcpeFcGn/6QTF2nVNG3EYo+MgrV34IOk0P3g0PGMXEKPhQCvPQuyQ0QrIOIRhK6CL cxkDaEVaqVQPDocg3KPyFO/jk9Om9NoJ4n+wCXH+o3G9vIESZyPRz8zzH8lo7wnUOUNo Bb99fMcwrdW1r2ZM6O2DQEtiozpdFIDmEkE6P6nNdjdO/4plHQMNY6m399znbAvzDxR8 iaKD1uiY1SLNeZPAX+NPOj2eBa1IBob3KwvZBJwz4pjff30v9RmUW9tjW3+Nq+jwhTkP Vmsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719438365; x=1720043165; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U+y9Jw/2GdJnbAqYZ072LCGScq8Q/W2kfxFZFo/y7qQ=; b=KAUyV1/aTcAKpHrBff6MWCjLT/KbI1VLNv1ZwMLLspds18XCG6vzH+XZliiH6qcU9i 5CJD/pVyEj8ZPy4QQBdb3LgZU08OmTBXCVGiUcMz3i1N52xwzjVhyJduCyuu95gjVcWP 2c0xfAFHCwL+/BrGTuimO+Cano6hsqiVg23AlWMMj83E82/MATZO1RyYlSybSnt0Dji0 NPEfYmkcbnKxBb5wuMv6yYAlWz4+auMMX7SVjMCZfElLsA3axJLiuqw4nHASwpsaQ+Ff iGfxoCL6ANUyCUOnJYOSzuLn1l4USX9nL/MvXrKM83Cz0MyXCwV2ndNjtDhheSWy4Gp4 0Osw== X-Gm-Message-State: AOJu0YwaqcuT00JRijD+w5w1UTDL8i5uVK1lnxdryRbwJrPGnUXYT/F7 8SH/NSH9L3BWdt+gTNN6/LjpIqF58CvpLAgjCXyRigH/BPNj5Di+wLl9O/FN3qlfGR6x352Rlti gUgs= X-Google-Smtp-Source: AGHT+IGJn3uylwB+3ohJi+8Ec7D8w5JkByYi9a8I9HQib/s9IzApTpfrehCOchB3jirtru6/fxSTOA== X-Received: by 2002:a2e:3009:0:b0:2ec:5ff1:227a with SMTP id 38308e7fff4ca-2ec5ff12384mr64301421fa.17.1719438365371; Wed, 26 Jun 2024 14:46:05 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ee4a350d96sm23201fa.49.2024.06.26.14.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 14:46:04 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 27 Jun 2024 00:45:57 +0300 Subject: [PATCH v5 03/12] drm/msm/dpu: take plane rotation into account for wide planes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240627-dpu-virtual-wide-v5-3-5efb90cbb8be@linaro.org> References: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> In-Reply-To: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1981; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=oZ0yq3Zy7nCQNd1WNthf0ukdXl1hN+VK6wuUcAguRdA=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ1pNj4RDTeh68xSjxS9P/pE5fDh+kX+68OcVvGy+v/p7F 34/4tzfyWjMwsDIxSArpsjiU9AyNWZTctiHHVPrYQaxMoFMYeDiFICJRDuz/9NxmCUb9DZPRp/v 5/+6tOxFJx961U9Pfyl7usfqwvnnt+81cHo27uWNW/TDdmUSy9InQbJy9nuYfx2V5Ta//C6bPej NvVrm+l2v3TJuzP6WtGJtI3u3bvPJhtTzM7K0JPiX3Gi/tdBggdKr6vUx3+fO2nHT/EhOjpf4Jd Ec98V188sYObSzis5d599som5wturrUdYPsy5virBWtdLWsNDmPLfviNPkKQ4eB4vdlSaY8WX9U fHUbMncuML3wwn/lDtq3cLNEW3eEetWMN79olXceOOP6lPVmNwJ1dUPPql/6ApZ0ezhE9c64UiT f/WT7V5Nte6frJ//1ayLUz1hbtpW/zdzrnWMe5/MunOdAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Take into account the plane rotation and flipping when calculating src positions for the wide plane parts. This is not an issue yet, because rotation is only supported for the UBWC planes and wide UBWC planes are rejected anyway because in parallel multirect case only the half of the usual width is supported for tiled formats. However it's better to fix this now rather than stumbling upon it later. Fixes: 80e8ae3b38ab ("drm/msm/dpu: add support for wide planes") Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 148bd79bdcef..8f2759d16247 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -862,6 +862,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; + drm_rect_rotate(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { /* @@ -911,6 +915,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; } + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if (r_pipe->sspp) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) return ret; From patchwork Wed Jun 26 21:45:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 807545 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2404194132 for ; Wed, 26 Jun 2024 21:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438370; cv=none; b=Q0nIlsPV96wiBdMat42doVwR8r4byGrc8iREghlr/92ZJk2qubWtFcaGblleyZzDmlKuVCd75Ymb/gW77wy6zWrjuhP8zWd50C1kAsd2xKNl2Ls4Nw6Dd75V8PlF/LCdnUkD7Gj7XtssM3OvQXvb7Zy85w7Qmydb+L66WpqFKXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438370; c=relaxed/simple; bh=/RuCdxaOfzUqrs6fOdBxa45FoG97EDlhyPdr1MkoBOs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s3pApPeq0f8wDMy8s15v3rPJ4QckbjpIfKDypkB38vuCjusJI2h6Fid0SpMi6kkMlSzP57lFfcz7CM8p5wqGxtSbKABuwLaKmHBKxdwBz+Tx21UeTvzdvv5/glqs/2DVIt3C4SLI+zFyz1V8ITWlCWhNqvtLJecooNw7z4QNM+8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=V/gVDU1T; arc=none smtp.client-ip=209.85.208.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="V/gVDU1T" Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-2ec50a5e230so55174271fa.0 for ; Wed, 26 Jun 2024 14:46:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719438367; x=1720043167; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4Y77eGqbRKhcTZYOAFZtERWR9uOufd9ItYTSL2OCah4=; b=V/gVDU1ToHIVVoTnZCKDGap5iLdF4yhnsl5yGJDhZLRx8XezWoSxGGFtqivjIhGoYR jh4ZRfePej43FH2XBcl7VOETQCjopqBrx9Yf1ZaJAW/9HJCe5CX8F67m8h5oaiiZieUJ hFdjAO2CWnM4slMNEe5oJzv6Fqc4cIeQahiOGEs0qyKPCTyPxRa3VJYlIWBFNdJWnyLG PQsm66aNWSs+m7TNGhDY9/S4GS6HmaH01kUnQSku5cMfNy1atOEVa3WkFIMvfvB9gXxE DfiYynU7xuVl9epg8yJONsvV77zGqxt7jNDiEonW95JxmOoTTSXU7mjdVfBqt2EgC1X8 mpcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719438367; x=1720043167; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4Y77eGqbRKhcTZYOAFZtERWR9uOufd9ItYTSL2OCah4=; b=EN1LsbPNfIA4Ua8+qD1WicpgwbjQNZ30JKX9epQwi/lFju3meB9aoxpYP4fPiz6uhb 3rKSUHwFQftt/1XiwqiAsRJCvLvOZJ5tzPWHybvbPffXws3E94GHQHBbW6xGiCMwZ4t7 MnRGP3FIoj3BzNSms8b63FyFICqTX0ohi85OmdRp7CaNnKACJAbgnfQvw4xXSNz8+xZ1 3rbv51fXkTJgl/wzNkCUo1AFdReD/kqDoFqz9NooasnZhFc9y6N5lBV5u8a1AIfendAD IIslfBhmWkp8CSTPTrNq3Tvv2udY9EXiR1mHs9CCoZNhvXQsCmQN08bowHKC+aPuwa+m Xn3Q== X-Gm-Message-State: AOJu0Yziz48+906rj2hxJhN3Vyd3WDfy/6Lj6gW1hTtoiXrBnmlcz0sV NAC6i+dSaRdmcHOQ8y9m2cLFWraTD4TDUngunEEUjM62MaezWIEN2wijV4Gt8Jk= X-Google-Smtp-Source: AGHT+IHl87h5y7BdQMiyGdU96awBRn9SsFpVAPRjKIFrEljr2L29AbJFfqLCyOki5HDhIAa3XymKYA== X-Received: by 2002:a2e:9f46:0:b0:2eb:d924:43fb with SMTP id 38308e7fff4ca-2ec5b2dd3ebmr67752871fa.41.1719438367129; Wed, 26 Jun 2024 14:46:07 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ee4a350d96sm23201fa.49.2024.06.26.14.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 14:46:06 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 27 Jun 2024 00:45:59 +0300 Subject: [PATCH v5 05/12] drm/msm/dpu: move pstate->pipe initialization to dpu_plane_atomic_check Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240627-dpu-virtual-wide-v5-5-5efb90cbb8be@linaro.org> References: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> In-Reply-To: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2729; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=/RuCdxaOfzUqrs6fOdBxa45FoG97EDlhyPdr1MkoBOs=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ1pNj0RGbgkjszHHxYVifTesr+383jQrxWLtGa4H3kt7X 03/f+dkJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAm4ivF/j+7TODFSobtN0Lt Ff7LLt3lv82IJ4p18cqdB5q9nSZ8Nv8soXk8U0P1YIZr5+HbmVrdX5d7pDLYXzWodc8XefXi5bc n2g9vrSnw+/0s2HXvLRfVpALtre7p/g4ti6wP77s16cQ7HZ6o0wcM3ykWNZXOtD0zfcI/Jcmba8 LtEqdVFN0SSH6pFcWU1hH+SCSeU+2pvWhUcRGb8Aue8JBYjk9ZIr5/jQPfN79N7zcuLlbTf1YV/ XXiIb1wowups240iTFds7FRSlvnuOXo//m3Jc6/aZw4/6lFUpC34r1vG0IqopUffr/Hbc98UO98 e9DfkO5GIceSW7G6KodEZzi/1xDLe3V8cojXDUOxe1sbAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In preparation for virtualized planes support, move pstate->pipe initialization from dpu_plane_reset() to dpu_plane_atomic_check(). In case of virtual planes the plane's pipe will not be known up to the point of atomic_check() callback. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4abaf2bb8a08..325af392e6a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -805,13 +805,22 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, uint32_t max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; - const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); + pipe->sspp = dpu_rm_get_sspp(&kms->rm, pdpu->pipe); + r_pipe->sspp = NULL; + + if (!pipe->sspp) + return -EINVAL; + + pipe_hw_caps = pipe->sspp->cap; + sblk = pipe->sspp->cap->sblk; + min_scale = FRAC_16_16(1, sblk->maxupscale); ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, @@ -828,7 +837,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - r_pipe->sspp = NULL; pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { @@ -1292,7 +1300,6 @@ static void dpu_plane_reset(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1314,16 +1321,6 @@ static void dpu_plane_reset(struct drm_plane *plane) return; } - /* - * Set the SSPP here until we have proper virtualized DPU planes. - * This is the place where the state is allocated, so fill it fully. - */ - pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; - pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; - - pstate->r_pipe.sspp = NULL; - __drm_atomic_helper_plane_reset(plane, &pstate->base); } From patchwork Wed Jun 26 21:46:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 807544 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CF9E1946BB for ; Wed, 26 Jun 2024 21:46:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438372; cv=none; b=m6LDNRMsiLw7v2xAlkQrV04e7Uwc1JyAggY1P/CySB/ZTA1YuI8LcxOSDznTFyJsZgQzI3+PSeLLl4yiD8mJaCAkxFyLq4yltHwhtr4wLa2t9z0K0Yg2U7H0SGH+Dug7mrtRtVqTbwJL0Z8qxkzK2+VuXjE4HUq9aQOvNJCFdwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438372; c=relaxed/simple; bh=D8PRyCR1WP9UcdKkDxh0WihWqPbf3nR7gzVRwJqdq0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=h9HsMI8IeuwFGRIv+7iXwQuY16TmhmTeDJCm/fUyPqoKHgB6UUOg0ZvjCvON/lLVbq2tzrHz3LZfo8pojN9Ozly88kolePfkDpu4mUEl9OW1JfOQTzuUDSmpHJVcLxhvvnkzbtSBs4eBPJsOmWrHr9eA8ZVy7Re2CjwH6lYAFFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=iiL7OxMe; arc=none smtp.client-ip=209.85.208.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="iiL7OxMe" Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-2ec408c6d94so81365341fa.3 for ; Wed, 26 Jun 2024 14:46:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719438369; x=1720043169; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DemnpnKqmXRex86PlFrPzeelpU92AqvZJg2FJufXVcc=; b=iiL7OxMeG2wd2E+T3xIepI13dHz9MWurFqs3lJOOUglcELZzx32uZ3ZLviY9Q3QCKn X5DVwlnRgmCa0htQg/ZR6451Yqje7woLiSmEK1xd6V1CIgtmwk3eUvcIEkgeRIEYrRU9 AWVFeHWv/yDNaAr22BxJg/5P01kkvwob18LRbeLu9uRjXT72SYKS51XhXWYnlzlXqb6m JJVDyFRublxcBp+y5sQ+o5ASifHhC26ICjTAJrsUtW2lF3Owv7A8sJiTCmvW8oAv+twY uPvXufOvXwZsKxeTsLg/BMwwb+fGQXSwuA9SfrufbNQhGsrF5cEUGONA4a1rUqU8aCRh M9Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719438369; x=1720043169; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DemnpnKqmXRex86PlFrPzeelpU92AqvZJg2FJufXVcc=; b=pJo+GtORGeKj9rel41EXLu7oxNTjFnx0Pens3PgbDLJGTP3pU54520aI1RF9LZqERN TGmZaobrWHmJF7p6ui4BbqoNEDcOQcvmYNLGwtFpwV7sZV2Mwh95rAPp7GmR4bvLhgsM 6WRFlTh3KqiYohwozZoVN7l5jYSr97bL+49FbZ5QT56uvzVloPKAz6nEyV5d8gejDIOO V6cwXfhV0y1BZSa4Nvlt02gZ55TbXnkihDCRn4VWtLS6pNDoCvDJiff1YAT5Tx5grDC8 SRREiQ6Vj06ei+HvVaoa40yw5GFJOEz/GiHfML46rKvtELE+3FONKbl/fS8abP10ESMA Lvcg== X-Gm-Message-State: AOJu0Yz5VTzzWc24UqqvxhV3dpH2CiJAR3B8i3h1+WigRcBTg/ZktYls 3P+EkyBHo/UMm/u5bRYDLgb3CDEIcfzm2nwjjj03FaIwbbx6w+BiDMS4wUv28n0= X-Google-Smtp-Source: AGHT+IEeHFUP+yywyF+IBaotMAk8zj7gvRjn8PAXMgbVbycBqrHxOKo1ModXZICS6iRWhs1JdVCsEQ== X-Received: by 2002:a2e:a69e:0:b0:2ee:46ec:60bc with SMTP id 38308e7fff4ca-2ee46ec6229mr8411781fa.27.1719438368720; Wed, 26 Jun 2024 14:46:08 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ee4a350d96sm23201fa.49.2024.06.26.14.46.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 14:46:08 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 27 Jun 2024 00:46:01 +0300 Subject: [PATCH v5 07/12] drm/msm/dpu: move scaling limitations out of the hw_catalog Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240627-dpu-virtual-wide-v5-7-5efb90cbb8be@linaro.org> References: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> In-Reply-To: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4746; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=D8PRyCR1WP9UcdKkDxh0WihWqPbf3nR7gzVRwJqdq0k=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmfIwZJZ3Ku7ERpfNmip/4P3ilOZfz6N7np1kNB 9dApxpeUSeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnyMGQAKCRCLPIo+Aiko 1SYjB/9A/yhQpxaYlLW3rjxz2DJS6WSK7DQ6utjdOmScQMJZ2zfCEO0eH/e4hgsC2ZnMSTilmPP b08rs7EkYiQPty/t/94c6kL+4H6qG3lDcMeV9k+by0yqtym7Y1nQjfVEQiB4/E4Su4DsOYNkZNs vVS21ELPf/TmJT723zBqccgjmqE65ny2f14MuD8WERggIcCTjugW1Vv2DQoJM0JyjMKYCDncfsr cQIR74CEPbQDrkLFPiQsPAgXaFJU95toW624omXd6JsmQk3qJ6+zjqMP+szui2XwprrE6qrUiAK crE30LjA5hZLNSwGhfHs1UfcSAn2idNSrGBvYMFIX90QuUZy X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Max upscale / downscale factors are constant between platforms. In preparation to adding support for virtual planes and allocating SSPP blocks on demand move max scaling factors out of the HW catalog and handle them in the dpu_plane directly. If any of the scaling blocks gets different limitations, this will have to be handled separately, after the plane refactoring. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ------------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 +++++++++++++--- 3 files changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index a3d29c69bda4..e9fd6b36a1c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -113,10 +113,6 @@ #define MAX_HORZ_DECIMATION 4 #define MAX_VERT_DECIMATION 4 -#define MAX_UPSCALE_RATIO 20 -#define MAX_DOWNSCALE_RATIO 4 -#define SSPP_UNITY_SCALE 1 - #define STRCAT(X, Y) (X Y) static const uint32_t plane_formats[] = { @@ -274,8 +270,6 @@ static const u32 wb2_formats_rgb_yuv[] = { /* SSPP common configuration */ #define _VIG_SBLK(scaler_ver) \ { \ - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ - .maxupscale = MAX_UPSCALE_RATIO, \ .scaler_blk = {.name = "scaler", \ .version = scaler_ver, \ .base = 0xa00, .len = 0xa0,}, \ @@ -288,8 +282,6 @@ static const u32 wb2_formats_rgb_yuv[] = { #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ { \ - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ - .maxupscale = MAX_UPSCALE_RATIO, \ .scaler_blk = {.name = "scaler", \ .version = scaler_ver, \ .base = 0xa00, .len = 0xa0,}, \ @@ -302,16 +294,12 @@ static const u32 wb2_formats_rgb_yuv[] = { #define _VIG_SBLK_NOSCALE() \ { \ - .maxdwnscale = SSPP_UNITY_SCALE, \ - .maxupscale = SSPP_UNITY_SCALE, \ .format_list = plane_formats, \ .num_formats = ARRAY_SIZE(plane_formats), \ } #define _DMA_SBLK() \ { \ - .maxdwnscale = SSPP_UNITY_SCALE, \ - .maxupscale = SSPP_UNITY_SCALE, \ .format_list = plane_formats, \ .num_formats = ARRAY_SIZE(plane_formats), \ } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 3f2646955ae0..bf86d643887d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -364,8 +364,6 @@ struct dpu_caps { /** * struct dpu_sspp_sub_blks : SSPP sub-blocks * common: Pointer to common configurations shared by sub blocks - * @maxdwnscale: max downscale ratio supported(without DECIMATION) - * @maxupscale: maxupscale ratio supported * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps * @qseed_ver: qseed version * @scaler_blk: @@ -375,8 +373,6 @@ struct dpu_caps { * @dpu_rotation_cfg: inline rotation configuration */ struct dpu_sspp_sub_blks { - u32 maxdwnscale; - u32 maxupscale; u32 max_per_pipe_bw; u32 qseed_ver; struct dpu_scaler_blk scaler_blk; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 325af392e6a2..115c1bd77bdd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -785,12 +785,15 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, return 0; } +#define MAX_UPSCALE_RATIO 20 +#define MAX_DOWNSCALE_RATIO 4 + static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); - int ret = 0, min_scale; + int ret = 0, min_scale, max_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; @@ -821,10 +824,17 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, pipe_hw_caps = pipe->sspp->cap; sblk = pipe->sspp->cap->sblk; - min_scale = FRAC_16_16(1, sblk->maxupscale); + if (sblk->scaler_blk.len) { + min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); + max_scale = MAX_DOWNSCALE_RATIO << 16; + } else { + min_scale = DRM_PLANE_NO_SCALING; + max_scale = DRM_PLANE_NO_SCALING; + } + ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, - sblk->maxdwnscale << 16, + max_scale, true, true); if (ret) { DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); From patchwork Wed Jun 26 21:46:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 807543 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30DCA194ADB for ; Wed, 26 Jun 2024 21:46:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438377; cv=none; b=b4hraaW84/cUUoiZUkdU57zjqo9utWCz/EYeV9g+2YsTFmDaTsiJzNWIW4n/I2xP5k/wsFk9RCbrqEgQ4jpNdU6x7x47ckna8EZ6wMg1C9f/oGygpWabHRivf0OemiqTJHZyWJuSer13UbrPZKEsBjQmNVloQYnt+njKnf0NLAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438377; c=relaxed/simple; bh=lFD7iY25uduQrISmYezTWzbetq+0s7Q3DnmHq0jujlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OeRCq1aL2bAWUa7obwtfFtHSWHUexWIYOD1KitrLGgdNKOIl09f2kSY9V9kkMmnPUHNUDPTf+9+LH7JwBlBZHTDmGVHq+QBUPXen5L/BagVl3L9MOrsKqF+Xwp+W4Vv7iSqIk/+EDgfQIr61gPnEYRhEOvFTgsQD2OgWwF5O0CQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=onJDWfJD; arc=none smtp.client-ip=209.85.208.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="onJDWfJD" Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2ec59193468so9020501fa.1 for ; Wed, 26 Jun 2024 14:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719438372; x=1720043172; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wCwITSOLHJdYGH/l/xlihLfKPyvCBWUXO5QlnX3YLVc=; b=onJDWfJD5yE6UDYPiq5DWFiQz6AKUUUXQT+o0Fx1nv8T96c15uH5Bgh+5NF1wTB6qH AxOjfCVujLUd8SujftBhxxdmw6ja+kxla8/rVv23kkfRtcE/0gPg0pyIgNc9ENuIroXo TKW3DF2PkImvtPaUHuF49ZPSIzWYMT91vmyvVQf0s3iwR9JcmVrjpZ0fZ3JVmQy/lkNh cCa6t8wxWd7YKIqwHNBnPr5zG6vja/1lWWrGAk+T5gwPDznEFNOtlDIvkZozwyejHf0j PvgSEa+fMDYmGZnKVBIHgxIHBCNUfrijJjm6rhPcqufjTnBoVPGRpy67/iKZYWJQVVxZ +7jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719438372; x=1720043172; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wCwITSOLHJdYGH/l/xlihLfKPyvCBWUXO5QlnX3YLVc=; b=B6Rs1eHT/fdhOr7rkJGoVhiWf9/IPXEz3VtiDymlAZi95tkCqw0dOT/8XgJW3SEmND oJ2NTJ9/v7liKVXWxZeLp1zH7J6CKxIff3CKdSgwCwhnoZaunbCmBwRH2PZU33AseZTI P65ap+NCXorZccp8Ww7Hb+VMKdPBHL4nUAMosnDJN+QfSrM0ep1Q3rr7KbngT5rIPzsA /fUQEVpq370CesyVaoAQDiXgjB8UmxV2lPpr0FIR8TzeHkyuaTkB403GyEcPjxF0VN+8 G/C6TGMyTqRvMob0nYDvMVCqp+LbZfjiCsj0arcfOEKuAtGAt/dUULk0o359A0TsiC5E cMjQ== X-Gm-Message-State: AOJu0Yw+ncnKBrhEGTKZ2P4iCRVR7Lfz5ybMHq3xWS8YLGnpnMoEda+n EaFhVEky33+lRLmrS/l/r9bAL8mYVbFnJX+mK/6JouuRj3IZQd4ASakBib0QZGw= X-Google-Smtp-Source: AGHT+IE8DpnOqJ/ChQfneZQxrWT9jg6t17SqP8ttL+UMM4dOVHNIK9InexUr0+5v8qlzHXG1XyQpSg== X-Received: by 2002:a2e:c52:0:b0:2ec:5172:f7b2 with SMTP id 38308e7fff4ca-2ee496192f1mr554021fa.2.1719438372450; Wed, 26 Jun 2024 14:46:12 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ee4a350d96sm23201fa.49.2024.06.26.14.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 14:46:11 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 27 Jun 2024 00:46:03 +0300 Subject: [PATCH v5 09/12] drm/msm/dpu: move rot90 checking to dpu_plane_atomic_check_pipe() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240627-dpu-virtual-wide-v5-9-5efb90cbb8be@linaro.org> References: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> In-Reply-To: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7305; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=lFD7iY25uduQrISmYezTWzbetq+0s7Q3DnmHq0jujlQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmfIwZKSlx7Y6RwCb75cVHPq3GyTdOv/Lb9GU5/ Xl2cLg8j+2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnyMGQAKCRCLPIo+Aiko 1QmTB/49+NwiwfAQBT4PPq4jOBJolFhZQZv84R6Shel9QeKkmR/GwBYkb9dTyP4SKn/pGBvSsbA cOXx/GWcXrmtcephuEBrg/0T0ViWXE7o0QPB25r1Yt9+bvRIWF+y9Thm0HqXf/TFIsSofqSblme 9lJqpXC/SFbpBrCz8Nv6yHnpAPDaElFLeriDnv8e4Ey2l9kBJhmjyz7biSFGJN3WjROC1te3kEA nL+tpcQsYva7Y6Zvg4C7tFU6EQlp4xVRjWHF+bOP6S7+ClrWgNVmLpnf97xmW4q33rz9BMEkV/f 08yKG7gr03FB6DEACw8eeG850CL9n8nHF0FhZ4SE7T26Qf+W X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move a call to dpu_plane_check_inline_rotation() to the dpu_plane_atomic_check_pipe() function, so that the rot90 constraints are checked for both pipes. Also move rotation field from struct dpu_plane_state to struct dpu_sw_pipe_cfg. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 55 +++++++++++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 -- 3 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 4a910b808687..fc54625ae5d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -142,10 +142,12 @@ struct dpu_hw_pixel_ext { * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. + * @rotation: simplified drm rotation hint */ struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; + unsigned int rotation; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 9b9fe28052ad..6ad160295341 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -527,8 +527,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, const struct msm_format *fmt, bool color_fill, - struct dpu_sw_pipe_cfg *pipe_cfg, - unsigned int rotation) + struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_hw_sspp *pipe_hw = pipe->sspp; const struct drm_format_info *info = drm_format_info(fmt->pixel_format); @@ -551,7 +550,7 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, dst_height, &scaler3_cfg, fmt, info->hsub, info->vsub, - rotation); + pipe_cfg->rotation); /* configure pixel extension based on scalar config */ _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, @@ -603,7 +602,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, if (pipe->sspp->ops.setup_rects) pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); - _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg); } /** @@ -704,12 +703,17 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane, } static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, - const struct dpu_sspp_sub_blks *sblk, - struct drm_rect src, const struct msm_format *fmt) + struct dpu_sw_pipe *pipe, + struct drm_rect src, + const struct msm_format *fmt) { + const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk; size_t num_formats; const u32 *supported_formats; + if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features)) + return -EINVAL; + if (!sblk->rotation_cfg) { DPU_ERROR("invalid rotation cfg\n"); return -EINVAL; @@ -739,6 +743,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, { uint32_t min_src_size; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); + int ret; min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; @@ -776,6 +781,12 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, return -EINVAL; } + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) { + ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt); + if (ret) + return ret; + } + /* max clk check */ if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); @@ -889,7 +900,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; uint32_t max_linewidth; - unsigned int rotation; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -913,6 +923,15 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |= DRM_MODE_ROTATE_90; + + pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, + supported_rotations); + r_pipe_cfg->rotation = pipe_cfg->rotation; + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) @@ -936,6 +955,7 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || + pipe_cfg->rotation & DRM_MODE_ROTATE_90 || MSM_FORMAT_IS_YUV(fmt)) { DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); @@ -959,23 +979,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, return ret; } - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; - - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) - supported_rotations |= DRM_MODE_ROTATE_90; - - rotation = drm_rotation_simplify(new_plane_state->rotation, - supported_rotations); - - if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && - (rotation & DRM_MODE_ROTATE_90)) { - ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); - if (ret) - return ret; - } - - pstate->rotation = rotation; - return 0; } @@ -1115,14 +1118,14 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, pipe_cfg); } - _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); + _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg); if (pipe->sspp->ops.setup_multirect) pipe->sspp->ops.setup_multirect( pipe); if (pipe->sspp->ops.setup_format) { - unsigned int rotation = pstate->rotation; + unsigned int rotation = pipe_cfg->rotation; src_flags = 0x0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index abd6b21a049b..a3ae45dc95d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -30,7 +30,6 @@ * @plane_fetch_bw: calculated BW per plane * @plane_clk: calculated clk per plane * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed - * @rotation: simplified drm rotation hint */ struct dpu_plane_state { struct drm_plane_state base; @@ -47,7 +46,6 @@ struct dpu_plane_state { u64 plane_clk; bool needs_dirtyfb; - unsigned int rotation; }; #define to_dpu_plane_state(x) \ From patchwork Wed Jun 26 21:46:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 807542 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 499C4194AF4 for ; Wed, 26 Jun 2024 21:46:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438377; cv=none; b=Q0EwD7qu4XemKPInDi6hdnc1ePpgavHFhkPjOI7+ILN9upfnRWfFJDxJDO2onO16+kRU+l7SyJ5ggLJ+ZeOHzJU4Gc+2gajlj0qoxv/WGdNWDwZnf6MibkIvsagpMEB59yjSknrDislWcvZyhqu2eWd10s6WGowfBuyxvm6V57w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719438377; c=relaxed/simple; bh=EHN34VJkW4Tsshf0z3nb48VHGRqnQtQh9hD7q2NKFyk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PNgUPY1KDk3I9AwZD70pP8q8OIGWwEOO4mhAWGg3I005PcI7J8/sdMeQLG8k0zyqJsySaWkwZzkq3Rgf4aRy9QMIgTYyBA/0sXl5viraK72FwVMog7REe0vJ7brXoH7yXNIooHDpjSQNjAqZRfsq9X9GmWVrfD4MiU5QNo7+JDs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dExnfx4C; arc=none smtp.client-ip=209.85.208.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dExnfx4C" Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2ec0f3b9cfeso86355801fa.0 for ; Wed, 26 Jun 2024 14:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719438373; x=1720043173; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6RUUv6QPzt7XzA46QfLVWzdO/kYhs4i+r+04SlOl4nE=; b=dExnfx4CDlxmCKdT8kxctKBmLBX6m9OXAcs6wDEPiVtEE4wPSX9vyBh9GzFM6taJsx Q7tLrwkc6Pvpuke/we+FPd6PcmhfTrhl8MltM84IH8wfjhlM1KrpRoPXUNdDKuQTf0wV dPkQqGgUlYFekTUv5QeMcWS3S/K46pGHElrFz02Ww8jk6IReoUz6JjmnRC9bgYMFGjG1 KhaAfDzTmOlvABdysV54F4hHQDcSX8PR1wVZRuOZQ9KvjBhbErVCmnVseBItnIlab4iw IJWJ6z3ZEoD+tYhQe1fK8db0ztK8wYnU0cuignd9wlFVE2QBcbtprKlY14cUJpihCRji t2yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719438373; x=1720043173; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6RUUv6QPzt7XzA46QfLVWzdO/kYhs4i+r+04SlOl4nE=; b=oBB4Reuk58bqG6p1NSkJTgw2OFX7RG+w30ds/2ia1CUW3zPE3bjoYp39ZKSlB/AWJq KEI72kqJ/qb5Y4qHK4fkMSMZyuPE+dfzAIdfUTSVyHmI+Fzp8zkMsxPfjMLiNt5NWJke RtRMf7OdYhQk/v7/Yhh1NQodi5G6cv+UZBI4ZuzLn1/N+QH8GlUcyFfCnhz7utdZInVE +ZBPrSM6V73mT56T92PczrJrly0BQklwxsaG4Tys3xKivB+uac9ozkXxTyVSks5MRlth 2+LBq4bsedHlxT6U8hgcPSIhYTaw7fZyEkf5RVBlRUFDp34uFofixXOng7UJKjlcsISc /+fw== X-Gm-Message-State: AOJu0YyTxf67PgDKze8SklAReBoL4vPGuUAf+4BZECIY4Pw3b30+0Fb5 3qUdjviMf02HkB0PiKLl+i5xeWRYIDO/vRHQ56icEaMnX8/gBBJBtQiga0PwQ4U= X-Google-Smtp-Source: AGHT+IFcYobwqjcwrUXn+MXupKiniSysaTFOXT74bVddR5hToi5ga/1eClag0WSAZb8PG98iBhjn4g== X-Received: by 2002:a2e:a310:0:b0:2ed:136c:4ce8 with SMTP id 38308e7fff4ca-2ed136c4d67mr23787221fa.6.1719438373397; Wed, 26 Jun 2024 14:46:13 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ee4a350d96sm23201fa.49.2024.06.26.14.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 14:46:12 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 27 Jun 2024 00:46:04 +0300 Subject: [PATCH v5 10/12] drm/msm/dpu: add support for virtual planes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240627-dpu-virtual-wide-v5-10-5efb90cbb8be@linaro.org> References: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> In-Reply-To: <20240627-dpu-virtual-wide-v5-0-5efb90cbb8be@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=21488; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=EHN34VJkW4Tsshf0z3nb48VHGRqnQtQh9hD7q2NKFyk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmfIwZo4CvonZQXrzLOu0YdEpkDyA5J76bfmtGe Gi5OHH4rauJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnyMGQAKCRCLPIo+Aiko 1T+YCACPMOvmWcA9N88hQO2mLh2elfaqhy2jTLIoYLTzFNcVzGCM+RNPLOtHfBI7BTSAuyZRcKZ Tc6Mzg69uOpO5JzyblBQFAS6bAIDgG6ft/M8TIgWgfGQBgR8MRdpXzNOoIbsy+Wuc4CMs77IRfj acNyBQ47+Y2LdgeR3qdNDD6ggfmqOCZXdB1nOCL+7zZE2K4bT34EQw8niSRInprtKyGEA3PBg+Q TitigqVPH8v11Lku0awO95803XaVFepUjyKFqeNqX+pLyAQ6JI1ThTIOfkZ0Q7RIhcEoDOy5k3j 0vFaEjZi2j4ztPU/vmzAsb2NzGpq/D+FaaD9crFjMYKWa25u X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Only several SSPP blocks support such features as YUV output or scaling, thus different DRM planes have different features. Properly utilizing all planes requires the attention of the compositor, who should prefer simpler planes to YUV-supporting ones. Otherwise it is very easy to end up in a situation when all featureful planes are already allocated for simple windows, leaving no spare plane for YUV playback. To solve this problem make all planes virtual. Each plane is registered as if it supports all possible features, but then at the runtime during the atomic_check phase the driver selects backing SSPP block for each plane. As the planes are attached to the CRTC and not the the encoder, the SSPP blocks are also allocated per CRTC ID (all other resources are currently allocated per encoder ID). This also matches the hardware requirement, where both rectangles of a single SSPP can only be used with the LM pair. Note, this does not provide support for using two different SSPP blocks for a single plane or using two rectangles of an SSPP to drive two planes. Each plane still gets its own SSPP and can utilize either a solo rectangle or both multirect rectangles depending on the resolution. Note #2: By default support for virtual planes is turned off and the driver still uses old code path with preallocated SSPP block for each plane. To enable virtual planes, pass 'msm.dpu_use_virtual_planes=1' kernel parameter. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 50 +++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 236 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 16 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 77 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 27 ++++ 7 files changed, 391 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9f2164782844..c438cf834320 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1168,6 +1168,49 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) return false; } +static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) +{ + int total_planes = crtc->dev->mode_config.num_total_plane; + struct drm_atomic_state *state = crtc_state->state; + struct dpu_global_state *global_state; + struct drm_plane_state **states; + struct drm_plane *plane; + int ret; + + global_state = dpu_kms_get_global_state(crtc_state->state); + if (IS_ERR(global_state)) + return PTR_ERR(global_state); + + dpu_rm_release_all_sspp(global_state, crtc); + + if (!crtc_state->enable) + return 0; + + states = kcalloc(total_planes, sizeof(*states), GFP_KERNEL); + if (!states) + return -ENOMEM; + + drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { + struct drm_plane_state *plane_state = + drm_atomic_get_plane_state(state, plane); + + if (IS_ERR(plane_state)) { + ret = PTR_ERR(plane_state); + goto done; + } + + states[plane_state->normalized_zpos] = plane_state; + } + + ret = dpu_assign_plane_resources(global_state, state, crtc, states, total_planes); + +done: + kfree(states); + return ret; + + return 0; +} + static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -1183,6 +1226,13 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); + if (dpu_use_virtual_planes && + (crtc_state->planes_changed || crtc_state->zpos_changed)) { + rc = dpu_crtc_reassign_planes(crtc, crtc_state); + if (rc < 0) + return rc; + } + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index d1e2143110f2..449fdc0d33dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -51,6 +51,9 @@ #define DPU_DEBUGFS_DIR "msm_dpu" #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" +bool dpu_use_virtual_planes = false; +module_param(dpu_use_virtual_planes, bool, 0); + static int dpu_kms_hw_init(struct msm_kms *kms); static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); @@ -814,8 +817,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) type, catalog->sspp[i].features, catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); - plane = dpu_plane_init(dev, catalog->sspp[i].id, type, - (1UL << max_crtc_count) - 1); + if (dpu_use_virtual_planes) + plane = dpu_plane_init_virtual(dev, type, (1UL << max_crtc_count) - 1); + else + plane = dpu_plane_init(dev, catalog->sspp[i].id, type, + (1UL << max_crtc_count) - 1); if (IS_ERR(plane)) { DPU_ERROR("dpu_plane_init failed\n"); ret = PTR_ERR(plane); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index e2adc937ea63..195257660057 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -64,6 +64,8 @@ #define ktime_compare_safe(A, B) \ ktime_compare(ktime_sub((A), (B)), ktime_set(0, 0)) +extern bool dpu_use_virtual_planes; + struct dpu_kms { struct msm_kms base; struct drm_device *dev; @@ -138,6 +140,8 @@ struct dpu_global_state { uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; uint32_t cdm_to_enc_id; + + uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 6ad160295341..c72c65bf55e1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -876,7 +876,7 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, drm_rect_rotate_inv(&pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); - if (r_pipe_cfg->src_rect.x1 != 0) + if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) drm_rect_rotate_inv(&r_pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); @@ -999,8 +999,13 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp = NULL; + if (pdpu->pipe != SSPP_NONE) { + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp = NULL; + } + + if (!pipe->sspp) + return -EINVAL; ret = dpu_plane_atomic_check_nopipe(plane, new_plane_state, crtc_state); if (ret) @@ -1017,6 +1022,112 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return dpu_plane_atomic_check_pipes(plane, state, crtc_state); } +static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *plane_state = + drm_atomic_get_plane_state(state, plane); + struct drm_plane_state *old_plane_state = + drm_atomic_get_old_plane_state(state, plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); + struct drm_crtc_state *crtc_state; + int ret; + + if (plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + ret = dpu_plane_atomic_check_nopipe(plane, plane_state, crtc_state); + if (ret) + return ret; + + if (!plane_state->visible) { + /* + * resources are freed by dpu_crtc_assign_plane_resources(), + * but clean them here. + */ + pstate->pipe.sspp = NULL; + pstate->r_pipe.sspp = NULL; + + return 0; + } + + /* force resource reallocation if the format of FB has changed */ + if (!old_plane_state || !old_plane_state->fb || + msm_framebuffer_format(old_plane_state->fb) != + msm_framebuffer_format(plane_state->fb)) + crtc_state->planes_changed = true; + + return 0; +} + +static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, + struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_plane_state *plane_state) +{ + const struct drm_crtc_state *crtc_state = NULL; + struct drm_plane *plane = plane_state->plane; + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + struct dpu_rm_sspp_requirements reqs; + struct dpu_plane_state *pstate; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe *r_pipe; + const struct msm_format *fmt; + + if (plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + pstate = to_dpu_plane_state(plane_state); + pipe = &pstate->pipe; + r_pipe = &pstate->r_pipe; + + pipe->sspp = NULL; + r_pipe->sspp = NULL; + + if (!plane_state->fb) + return -EINVAL; + + fmt = msm_framebuffer_format(plane_state->fb); + reqs.yuv = MSM_FORMAT_IS_YUV(fmt); + reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) || + (plane_state->src_h >> 16 != plane_state->crtc_h); + + reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation); + + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); + if (!pipe->sspp) + return -ENODEV; + + return dpu_plane_atomic_check_pipes(plane, state, crtc_state); +} + +int dpu_assign_plane_resources(struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_plane_state **states, + unsigned int num_planes) +{ + unsigned int i; + int ret; + + for (i = 0; i < num_planes; i++) { + struct drm_plane_state *plane_state = states[i]; + + if (!plane_state || + !plane_state->visible) + continue; + + ret = dpu_plane_virtual_assign_resources(crtc, global_state, + state, plane_state); + if (ret) + break; + } + + return ret; +} + static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) { const struct msm_format *format = @@ -1337,12 +1448,14 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=%s\n", - dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); - drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); + if (pipe->sspp) { + drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[0]=%s\n", + dpu_get_multirect_index(pipe->multirect_index)); + drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); + } if (r_pipe->sspp) { drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); @@ -1431,31 +1544,29 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { .atomic_update = dpu_plane_atomic_update, }; +static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = { + .prepare_fb = dpu_plane_prepare_fb, + .cleanup_fb = dpu_plane_cleanup_fb, + .atomic_check = dpu_plane_virtual_atomic_check, + .atomic_update = dpu_plane_atomic_update, +}; + /* initialize plane */ -struct drm_plane *dpu_plane_init(struct drm_device *dev, - uint32_t pipe, enum drm_plane_type type, - unsigned long possible_crtcs) +static struct drm_plane *dpu_plane_init_common(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs, + bool inline_rotation, + const uint32_t *format_list, + uint32_t num_formats, + enum dpu_sspp pipe) { struct drm_plane *plane = NULL; - const uint32_t *format_list; struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); - struct dpu_hw_sspp *pipe_hw; - uint32_t num_formats; uint32_t supported_rotations; int ret; - /* initialize underlying h/w driver */ - pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); - if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { - DPU_ERROR("[%u]SSPP is invalid\n", pipe); - return ERR_PTR(-EINVAL); - } - - format_list = pipe_hw->cap->sblk->format_list; - num_formats = pipe_hw->cap->sblk->num_formats; - pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base, 0xff, &dpu_plane_funcs, format_list, num_formats, @@ -1481,7 +1592,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; - if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + if (inline_rotation) supported_rotations |= DRM_MODE_ROTATE_MASK; drm_plane_create_rotation_property(plane, @@ -1489,10 +1600,81 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, drm_plane_enable_fb_damage_clips(plane); - /* success! finalize initialization */ + DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, + pipe, plane->base.id); + return plane; +} + +struct drm_plane *dpu_plane_init(struct drm_device *dev, + uint32_t pipe, enum drm_plane_type type, + unsigned long possible_crtcs) +{ + struct drm_plane *plane = NULL; + struct msm_drm_private *priv = dev->dev_private; + struct dpu_kms *kms = to_dpu_kms(priv->kms); + struct dpu_hw_sspp *pipe_hw; + + /* initialize underlying h/w driver */ + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { + DPU_ERROR("[%u]SSPP is invalid\n", pipe); + return ERR_PTR(-EINVAL); + } + + + plane = dpu_plane_init_common(dev, type, possible_crtcs, + pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION), + pipe_hw->cap->sblk->format_list, + pipe_hw->cap->sblk->num_formats, + pipe); + if (IS_ERR(plane)) + return plane; + drm_plane_helper_add(plane, &dpu_plane_helper_funcs); DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, pipe, plane->base.id); + + return plane; +} + +struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs) +{ + struct drm_plane *plane = NULL; + struct msm_drm_private *priv = dev->dev_private; + struct dpu_kms *kms = to_dpu_kms(priv->kms); + bool has_inline_rotation = false; + const u32 *format_list = NULL; + u32 num_formats = 0; + int i; + + /* Determine the largest configuration that we can implement */ + for (i = 0; i < kms->catalog->sspp_count; i++) { + const struct dpu_sspp_cfg *cfg = &kms->catalog->sspp[i]; + + if (test_bit(DPU_SSPP_INLINE_ROTATION, &cfg->features)) + has_inline_rotation = true; + + if (!format_list || + cfg->sblk->csc_blk.len) { + format_list = cfg->sblk->format_list; + num_formats = cfg->sblk->num_formats; + } + } + + plane = dpu_plane_init_common(dev, type, possible_crtcs, + has_inline_rotation, + format_list, + num_formats, + SSPP_NONE); + if (IS_ERR(plane)) + return plane; + + drm_plane_helper_add(plane, &dpu_plane_virtual_helper_funcs); + + DPU_DEBUG("%s created virtual id:%u\n", plane->name, plane->base.id); + return plane; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index a3ae45dc95d0..e225d5baceb0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -75,6 +75,16 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, unsigned long possible_crtcs); +/** + * dpu_plane_init_virtual - create new dpu virtualized plane + * @dev: Pointer to DRM device + * @type: Plane type - PRIMARY/OVERLAY/CURSOR + * @possible_crtcs: bitmask of crtc that can be attached to the given pipe + */ +struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs); + /** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object @@ -91,4 +101,10 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable); static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) {} #endif +int dpu_assign_plane_resources(struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_plane_state **states, + unsigned int num_planes); + #endif /* _DPU_PLANE_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 44938ba7a2b7..dbf1f7229e45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -694,6 +694,83 @@ int dpu_rm_reserve( return ret; } +struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs) +{ + uint32_t crtc_id = crtc->base.id; + unsigned int weight, best_weight = UINT_MAX; + struct dpu_hw_sspp *hw_sspp; + unsigned long mask = 0; + int i, best_idx = -1; + + /* + * Don't take cursor feature into consideration until there is proper support for SSPP_CURSORn. + */ + mask |= BIT(DPU_SSPP_CURSOR); + + if (reqs->scale) + mask |= BIT(DPU_SSPP_SCALER_RGB) | + BIT(DPU_SSPP_SCALER_QSEED2) | + BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE); + + if (reqs->yuv) + mask |= BIT(DPU_SSPP_CSC) | + BIT(DPU_SSPP_CSC_10BIT); + + if (reqs->rot90) + mask |= BIT(DPU_SSPP_INLINE_ROTATION); + + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++) { + if (!rm->hw_sspp[i]) + continue; + + if (global_state->sspp_to_crtc_id[i]) + continue; + + hw_sspp = rm->hw_sspp[i]; + + /* skip incompatible planes */ + if (reqs->scale && !hw_sspp->cap->sblk->scaler_blk.len) + continue; + + if (reqs->yuv && !hw_sspp->cap->sblk->csc_blk.len) + continue; + + if (reqs->rot90 && !(hw_sspp->cap->features & DPU_SSPP_INLINE_ROTATION)) + continue; + + /* + * For non-yuv, non-scaled planes prefer simple (DMA or RGB) + * plane, falling back to VIG only if there are no such planes. + * + * This way we'd leave VIG sspps to be later used for YUV formats. + */ + weight = hweight64(hw_sspp->cap->features & ~mask); + if (weight < best_weight) { + best_weight = weight; + best_idx = i; + } + } + + if (best_idx < 0) + return NULL; + + global_state->sspp_to_crtc_id[best_idx] = crtc_id; + + return rm->hw_sspp[best_idx]; +} + +void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, + struct drm_crtc *crtc) +{ + uint32_t crtc_id = crtc->base.id; + + _dpu_rm_clear_mapping(global_state->sspp_to_crtc_id, + ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); +} + int dpu_rm_get_assigned_resources(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index e63db8ace6b9..6edff89fe83a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -37,6 +37,12 @@ struct dpu_rm { struct dpu_hw_blk *cdm_blk; }; +struct dpu_rm_sspp_requirements { + bool yuv; + bool scale; + bool rot90; +}; + /** * dpu_rm_init - Read hardware catalog and create reservation tracking objects * for all HW blocks. @@ -82,6 +88,27 @@ int dpu_rm_reserve(struct dpu_rm *rm, void dpu_rm_release(struct dpu_global_state *global_state, struct drm_encoder *enc); +/** + * dpu_rm_reserve_sspp - Reserve the required SSPP for the provided CRTC + * @rm: DPU Resource Manager handle + * @global_state: private global state + * @crtc: DRM CRTC handle + * @reqs: SSPP required features + */ +struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs); + +/** + * dpu_rm_release_all_sspp - Given the CRTC, release all SSPP + * blocks previously reserved for that use case. + * @rm: DPU Resource Manager handle + * @crtc: DRM CRTC handle + */ +void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, + struct drm_crtc *crtc); + /** * Get hw resources of the given type that are assigned to this encoder. */