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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(82310400023)(1800799021)(36860700010)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 16:51:23.7843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05dacc13-d042-46c5-dc1e-08dc9212627d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6734 There are some other drivers also need to use the MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move the definition to a common header file to allow other driver to use it. No intentional functional impact. Suggested-by: Gautham Ranjal Shenoy Signed-off-by: Perry Yuan Acked-by: Rafael J. Wysocki Acked-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/cpufreq/acpi-cpufreq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e022e6eb766c..384739d592af 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -781,6 +781,8 @@ #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 +#define MSR_K7_HWCR_CPB_DIS_BIT 25 +#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) /* K6 MSRs */ #define MSR_K6_WHCR 0xc0000082 diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 37f1cdf46d29..2fc82831bddd 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -50,8 +50,6 @@ enum { #define AMD_MSR_RANGE (0x7) #define HYGON_MSR_RANGE (0x7) -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - struct acpi_cpufreq_data { unsigned int resume; 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This simplifies the code and improves readability by using a standard kernel function for boolean string conversion. Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan --- drivers/cpufreq/cpufreq.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index a45aac17c20f..1fdabb660231 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -614,10 +614,9 @@ static ssize_t show_boost(struct kobject *kobj, static ssize_t store_boost(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { - int ret, enable; + bool enable; - ret = sscanf(buf, "%d", &enable); - if (ret != 1 || enable < 0 || enable > 1) + if (kstrtobool(buf, &enable)) return -EINVAL; if (cpufreq_boost_trigger_state(enable)) { @@ -641,10 +640,10 @@ static ssize_t show_local_boost(struct cpufreq_policy *policy, char *buf) static ssize_t store_local_boost(struct cpufreq_policy *policy, const char *buf, size_t count) { - int ret, enable; + int ret; + bool enable; - ret = kstrtoint(buf, 10, &enable); - if (ret || enable < 0 || enable > 1) + if (kstrtobool(buf, &enable)) return -EINVAL; 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This initialization is required before calling the set_boost interface for each CPU. The init_boost callback will set up and synchronize each CPU's current boost state before invoking the set_boost function. Without this step, the boost state may be inconsistent across CPUs. Signed-off-by: Perry Yuan --- drivers/cpufreq/cpufreq.c | 14 ++++++++++++-- include/linux/cpufreq.h | 2 ++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 1fdabb660231..0c99d2dfdb53 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -1429,8 +1429,18 @@ static int cpufreq_online(unsigned int cpu) goto out_free_policy; } - /* Let the per-policy boost flag mirror the cpufreq_driver boost during init */ - policy->boost_enabled = cpufreq_boost_enabled() && policy_has_boost_freq(policy); + /* init boost state to prepare set_boost callback for each CPU */ + if (cpufreq_driver->init_boost) { + ret = cpufreq_driver->init_boost(policy); + if (ret) { + pr_debug("%s: %d: boost initialization failed\n", __func__, + __LINE__); + goto out_offline_policy; + } + } else { + /* Let the per-policy boost flag mirror the cpufreq_driver boost during init */ + policy->boost_enabled = cpufreq_boost_enabled() && policy_has_boost_freq(policy); + } /* * The initialization has succeeded and the policy is online. diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 20f7e98ee8af..0698c0292d8f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -409,6 +409,8 @@ struct cpufreq_driver { bool boost_enabled; int (*set_boost)(struct cpufreq_policy *policy, int state); + /* initialize boost state to be consistent before calling set_boost */ + int (*init_boost)(struct cpufreq_policy *policy); /* * Set by drivers that want to register with the energy model after the * policy is properly initialized, but before the governor is started. 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(1800799021)(36860700010)(82310400023)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 16:51:31.0657 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c8b2807-b595-4afa-e1a4-08dc921266d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7206 From: Perry Yuan The "Core Performance Boost (CPB) feature, when enabled in the BIOS, allows the OS to control the highest performance for each individual core. The active, passive and the guided modes of the amd-pstate driver do support controlling the core frequency boost when this BIOS feature is enabled. Additionally, the amd-pstate driver provides a sysfs interface allowing the user to activate/deactive this core performance boost featur at runtime. Add an amd_pstate_global_params object to record whether CPB is enabled in the BIOS, and if it has been activated by the user. Reported-by: Artem S. Tashkinov" Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 65 ++++++++++++++++++++++++++++++------ drivers/cpufreq/amd-pstate.h | 13 ++++++++ 2 files changed, 67 insertions(+), 11 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c418f2bb5ced..d3e7f9cfa5c8 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -94,6 +94,10 @@ static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +/* export the amd_pstate_global_params for unit test */ +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -686,7 +690,7 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) if (!cpudata->boost_supported) { pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; + return -ENOTSUPP; } if (state) @@ -704,18 +708,42 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) return 0; } -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) { - u32 highest_perf, nominal_perf; + u64 boost_val; + int ret = -1; - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); + /* + * If platform has no CPB support or disble it, initialize current driver + * boost_enabled state to be false, it is not an error for cpufreq core to handle. + */ + if (!cpu_feature_enabled(X86_FEATURE_CPB)) { + pr_debug_once("Boost CPB capabilities not present in the processor\n"); + ret = 0; + goto exit_err; + } - if (highest_perf <= nominal_perf) - return; + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); + ret = -EIO; + goto exit_err; + } + + amd_pstate_global_params.cpb_supported = !(boost_val & MSR_K7_HWCR_CPB_DIS); + if (amd_pstate_global_params.cpb_supported) { + current_pstate_driver->boost_enabled = true; + cpudata->boost_supported = true; + } + + amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; + return 0; - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; +exit_err: + cpudata->boost_supported = false; + current_pstate_driver->boost_enabled = false; + amd_pstate_global_params.cpb_boost = false; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -1005,7 +1033,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1387,6 +1414,21 @@ static bool amd_pstate_acpi_pm_profile_undefined(void) return false; } +static int amd_pstate_init_boost(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int ret; + + /* initialize cpu cores boot state */ + ret = amd_pstate_init_boost_support(cpudata); + if (ret) + return ret; + + policy->boost_enabled = READ_ONCE(cpudata->boost_supported); + + return 0; +} + static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, ret; @@ -1456,7 +1498,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; @@ -1701,6 +1742,7 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, + .init_boost = amd_pstate_init_boost, .set_boost = amd_pstate_set_boost, .update_limits = amd_pstate_update_limits, .name = "amd-pstate", @@ -1718,6 +1760,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, .update_limits = amd_pstate_update_limits, + .init_boost = amd_pstate_init_boost, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index f80b33fa5d43..133042370a8f 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -102,4 +102,17 @@ struct amd_cpudata { s16 epp_default; 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Fri, 21 Jun 2024 11:51:30 -0500 From: Perry Yuan To: , , , CC: , , , , , Subject: [PATCH v13 5/9] cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control Date: Sat, 22 Jun 2024 00:51:00 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F6:EE_|MW6PR12MB8663:EE_ X-MS-Office365-Filtering-Correlation-Id: ce25c3fe-b93c-4d3c-f3b0-08dc9212688d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|1800799021|82310400023|36860700010|376011; X-Microsoft-Antispam-Message-Info: eyRITpS9lq/aXFmSbokGNIWxKKaOxLMDWHWImzbwZmYJLykbFk6kx+mncdIkxULXHnpzC8cVMlImh3j4hSDuG1w/AuhcyXWSn52JD2s58W6NjaF+JscjrL4d4gBt+piqy7hT9micOSE2HRJ2WlwqA9HMUrI6v4Ykus8bwGlRGjPseedNJksB92ngm1Xxw+zUaAc2JwpFCbrrKhOO/i2PX8ujD6s2CzhcPDqnfm9a0VGeyMM9L3J3iFplvFt/pYww8kdGgMK59I12aEvNx9CrCUs0C9DNDXc3xzOW1egHrTmpL0NRdqqLYTcm+UXloDBgZjRMTyEzrEan0q8zWAtwx+errgL2zIDow1eizIeD4RdQqevK+1REIUvV5wLahOF0QX60b3JP+QYmzO3jZtNcG7m1HfundQbltCWaCpxKlgA+lX5iuqltUcmpNv1sfOj/50YcWr2eIhzXudVBHV7VHv+R2G6oF/yRpvIc0Na9Vt6ngUW3YR1pLbsQ71zJG51hbsrRgq3sFfKZCstSjqR1s3Bh9GtVt+4YOdMzOEvk+728Wbq7CbNToOEnNgcMLgfsdunNAJgTRLT0sgZxpHjNdJXQSdD6Ins3GPX8DHyM3vqqTwFmiorio8XNxy8RaR12sub/svRkG++0le+r2BoTKF31OjcVVC6sbISFWziTfZv13Pm8mgXWtNXCGhs6JdI6HTGBaGaA1s9naaocgrZaE/khM74UKu64nTv9W3ASisjyRYTX9r/FqIR1NSP1VW1HhXs/9TM4gMwPIIBhog0hxDmxuWUI7ZIpHPhLwtU4NP5WtxIwRLGiPn8XvT3HMWS+3/UskWHiCAdjTMSR6vdw/du4KIzqbqIDejHiAEbCk40rwiT7t/HECIBMohjtOHl+pdQ+xJqFg4X7GUlW4CbErUPy1n1p6KPJ9GB7/JMwn3qFGFT9RW1W6GvTE65lrhpKEgBqbthoWUNA7eUjZ2pro8XlRP9IiLyZEyc4H1r6CZEajoDsw4wFjnkkgVIKqbDlVkRt4PeJhIRclTbyMyE0jkQ4ps1u/vkhs0hm/aAhHiFrFQIeJq7SaZ1NXR5fSEPUtoul+acXnx6QjIZj8YlJAtrz6v77QHY64KI8ocOqy0jlZsvqQ/B5/VXTdaEkp0+xQBvvPbnywCV6GW2jetbzY08sNBvL9i/8ZJV0f78+sjjFHtAVl4wmAjjB7yj4i/Wm2KJIbBfiZuB8YaWJPUCZ++HbU+mh7fJHH9+mIrFDTXP3bDxyKszMSnQI+Tmcba3Cc7XY0oPbjFnBAn9/CVm5WUGZlKT9g1bBT9nnahzjXKU1X2wb+8ULhMUp/4fQdcx5SO9ddUJjctc2cTE5n3TN+vuZK2Ii91srxfeuIGrHlx8= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(1800799021)(82310400023)(36860700010)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 16:51:33.9561 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce25c3fe-b93c-4d3c-f3b0-08dc9212688d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8663 From: Perry Yuan With this new sysfs entry `cpb_boost` created, user can change CPU boost state dynamically under `active`, `guided` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changes. Check current boost state: $ cat /sys/devices/system/cpu/amd_pstate/cpb_boost enabled or $ cat /sys/devices/system/cpu/amd_pstate/cpb_boost disabled Disable CPU boost sudo bash -c "echo "disabled" > /sys/devices/system/cpu/amd_pstate/cpb_boost" Enable CPU boost sudo bash -c "echo "enabled" > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate-ut.c | 2 +- drivers/cpufreq/amd-pstate.c | 129 +++++++++++++++++++++++++++++++- drivers/cpufreq/amd-pstate.h | 1 + 3 files changed, 130 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index fc275d41d51e..b528f198f4c3 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -227,7 +227,7 @@ static void amd_pstate_ut_check_freq(u32 index) goto skip_test; } - if (cpudata->boost_supported) { + if (amd_pstate_global_params.cpb_boost) { if ((policy->max == cpudata->max_freq) || (policy->max == cpudata->nominal_freq)) amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS; diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d3e7f9cfa5c8..6710b3c28cda 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -97,6 +97,7 @@ static struct quirk_entry *quirks; /* export the amd_pstate_global_params for unit test */ struct amd_pstate_global_params amd_pstate_global_params; EXPORT_SYMBOL_GPL(amd_pstate_global_params); +static int amd_pstate_cpu_boost(int cpu, bool state); /* * AMD Energy Preference Performance (EPP) @@ -139,6 +140,16 @@ static unsigned int epp_values[] = { [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE, }; +enum CPB_STATE_INDEX { + CPB_STATE_DISABLED = 0, + CPB_STATE_ENABLED = 1, +}; + +static const char * const cpb_state[] = { + [CPB_STATE_DISABLED] = "disabled", + [CPB_STATE_ENABLED] = "enabled", +}; + typedef int (*cppc_mode_transition_fn)(int); static struct quirk_entry quirk_amd_7k62 = { @@ -734,6 +745,7 @@ static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) if (amd_pstate_global_params.cpb_supported) { current_pstate_driver->boost_enabled = true; cpudata->boost_supported = true; + cpudata->boost_state = true; } amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; @@ -741,6 +753,7 @@ static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) exit_err: cpudata->boost_supported = false; + cpudata->boost_state = false; current_pstate_driver->boost_enabled = false; amd_pstate_global_params.cpb_boost = false; return ret; @@ -1352,6 +1365,118 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } +static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on) +{ + struct amd_cpudata *cpudata = policy->driver_data; + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf, nominal_freq, max_freq; + int ret; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + nominal_freq = READ_ONCE(cpudata->nominal_freq); + max_freq = READ_ONCE(cpudata->max_freq); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_perf(cpudata->cpu, &perf_ctrls); + if (ret) { + cpufreq_cpu_release(policy); + pr_debug("Failed to set max perf on CPU:%d. ret:%d\n", + cpudata->cpu, ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq = max_freq; + else + policy->cpuinfo.max_freq = nominal_freq * 1000; + + policy->max = policy->cpuinfo.max_freq; + + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq); + if (ret < 0) + pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu); + } + + return ret < 0 ? ret : 0; +} + +static int amd_pstate_cpu_boost(int cpu, bool state) +{ + int ret; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + if (!policy) { + pr_err("policy is NULL\n"); + ret = -ENODATA; + goto err_exit; + } + + ret = amd_pstate_cpu_boost_update(policy, state); + refresh_frequency_limits(policy); + WRITE_ONCE(cpudata->boost_state, state); + policy->boost_enabled = state; + +err_exit: + cpufreq_cpu_put(policy); + return ret < 0 ? ret : 0; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + bool cpb_idx; + + cpb_idx = amd_pstate_global_params.cpb_boost; + + return sysfs_emit(buf, "%s\n", cpb_state[cpb_idx]); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu, cpb_idx; + + if (!amd_pstate_global_params.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + cpb_idx = sysfs_match_string(cpb_state, buf); + if (cpb_idx < 0) + return -EINVAL; + + new_state = cpb_idx; + + mutex_lock(&amd_pstate_driver_lock); + for_each_present_cpu(cpu) { + ret = amd_pstate_cpu_boost(cpu, new_state); + if (ret < 0) { + pr_warn("failed to update cpu boost for CPU%d (%zd)\n", cpu, ret); + goto err_exit; + } + } + amd_pstate_global_params.cpb_boost = !!new_state; + +err_exit: + mutex_unlock(&amd_pstate_driver_lock); + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1362,6 +1487,7 @@ cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); +static DEVICE_ATTR_RW(cpb_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1386,6 +1512,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, &dev_attr_prefcore.attr, + &dev_attr_cpb_boost.attr, NULL }; @@ -1424,7 +1551,7 @@ static int amd_pstate_init_boost(struct cpufreq_policy *policy) if (ret) return ret; - policy->boost_enabled = READ_ONCE(cpudata->boost_supported); + policy->boost_enabled = READ_ONCE(cpudata->boost_state); return 0; } diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index 133042370a8f..fb240a870289 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -100,6 +100,7 @@ struct amd_cpudata { u64 cppc_cap1_cached; bool suspended; s16 epp_default; + bool boost_state; }; /** From patchwork Fri Jun 21 16:51:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 806522 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2062.outbound.protection.outlook.com [40.107.237.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4428D174EC6; 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Fri, 21 Jun 2024 11:51:33 -0500 From: Perry Yuan To: , , , CC: , , , , , Subject: [PATCH v13 6/9] cpufreq: amd-pstate: Add set_boost callback for active mode Date: Sat, 22 Jun 2024 00:51:01 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F5:EE_|IA1PR12MB6532:EE_ X-MS-Office365-Filtering-Correlation-Id: e12fb8d9-9d81-46df-ec5d-08dc92126a3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|82310400023|1800799021|376011|36860700010; X-Microsoft-Antispam-Message-Info: pRocTqHtyS84QwvxOi4WNka16phuUU2xR+eRNb5IgNMUnnD2mhDel7y1qpWYgSRrN50gAY/P3dpTEtHKql4o46dgoLIAHbXYBsA4fdo4bYvA0qpu1/OOb1qAu7XRETD5PpALN+eVFDw43gfSdAkPsZPbdEDkZCYCzFR6jeiok8k0uFi5v+eZp7AnpCIOBnrNGi2aF6RigyJ/ZD5il46p72lW1khSXOC/f+wZwJuRHb8ZdXqYw8mCwYYx3/QU5x8Pi88iAVmlhyQKS04jrh8OwGbtuhjIYrnI9e5OupPyFI0TO3vaFD9+oxTYGGQaKS5CfUWeAZBzhyN8k6xxm9+rFi6kjLOwDY/sk+R5VJPzdcamg/fwJ6QN4tMEWmEkgekh89D/IT0JjdtO8uD8Dkg3gw00C2AiHOOoqCr66WMnYTCIlKaAMjkCcdrRnnE88Cx9sFzMrLhTQfQWYGyAIixalb8QYdMuVSAUPbbHg02t0fJgPJsGCD8T+kZ0XNdkaP68kDsTzEWAkNOAkiPZe8Z2VslGP5ik4C6pitd7hxGXExzd3o1s62ffKuygwrewCAPF+wiIjQ8CTTAihemy0KOQ6r8cnUO5W4uxBPVOu14s1aBe/LKvC1mcMtZ8VPyhJgFMVKIUOQujCprLRoYGRY51XvEVJBCrQDDzedznNSOlrKNgldRVWf1ECyFDV5LF4Yw7dzMuHLrHguURbMp/EdFWCKx5FUGaUMw1cgbpMwor49VzWndKHkmt87tlMHTvLGoK7es4oKevxxDEOVA3PM6eCG75X67oDOjZegRpKTRdqx1AOzBOdxjaBAqkMXJF9Lg8M+RaU0J1OZZTDoC9wFMW29oG86yTI6WhOrBGaIq9iJnXyNUVLElS5Fd/IxNlqQlFj39ECE/fg49NPZhBUQk0wF7/nXGpCFbM7bvvHraQ9imz0Uum35iuRAr2WxqNlMPlXIeKNS2CYtPKLZ5+Ft28yzLnKYkPPFPDUJPW5UXw9LAIwe4gYTZUz02339vaH4/UU/aLDRfqhkU2SLXJDOah+oyH42m758AjSUzOmMnso6juOPVfFwdm9ZZ49/GoH+NxvOS0GE3YEByxnuvqvh+PFrbyE4QMb3plW68BoM5nfgdByNzVDFF/Dh/VtgbcxSXzoKKeQdYP0D5h0FhefGobtnVxxdOP30kA77kahupoA5+9r5eYaeT1ZGCUtb9pfPLhU2BAtztxXP8wYl04DK2P6BDUCDeBqb/cp8Mi14wrN9MgA8E5J5ecn2JvRvLSxVnbF8hLXea4W2aDp5rxVXUjc8xBNIGoO5WUBLo/xx+E1EeUXXDGu5d5gLBkvYWLDaVoXy7ZW0Rck1CpsVB7dZmJo2fSyAk5MvwfPbV7ml3arrnDTLfM0Kg+axBGQwY8jn+uvlBi8gX++TBY8WVWZe2CpQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(82310400023)(1800799021)(376011)(36860700010); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 16:51:36.7805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e12fb8d9-9d81-46df-ec5d-08dc92126a3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6532 Add support for the set_boost callback in the active mode driver to enable boost control via the cpufreq core. This ensures a consistent boost control interface across all pstate modes, including passive mode, guided mode, and active mode. With this addition, all three pstate modes can support the same boost control interface with unique interface and global CPB control. Each CPU also supports individual boost control, allowing global CPB to change all cores' boost states simultaneously. Specific CPUs can update their boost states separately, ensuring all cores' boost states are synchronized. Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Acked-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6710b3c28cda..02767230524e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -703,20 +703,11 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) pr_err("Boost mode is not supported by this processor or SBIOS\n"); return -ENOTSUPP; } + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_cpu_boost(policy->cpu, state); + mutex_unlock(&amd_pstate_driver_lock); - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq * 1000; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) - return ret; - - return 0; + return ret < 0 ? ret : 0; } static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) @@ -1888,6 +1879,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .resume = amd_pstate_epp_resume, .update_limits = amd_pstate_update_limits, .init_boost = amd_pstate_init_boost, + .set_boost = amd_pstate_set_boost, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(1800799021)(376011)(36860700010)(82310400023); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 16:51:42.8587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a887171-5d66-45c2-c1c6-08dc92126dde X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8317 From: Perry Yuan When Core Performance Boost is disabled by the user, the CPPC_REQ.max_perf should not exceed the nominal_perf since by definition the frequencies between nominal_perf and the highest_perf are in the boost range. Fix this in amd_pstate_update() Acked-by: Huang Rui Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 02767230524e..05e80d2f8803 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -529,6 +529,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, unsigned long max_freq; struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu); u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, @@ -551,6 +552,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!amd_pstate_global_params.cpb_boost) + max_perf = min_t(unsigned long, nominal_perf, max_perf); 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(82310400023)(1800799021)(36860700010)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 16:51:43.7024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9ff4a14-cbfe-42ae-809d-08dc92126e5f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7356 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- Documentation/admin-guide/pm/amd-pstate.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index f5ee81419a93..dc1b10d7dd09 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -440,6 +440,23 @@ control its functionality at the system level. They are located in the This attribute is read-only to check the state of preferred core set by the kernel parameter. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this attribute file which allows + user to change all cores frequency boosting state. It supports all amd-pstate modes. + + States of the driver "/sys/devices/system/cpu/amd_pstate/cpb_boost" + "disabled" Core Performance Boosting Disabled. + "enabled" Core Performance Boosting Enabled. + + To enable core performance boost: + # echo "enabled" > /sys/devices/system/cpu/amd_pstate/cpb_boost + + To disable core performance boost: + # echo "disabled" > /sys/devices/system/cpu/amd_pstate/cpb_boost + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Fri Jun 21 16:51:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 806521 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2058.outbound.protection.outlook.com [40.107.244.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F25FD168491; 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Fri, 21 Jun 2024 11:51:42 -0500 From: Perry Yuan To: , , , CC: , , , , , Subject: [PATCH v13 9/9] Documentation: cpufreq: amd-pstate: update doc for Per CPU boost control method Date: Sat, 22 Jun 2024 00:51:04 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F5:EE_|PH8PR12MB6889:EE_ X-MS-Office365-Filtering-Correlation-Id: a4858824-2278-4999-af2d-08dc92126f71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|1800799021|82310400023|376011|36860700010; X-Microsoft-Antispam-Message-Info: QlGbI/e+NAqndc3EGidBpxmRsoJX7zNVfRIuYxhVkPKIBehGIWjcX3gGU99m9s+sFAZLW6RknWFpr+Cq03G3Jc6nrTIyq9TkqLNPtzslYM1+Do1/54Nm0ryAukj9Icc1iPbF5UZNnqTUus/pY8UvBxKiU1jwRAGuF0t92hQ9DzYf3ODlVT4/N8NQkbAxMQRgigadAuDyp0WPZodzsq3Ma0uF1ZSSdzgSBEfNrjqpsADU6NBpPeAMRHzxgpQlvt0wn0LNRv2W0omXKPlw+aWA1KznXJcX+7bhytDW6N/e/uwzXfcipM+hZKlTR2nS1WO0/rp+MfZyotfDSq05qYsMDbldbvKi38EX2RT7RtGXkKJ+9aXRKPiGUUOcor0TnjbwYC5HBxvvKPsoGdul9yXtF3QV3SKEyKE4b+xcPwfWt4JR6JGtFdY1kQ8v7UGhv3ngg4QKpMguaKOP7UMUgwkpIU3XwGH42b2BXu+y+VZO+LmtIbSwcK36Iry+91ktl9TS/0J4KWTRzuWzRNrAfUePFwEkqzyYyeCXPWJO77IBGjcqC5AM3aywa+62F9I9VEXqqv2QFZ3o8oK7SFXiKd8azawQZ79l19n+Rcslrtb/qLbST+vGx27Q4LJJQ7gguSk3nHTGasBeO5L7pK+lUnXrJWH8pNNwH162HfrkFMUxVmBM6MTxAMQUD5gK8A1awjARH1TyBe0X2TaEbJXu9vcWZUwVxDDX1XjLdq4ynpWcmryoUJS0vpucbEx/w557XIb3daEva4yk9ITuK6L7EGdKOQJ27C4D6AX31pgULlRb4sLRMVWBwcoMj38qp93xYjEjovdd/Kbjddg11FB/zkemj03nvT2JlpWAcdU9AODP/SllJdaqGnUzpTRtrslFnp7kBzzAjm4JQSe5iCszU7oJVGbY76c18UYHWhZ0UNINrpON9OR873G81CgpUqRBTsVtt9TSjUMsLyeUbyILSuJ183BzVXVT6YGD+bR74w+ciNFnVAspv89toFcJT1N6Fxeg4Sx4othoa+MvMV1cw5kXA5l/8VK5E7OfNTw+YcuRQg0ZWD+3nhWLynWpljk6staVDbj2zEPIMOO8OQkZIRURT8P8waWUY3GM9d6kB/Hu+sgA7puEjIOfcGcoXw2xNSTLtmVJCzJrp5qh6iMNBem0BwShLPk1Z6mIVXkkyzfitPx4qt5XfaooomF2FIXOH7qi3dadElMcZUXFNS3oLuHhnOEM2QrwTyUCd2mYOwd1ImnIQKMHxU3Afnre5TWuUwWeq+wK3EhXxJJ3ktI9O4n8ECs2OES7lqsRE8V0CeKTtru3DzZLbJsSGovSPz3g74/1t1a1+49KD0K5v1UgoXserHkDLhKik4bDXujCSyM/+tcsls5sc+rzm1a+LbuBPUvr/auqBsGnPXOeNvi+LWN0ag== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Users can now enable or disable the Core Performance Boost (CPB) feature on individual CPUs using the `boost` sysfs attribute. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- Documentation/admin-guide/pm/amd-pstate.rst | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index dc1b10d7dd09..57995f54f0c8 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -281,6 +281,27 @@ integer values defined between 0 to 255 when EPP feature is enabled by platform firmware, if EPP feature is disabled, driver will ignore the written value This attribute is read-write. +``boost`` +The `boost` sysfs attribute provides control over the CPU core +performance boost, allowing users to manage the maximum frequency limitation +of the CPU. This attribute can be used to enable or disable the boost feature +on individual CPUs. + +When the boost feature is enabled, the CPU can dynamically increase its frequency +beyond the base frequency, providing enhanced performance for demanding workloads. +On the other hand, disabling the boost feature restricts the CPU to operate at the +base frequency, which may be desirable in certain scenarios to prioritize power +efficiency or manage temperature. + +To manipulate the `boost` attribute, users can write a value of `0` to disable the +boost or `1` to enable it, for the respective CPU using the sysfs path +`/sys/devices/system/cpu/cpuX/cpufreq/boost`, where `X` represents the CPU number. + +It is important to note that modifying the global variable +`/sys/devices/system/cpu/amd_pstate/cpb_boost` will override the individual CPU +settings. + + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.