From patchwork Wed Jun 19 08:45:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 806069 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A8092139B1; Wed, 19 Jun 2024 08:45:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718786753; cv=none; b=ERoPPf2tAdPP2RngnQAtA+gdgV34SqKqCC+L+E2VvThGR9KqzS6h1trqm2AKhGZrkTou+zJ6CYmW91tDOR6J1HCOHoOnmCMbCzkSbJsHMFYgKyZVJtZgeTYwenjjmAFrFncFLP/soPptYaLyb5RkzPha0Jx5356jkdVtc2rfAPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718786753; c=relaxed/simple; bh=VPko8A1dsJhGfauSkOnRVf64PdjlMkke7UygpBGQoRU=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=iXv1MRnbHOrWpd1ag49yYnelnxhhcmaowNeWJPJXEm4cTnxouOWe+EaxKLXm2jjvLlkT3/TB+Sriw1Zv8x9E1+T8IoCLmskF5t5xvJLpGEVODejf2LgeYzBQl840MoaZbeO5QWRwh/JXjqfrCXTVMUeaO68hkdfIZJXKrvV7tcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AgTIjAMe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AgTIjAMe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA1F4C2BBFC; Wed, 19 Jun 2024 08:45:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718786752; bh=VPko8A1dsJhGfauSkOnRVf64PdjlMkke7UygpBGQoRU=; h=From:To:Cc:Subject:Date:From; b=AgTIjAMea49Zr/kJ721r/Hf5kIr12/zNJ+P8cs8qMWvDxwiYUSZg9rwCmD8atMX0P 8D/OqD/c5CRkkJ0dHKkSU6S+00kNs+6GC2WaGPlJtq5zxzH2e2y0oNoSh4bNk4vone 3RTvnaHucIy2MjyXP5OC/YIhDGrpf1IcIPBTJi9cHKXxLve7TGWa/jRYBeYu6MqwCu vbJAGEwS9p/8qswACATfh7YyRytuEIvakr3M5vieqSfFarczygba6vMhzsFYvjO6Xf SWzSct9/Any8mAWymtFOB3J747WDcbieFCBIjORigGplnKteqBmw9EvPmiQeD7PZca z89i2qXlgMakA== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sJqww-00000003FRA-2Url; Wed, 19 Jun 2024 10:45:50 +0200 From: Mauro Carvalho Chehab To: Cc: Mauro Carvalho Chehab , Alison Schofield , Ard Biesheuvel , Dave Jiang , Ira Weiny , Borislav Petkov , Tony Luck , James Morse , Jonathan Cameron , Shiju Jose , linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: [RFC] efi/cper: align ARM CPER type with UEFI 2.9A/2.10 specs Date: Wed, 19 Jun 2024 10:45:43 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Up to UEFI 2.9 spec, the type byte of CPER struct was defined simply as type at byte offset 4: - Cache error - TLB Error - Bus Error - Micro-architectural Error All other values are reserved Yet, there was no information about how this would be encoded. Spec 2.9A errata corrected it by defining: - Bit 1 - Cache Error - Bit 2 - TLB Error - Bit 3 - Bus Error - Bit 4 - Micro-architectural Error All other values are reserved Spec 2.10 also preserve the same encoding as 2.9A See: https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#arm-processor-error-information Adjust CPER handling code for ARM to properly handle UEFI 2.9A and 2.10 encoding. Signed-off-by: Mauro Carvalho Chehab --- drivers/firmware/efi/cper-arm.c | 37 +++++++++++++-------------------- include/linux/cper.h | 9 ++++---- 2 files changed, 18 insertions(+), 28 deletions(-) diff --git a/drivers/firmware/efi/cper-arm.c b/drivers/firmware/efi/cper-arm.c index fa9c1c3bf168..17b84ffa61d2 100644 --- a/drivers/firmware/efi/cper-arm.c +++ b/drivers/firmware/efi/cper-arm.c @@ -93,15 +93,11 @@ static void cper_print_arm_err_info(const char *pfx, u32 type, bool proc_context_corrupt, corrected, precise_pc, restartable_pc; bool time_out, access_mode; - /* If the type is unknown, bail. */ - if (type > CPER_ARM_MAX_TYPE) - return; - /* * Vendor type errors have error information values that are vendor * specific. */ - if (type == CPER_ARM_VENDOR_ERROR) + if (type & CPER_ARM_VENDOR_ERROR) return; if (error_info & CPER_ARM_ERR_VALID_TRANSACTION_TYPE) { @@ -116,43 +112,38 @@ static void cper_print_arm_err_info(const char *pfx, u32 type, if (error_info & CPER_ARM_ERR_VALID_OPERATION_TYPE) { op_type = ((error_info >> CPER_ARM_ERR_OPERATION_SHIFT) & CPER_ARM_ERR_OPERATION_MASK); - switch (type) { - case CPER_ARM_CACHE_ERROR: + if (type & CPER_ARM_CACHE_ERROR) { if (op_type < ARRAY_SIZE(arm_cache_err_op_strs)) { - printk("%soperation type: %s\n", pfx, + printk("%scache error: %s\n", pfx, arm_cache_err_op_strs[op_type]); } - break; - case CPER_ARM_TLB_ERROR: + } + if (type & CPER_ARM_TLB_ERROR) { if (op_type < ARRAY_SIZE(arm_tlb_err_op_strs)) { - printk("%soperation type: %s\n", pfx, + printk("%sTLB error: %s\n", pfx, arm_tlb_err_op_strs[op_type]); } - break; - case CPER_ARM_BUS_ERROR: + } + if (type & CPER_ARM_BUS_ERROR) { if (op_type < ARRAY_SIZE(arm_bus_err_op_strs)) { - printk("%soperation type: %s\n", pfx, + printk("%sbus error: %s\n", pfx, arm_bus_err_op_strs[op_type]); } - break; } } if (error_info & CPER_ARM_ERR_VALID_LEVEL) { level = ((error_info >> CPER_ARM_ERR_LEVEL_SHIFT) & CPER_ARM_ERR_LEVEL_MASK); - switch (type) { - case CPER_ARM_CACHE_ERROR: + if (type & CPER_ARM_CACHE_ERROR) printk("%scache level: %d\n", pfx, level); - break; - case CPER_ARM_TLB_ERROR: + + if (type & CPER_ARM_TLB_ERROR) printk("%sTLB level: %d\n", pfx, level); - break; - case CPER_ARM_BUS_ERROR: + + if (type & CPER_ARM_BUS_ERROR) printk("%saffinity level at which the bus error occurred: %d\n", pfx, level); - break; - } } if (error_info & CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT) { diff --git a/include/linux/cper.h b/include/linux/cper.h index 265b0f8fc0b3..afc6d41b4e67 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -293,11 +293,10 @@ enum { #define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2) #define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3) -#define CPER_ARM_CACHE_ERROR 0 -#define CPER_ARM_TLB_ERROR 1 -#define CPER_ARM_BUS_ERROR 2 -#define CPER_ARM_VENDOR_ERROR 3 -#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR +#define CPER_ARM_CACHE_ERROR BIT(1) +#define CPER_ARM_TLB_ERROR BIT(2) +#define CPER_ARM_BUS_ERROR BIT(3) +#define CPER_ARM_VENDOR_ERROR BIT(4) #define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0) #define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)