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Mon, 17 Jun 2024 01:03:53 -0700 (PDT) From: Caleb Connolly Date: Mon, 17 Jun 2024 10:03:47 +0200 Subject: [PATCH v3 1/3] arm64: mmu.h: fix PTE_TABLE_AP MIME-Version: 1.0 Message-Id: <20240617-caleb-upstreaming-v3-1-1ba35dc9179d@linaro.org> References: <20240617-caleb-upstreaming-v3-0-1ba35dc9179d@linaro.org> In-Reply-To: <20240617-caleb-upstreaming-v3-0-1ba35dc9179d@linaro.org> To: Tom Rini Cc: Michal Simek , Ilias Apalodimas , Neil Armstrong , u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=757; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=e1xnCDVDSraolIJhnHUmQGQpqz/i168ZLEa3Z2JGSc4=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmb+3oFukAwp7776hOWqO7rJA16qJeGTByJuFCP lHiFmck3/WJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZm/t6AAKCRAFgzErGV9k tr5wD/90lTEfZeCt+aDC1OEnNIyAazDOKLLzokGcylprpLqYTCpvjcnF1Zh8oxPh8Ywa+PBnRkE xitGmYRh73sGN29ARmIUv0hfi1bnNchI3KXWbEUbMLVD9J3ETt7C8sCseXgOYWZRBDaXFJIPeTa fNTYzP8YIOwnY70mRZh29hj7/Gq2EYU9sUCg+uwhNv+mbaMD5o6ONYknW9laJJpB+W+yTJRYu0X okQckJlEK2aIR5GsZwYc0/zjQTujmlUD7X0Abb7cXyFJ1u/VKOmPWX3RqgaxXu60nyPcahgSGUf uF458ncTs4BBqA82DA3wAN58f+pWmvlE5RvPcG88VNabTuEULyes5T2vJ/9KuZ4FdpZwuhgD051 EYTMTiacbGbAvglofmk65T3jwpjdbsbPt80pA7TIvj2MHC2mXDS5oWDo5t7/DnndhHVXeGazxno 8pU/m5UQJjUFC1Tuz/ltu4sNkpGljOPL1P/+zGm3M/t0PtBHJYMYa9nEtijfiNeH9IdXDQshewD o6bEZ9VBmNDJAlLK4CB/r2lXiBlPwJV78GkV5zqgMhGJx0F4wJ829D3X4gtxQV6oJtqpXlGmtbX Rvhiz7qaarPC2QqnOWW+DZisL144w1fpNdJkZe8wZYUiSZ+n8Jd42yQCq0CChNyKA5/CjiL75KO 3Flyj/NQnFvzadg== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The APTable attribute is two bits wide according to the ARMv8-A architecture reference manual. Fix the macro accordingly. Signed-off-by: Caleb Connolly --- arch/arm/include/asm/armv8/mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index ce655ce7a952..52cb18b9ed5e 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -50,9 +50,9 @@ #define PTE_TYPE_VALID (1 << 0) #define PTE_TABLE_PXN (1UL << 59) #define PTE_TABLE_XN (1UL << 60) -#define PTE_TABLE_AP (1UL << 61) +#define PTE_TABLE_AP (3UL << 61) #define PTE_TABLE_NS (1UL << 63) /* * Block From patchwork Mon Jun 17 08:03:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 804866 Delivered-To: patch@linaro.org Received: by 2002:adf:fb90:0:b0:360:93e7:1765 with SMTP id a16csp447162wrr; Mon, 17 Jun 2024 01:04:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU7eK8hSDqrN9vvUK6cjy4KRU+qlQ0OuaUVAv+kcAM6oXI4gb6Eb6q3k6N7OwgkhnKizlv/tSAnniFtzEZRlfkt X-Google-Smtp-Source: AGHT+IEGtvEyYUapf7fBrL8NYOvamZ4RfWjLP8qESREFbqdf8KFiniLu7pYvbaMCpvHeRdOA/cLH X-Received: by 2002:a50:8747:0:b0:57c:563b:f37f with SMTP id 4fb4d7f45d1cf-57cbd67dbedmr6261588a12.19.1718611461559; Mon, 17 Jun 2024 01:04:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1718611461; cv=none; d=google.com; s=arc-20160816; b=Q+5UXBleY2bjvpGdFhnvqEYReRlAqbls9lgj7IWMMTbtzmpGKwxvYtd0JZX1AzPiXZ yAGuZx3or4LjCKkI8rinlafNA7j92Cr5wZIeXaBTI4kEnvWoKS0pu/gMjha+n+zaqHAE 7gryqBQMpFG+rYRe0iwzKEJV3so71ZOh8SLWZ/p6hHfUVLAdC+SsizaT4XiUro2Nbv6B UOiOprCskPW87KAwx+SRT+xxOT+iVilMqqopR60JnTXXK1LGDjC7Od8cQW2T/cCwzDFN +LF+FVWzKUsGfgMI6+NjaGvw2hpKj7s2TAjFQTVh8bPtHgEURppZ6ihcJSlA+omsxRQ+ n4Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=KeWLLc1x+3A5e5lAV/5VfRTg3STaj+HfrLlU0fBCHSA=; fh=FwM+eEH2zex6kbSFM+jR+ip52KnZHu8E094tWd8xw/o=; b=ffDMCVyFquH1jH+BKuyvbv2nwt4S8uDiTTm65hCnGwwGEZFy2MYH/Y0Bdj0EvVYTFx KuVu/1jd/2fd9ThRzUblDV2V4mFlnaw30dbNjiJVKFvkCRysNWh7QlG++QrSb3iCWVkB 6GPYBROo35RqzL2Sgzu8Rz3tZDg+dW/xrk9Q5IezfVYwgfQqDuXseTApIBWgzM1P+dKU UpJFbgG5iHxMy3SUtmNScKDGT+/pYzbQTqZUSDxrppR7ftDt1u0tnPnZRbEulv8kpPid nd4ojqhKNcDhb6Kxytf8x7wpnUWgOtHHbbDwxBq1Ish9CnuGeN88SvOG++/Ae0cLnIzn iL0A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=spLZQw3E; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add a basic software implementation of the ARM64 pagetable walker. This can be used for debugging U-Boot's pagetable, as well as dumping the pagetable from the previous bootloader stage if it used one (by reading out the ttbr address). One can either call dump_pagetable() to print the pagetable to the console with the default formatter, or implement their own pagetable handler using walke_pagetable() with a custom pte_walker_cb_t callback. All of the added code is discarded when unused, hence there is no need to add an additional Kconfig option for this. Signed-off-by: Caleb Connolly --- arch/arm/cpu/armv8/cache_v8.c | 245 +++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 56 +++++++++ 2 files changed, 301 insertions(+) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index d4c64f2d60d9..c3f8dac648ba 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -395,8 +395,253 @@ static int count_ranges(void) return count; } +#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) + +enum walker_state { + WALKER_STATE_START = 0, + WALKER_STATE_TABLE, + WALKER_STATE_REGION, /* block or page, depending on level */ +}; + + +/** + * __pagetable_walk() - Walk through the pagetable and call cb() for each memory region + * + * This is a software implementation of the ARMv8-A MMU translation table walk. As per + * section D5.4 of the ARMv8-A Architecture Reference Manual. It recursively walks the + * 4 or 3 levels of the page table and calls the callback function for each discrete + * region of memory (that being the discovery of a new table, a collection of blocks + * with the same attributes, or of pages with the same attributes). + * + * U-Boot picks the smallest number of virtual address (VA) bits that it can based on the + * memory map configured by the board. If this is less than 39 then the MMU will only use + * 3 levels of translation instead of 3 - skipping level 0. + * + * Each level has 512 entries of 64-bits each. Each entry includes attribute bits and + * an address. When the attribute bits indicate a table, the address is the physical + * address of the table, so we can recursively call _pagetable_walk() on it (after calling + * @cb). If instead they indicate a block or page, we record the start address and attributes + * and continue walking until we find a region with different attributes, or the end of the + * table, in either case we call @cb with the start and end address of the region. + * + * This approach can be used to fully emulate the MMU's translation table walk, as per + * Figure D5-25 of the ARMv8-A Architecture Reference Manual. + * + * @addr: The address of the table to walk + * @tcr: The TCR register value + * @level: The current level of the table + * @cb: The callback function to call for each region + * @priv: Private data to pass to the callback function + */ +static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, void *priv) +{ + u64 *table = (u64 *)addr; + u64 attrs, last_attrs = 0, last_addr = 0, entry_start = 0; + int i; + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + static enum walker_state state[4] = { 0 }; + static bool exit; + + if (!level) { + exit = false; + if (va_bits < 39) + level = 1; + } + + state[level] = WALKER_STATE_START; + + /* Walk through the table entries */ + for (i = 0; i < MAX_PTE_ENTRIES; i++) { + u64 pte = table[i]; + u64 _addr = pte & GENMASK_ULL(va_bits, PAGE_SHIFT); + + if (exit) + return; + + if (pte_type(&pte) == PTE_TYPE_FAULT) + continue; + + attrs = pte & ALL_ATTRS; + /* If we're currently inside a block or set of pages */ + if (state[level] > WALKER_STATE_START && state[level] != WALKER_STATE_TABLE) { + /* + * Continue walking if this entry has the same attributes as the last and + * is one page/block away -- it's a contiguous region. + */ + if (attrs == last_attrs && _addr == last_addr + (1 << level2shift(level))) { + last_attrs = attrs; + last_addr = _addr; + continue; + } else { + /* We either hit a table or a new region */ + exit = cb(entry_start, last_addr + (1 << level2shift(level)), + va_bits, level, priv); + if (exit) + return; + state[level] = WALKER_STATE_START; + } + } + last_attrs = attrs; + last_addr = _addr; + + if (PTE_IS_TABLE(pte, level)) { + /* After the end of the table might be corrupted data */ + if (!_addr || (pte & 0xfff) > 0x3ff) + return; + state[level] = WALKER_STATE_TABLE; + /* Signify the start of a table */ + exit = cb(pte, 0, va_bits, level, priv); + if (exit) + return; + + /* Go down a level */ + __pagetable_walk(_addr, tcr, level + 1, cb, priv); + state[level] = WALKER_STATE_START; + } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) { + /* We foud a block or page, start walking */ + entry_start = pte; + state[level] = WALKER_STATE_REGION; + } + } + + if (state[level] > WALKER_STATE_START) + exit = cb(entry_start, last_addr + (1 << level2shift(level)), va_bits, level, priv); +} + +static void pretty_print_pte_type(u64 pte) +{ + switch (pte_type(&pte)) { + case PTE_TYPE_FAULT: + printf(" %-5s", "Fault"); + break; + case PTE_TYPE_BLOCK: + printf(" %-5s", "Block"); + break; + case PTE_TYPE_PAGE: + printf(" %-5s", "Pages"); + break; + default: + printf(" %-5s", "Unk"); + } +} + +static void pretty_print_table_attrs(u64 pte) +{ + int ap = (pte & PTE_TABLE_AP) >> 61; + + printf(" | %2s %10s", + (ap & 2) ? "RO" : "", + (ap & 1) ? "!EL0" : ""); + printf(" | %3s %2s %2s", + (pte & PTE_TABLE_PXN) ? "PXN" : "", + (pte & PTE_TABLE_XN) ? "XN" : "", + (pte & PTE_TABLE_NS) ? "NS" : ""); +} + +static void pretty_print_block_attrs(u64 pte) +{ + u64 attrs = pte & PMD_ATTRINDX_MASK; + + switch (attrs) { + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): + printf(" | %-13s", "Device-nGnRnE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE): + printf(" | %-13s", "Device-nGnRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_GRE): + printf(" | %-13s", "Device-GRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL_NC): + printf(" | %-13s", "Normal-NC"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL): + printf(" | %-13s", "Normal"); + break; + default: + printf(" | %-13s", "Unknown"); + } +} + +static void pretty_print_block_memtype(u64 pte) +{ + u64 share = pte & (3 << 8); + + switch (share) { + case PTE_BLOCK_NON_SHARE: + printf(" | %-16s", "Non-shareable"); + break; + case PTE_BLOCK_OUTER_SHARE: + printf(" | %-16s", "Outer-shareable"); + break; + case PTE_BLOCK_INNER_SHARE: + printf(" | %-16s", "Inner-shareable"); + break; + default: + printf(" | %-16s", "Unknown"); + } +} + +static void print_pte(u64 pte, int level) +{ + if (PTE_IS_TABLE(pte, level)) { + printf(" %-5s", "Table"); + pretty_print_table_attrs(pte); + } else { + pretty_print_pte_type(pte); + pretty_print_block_attrs(pte); + pretty_print_block_memtype(pte); + } + printf("\n"); +} + +/** + * pagetable_print_entry() - Callback function to print a single pagetable region + * + * This is the default callback used by @dump_pagetable(). It does some basic pretty + * printing (see example in the U-Boot arm64 documentation). It can be replaced by + * a custom callback function if more detailed information is needed. + * + * @start_attrs: The start address and attributes of the region (or table address) + * @end: The end address of the region (or 0 if it's a table) + * @va_bits: The number of bits used for the virtual address + * @level: The level of the region + * @priv: Private data for the callback (unused) + */ +static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int level, void *priv) +{ + u64 _addr = start_attrs & GENMASK_ULL(va_bits, PAGE_SHIFT); + int indent = va_bits < 39 ? level - 1 : level; + + printf("%*s", indent * 2, ""); + if (PTE_IS_TABLE(start_attrs, level)) + printf("[%#011llx]%14s", _addr, ""); + else + printf("[%#011llx - %#011llx]", _addr, end); + + printf("%*s | ", (3 - level) * 2, ""); + print_pte(start_attrs, level); + + return false; +} + +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv) +{ + __pagetable_walk(ttbr, tcr, 0, cb, priv); +} + +void dump_pagetable(u64 ttbr, u64 tcr) +{ + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + + printf("Walking pagetable at %p, va_bits: %lld. Using %d levels\n", (void *)ttbr, + va_bits, va_bits < 39 ? 3 : 4); + walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL); +} + /* Returns the estimated required size of all page tables */ __weak u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 52cb18b9ed5e..1348db4204ee 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -128,8 +128,64 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } +static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr) +{ + if (el == 1) { + asm volatile("mrs %0, ttbr0_el1" : "=r" (*table)); + asm volatile("mrs %0, tcr_el1" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el1" : "=r" (*attr)); + } else if (el == 2) { + asm volatile("mrs %0, ttbr0_el2" : "=r" (*table)); + asm volatile("mrs %0, tcr_el2" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el2" : "=r" (*attr)); + } else if (el == 3) { + asm volatile("mrs %0, ttbr0_el3" : "=r" (*table)); + asm volatile("mrs %0, tcr_el3" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el3" : "=r" (*attr)); + } else { + hang(); + } +} + +/** + * pte_walker_cb_t - callback function for walk_pagetable. + * + * This function is called when the walker finds a table entry + * or after parsing a block or pages. For a table the @end address + * is 0, and @addr is the address of the table. Otherwise, they + * are the start and end physical addresses of the block or page. + * + * @addr: PTE start address (PA), or address of table. Includes attributes. + * @end: End address of the region (or 0 for a table) + * @va_bits: Number of bits in the virtual address + * @level: Table level + * @priv: Private data for the callback + * + * Return: true to stop walking, false to continue + */ +typedef bool (*pte_walker_cb_t)(u64 addr, u64 end, int va_bits, int level, void *priv); + +/** + * walk_pagetable() - Walk the pagetable at ttbr and call @cb for each region + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + * @cb: Callback function to call for each entry + * @priv: Private data for the callback + */ +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv); + +/** + * dump_pagetable() - Dump the pagetable at ttbr, printing each region and + * level. + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + */ +void dump_pagetable(u64 ttbr, u64 tcr); + struct mm_region { u64 virt; u64 phys; u64 size; From patchwork Mon Jun 17 08:03:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 804867 Delivered-To: patch@linaro.org Received: by 2002:adf:fb90:0:b0:360:93e7:1765 with SMTP id a16csp447233wrr; Mon, 17 Jun 2024 01:04:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV/zyTJeHxSFlA8s+A+wgAw50SFIzH0bQOGfy/biBrTHYsUyS4mjmyvaIvxhKW+J9jE8+9IC9rB2HYAgiyXTOZw X-Google-Smtp-Source: AGHT+IFKhyt3I3eVguW6n9v9DCwMlHKEniobnjNVAy/Fo4yENmpGm4Zvwv1ghW7VPfSgDpZryRYn X-Received: by 2002:a05:6512:3a6:b0:52c:8f4e:b1c9 with SMTP id 2adb3069b0e04-52ca6e6712dmr6264730e87.15.1718611472144; Mon, 17 Jun 2024 01:04:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1718611472; cv=none; d=google.com; s=arc-20160816; b=S3ff3wuOEjsInIZw+K9H7WgbSt2RWCDa/ww5dDVQzInrW288voSPPAAT80j4bb7i/1 N8Cw9lubglQwuiwnZ2VTLyLVHGrm3XquYJJQQ+zL8hc0/wiQojf4z5ZJfkbTtkskIa7b Co3BjG86AgaGj4WE69NzSFIGZEfKKzlRS+bQlO4JUJ0ZWyJi4H2Ae87In8Snc1y4kT4Z fQJxBUatYyLoV0GnY/jUdCHHIppljnqM/Uck0xP7BxbItZzwt3pz/cLS7+UMFnQb6yhI MfqlaUAo/ZsmMXLAQPKzgtGF14hlsG0IJh516vIJj4m78xCMuVJuxZ2T401ZTQCd8ZQw lq2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=AJ93HwsqAXtIbUSZ7NQ6F4J0JBSryn27ujF9AziP7Ik=; fh=vFUtK+Pu84arNftK6TabbNpJrSj8shSLjdbqVoXxAgg=; b=F5P4JnDxwGa/vbPtwQNBZ7BAKmrjjtgK62xeTUmLTLzkAUoQaRXuh6tVdSy2AbxxQV aYuZgRhz/+zCCBun1iBreq2O70skggyIIemwIvDf4RLf2DZOM5wKf7P56PYvvNptfWan oGXmfMcl2rEBSwQXwRh+VPgMINzMSDMM1ZH6aiD5Eb30mJr7T+31jwnz8h3pB4xeA6vi ozITUpJICXMnm3zFQrTaJYmqq6bVYSYzcirtFqyXABHy1EmmEgUD8qKd8+oXswYAreNG wVlyyWX+7bjckUj+pjma0k6PUM0qzydXHrpiODC681cHfan2rrpg5SHbk4EV0Dp4T/+q ld5A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jSehmHC1; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Mon, 17 Jun 2024 01:03:56 -0700 (PDT) From: Caleb Connolly Date: Mon, 17 Jun 2024 10:03:49 +0200 Subject: [PATCH v3 3/3] doc: arch: arm64: describe pagetable debugging MIME-Version: 1.0 Message-Id: <20240617-caleb-upstreaming-v3-3-1ba35dc9179d@linaro.org> References: <20240617-caleb-upstreaming-v3-0-1ba35dc9179d@linaro.org> In-Reply-To: <20240617-caleb-upstreaming-v3-0-1ba35dc9179d@linaro.org> To: Tom Rini Cc: Michal Simek , Ilias Apalodimas , Neil Armstrong , u-boot@lists.denx.de, Caleb Connolly X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2885; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=TPOgzFdhZenO6Jgr2nYHp08fJzeSlno4tUwmj5uCwUg=; b=owEBbQKS/ZANAwAIAQWDMSsZX2S2AcsmYgBmb+3oFbR+A5QkEy3+DMbs7T/R0Go6c0zME/2nf Dar86SbWmyJAjMEAAEIAB0WIQS2UaFGPGq+0GkMVc0FgzErGV9ktgUCZm/t6AAKCRAFgzErGV9k togPEACiNd1QYtbtPW7RxxspYzVgJimcDrsKg6M4v+LUXj/FmpoBD0IAi88K9ovWubAxmjfOneb Bybr7T4oIL8x5p6q4RS8fUn4x+cKJ8S2gcKitOIN2x9eET3OjrE89ekqV3eOuyGla8/LdbB81WX 0kmKLjlukoYNfs0VbNIfk3XtVUZGND1WAA2kwc7tuLGVk2Pl0YphUfm0wk2N0nLDtq7f2gGa7Tg TTqCDRTIR2oTjeZnuTgsLwOTuGJODPGbtkYNVoeX5TY7kF4ogp7DX1CouwANfg/pyVq50gVshY2 G4B7bfqWuswz7zntYtqZtldipGaShF8TYKblHb9CmVQVngLEQTnoRjRqEoR7euj2osLZ40+xqlM i4qsLg/107oO5oXm1GKH70+GhWHEz+0LHa8XjgzIru9sZRyyIhWcPT5KFOclQp+yyTWp40u55LS w+/YzfzkgzYn1hZftsFwWUXlzHmUNGcEhvpcO/TpxBn3PmxFtRUqZjmSGb3Qdywguc79uiCvM4J 7m0Mcf3tES/0zkfp2Fcv9XMpHAwaO8qfLkHiIff9rWanM9mSkLzwQm0kmnXh/NtoyLO8DYFn5IK y0v6LqryRwL9gYtjreQDi0XOUo9y2Ym3eWNuxGdBOZXTA0GESPLf3vfwE4GcGZCkVrBS47Btd8M TCnYvH03HJoKkSw== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add some brief documentation on using dump_pagetables() to print out U-Boot's pagetables during boot. Signed-off-by: Caleb Connolly --- doc/arch/arm64.rst | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/doc/arch/arm64.rst b/doc/arch/arm64.rst index 7c0713504c47..19662be6fc6e 100644 --- a/doc/arch/arm64.rst +++ b/doc/arch/arm64.rst @@ -47,8 +47,57 @@ Notes 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and aarch32 specific codes. +MMU +--- + +U-Boot uses a simple page table for MMU setup. It uses the smallest number of bits +possible for the virtual address based on the maximum memory address (see the logic +in ``get_tcr()``). If this is less than 39 bits, the MMU will use only 3 levels for +address translation. + +As with all platforms, U-Boot on ARM64 uses a 1:1 mapping of virtual to physical addresses. +In general, the memory map is expected to remain static once the MMU is enabled. + +Software pagetable walker +^^^^^^^^^^^^^^^^^^^^^^^^^ + +It is possible to debug the pagetable generated by U-Boot with the built in +``dump_pagetable()`` and ``walk_pagetable()`` functions (the former being a simple +wrapper for the latter). For example the following can be added to ``setup_all_pgtables()`` +after the first call to ``setup_pgtables()``: + +.. code-block:: c + + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); + +.. kernel-doc:: arch/arm/cpu/armv8/cache_v8.c + :identifiers: __pagetable_walk pagetable_print_entry + +The pagetable walker can be used as follows: + +.. kernel-doc:: arch/arm/include/asm/armv8/mmu.h + :identifiers: pte_walker_cb_t walk_pagetable dump_pagetable + +This will result in a print like the following: + +.. code-block:: text + + Walking pagetable at 000000017df90000, va_bits: 36. Using 3 levels + [0x17df91000] | Table | | + [0x17df92000] | Table | | + [0x000001000 - 0x000200000] | Pages | Device-nGnRnE | Non-shareable + [0x000200000 - 0x040000000] | Block | Device-nGnRnE | Non-shareable + [0x040000000 - 0x080000000] | Block | Device-nGnRnE | Non-shareable + [0x080000000 - 0x140000000] | Block | Normal | Inner-shareable + [0x17df93000] | Table | | + [0x140000000 - 0x17de00000] | Block | Normal | Inner-shareable + [0x17df94000] | Table | | + [0x17de00000 - 0x17dfa0000] | Pages | Normal | Inner-shareable + +For more information, please refer to the additional function documentation in +``arch/arm/include/asm/armv8/mmu.h``. Contributors ------------ * Tom Rini