From patchwork Thu Oct 24 11:40:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177409 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2062753ill; Thu, 24 Oct 2019 04:41:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxb2K52GDJLM/3MGYsIPi/ziZaK3963KIFq4jwf6RklHpdsHiJwjBVN4OJiEaLu19aemysC X-Received: by 2002:aa7:d28d:: with SMTP id w13mr42219561edq.184.1571917262965; Thu, 24 Oct 2019 04:41:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571917262; cv=none; d=google.com; s=arc-20160816; b=THoeL2n9iAdNVXVJTTZRtF63LBhdt5G5BjwJZmRV+fgsNOwtS6fiqUXqf93Emd6pRm oOFsrUY5dV0dqKZAi5D54P9cGDY95aksrFtsSNv6R1asNeka/y3hDbkSaut923X8tAoV v9VZvyB8ZKa4RSvftXXy5QWnwvzKH76LsAQrAL1jSt0vMWSE8mJIusDfRhlq4LfS+RAH qjIHFf0CQpl6SNvxux6/DPHiTppPoibWgt/JThqAPnI8VvtSj+u+hVj7TObpsGUIGrQr FH9rV48U2RYRlzwsjVgz7nSvsZYK7KWxn1CeQu+CJt72nm52SOg8ndKt255p1Ro8jP2g qmCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=aZ5vSfLI7IEX6A4bp3VeoImtgXF8hKwoS6ngiBVedGY=; b=aP0vOjCiGixXnxEmmFDbJJKjgKiO3jAVDww7hRAa7IN9YtyiC5JvLvUsRIwNriz7Nw PWthZ6Ap1LMkvBlQ2XoStzt98kWGbWMg/iyj6xplvtUYeIAVN4y1xbUq7MuziSdRsQBf lBD+AM8wbBGZcT02BivnpTCmEn761fnMRPMXh9myR2qfPFXdnln2Nv1yTvu6WTW+8D+g 2OavNRKwbCu0eGEnS/pByZQiBMewoXBvFNRvW2HMRfCigVnFpPLd7AgvoPElBOIjmMUG +YjRoROe3pUTKev604R3Bo/2a1ZLXGqiyV8+hR1nvUddfCiYhjuu6g2sLlpMSL2bd+4/ 78KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=uBEUB0AC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g31si231887eda.325.2019.10.24.04.41.02; Thu, 24 Oct 2019 04:41:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=uBEUB0AC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439049AbfJXLkz (ORCPT + 26 others); Thu, 24 Oct 2019 07:40:55 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37584 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725283AbfJXLkv (ORCPT ); Thu, 24 Oct 2019 07:40:51 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9OBen2A012074; Thu, 24 Oct 2019 06:40:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571917249; bh=aZ5vSfLI7IEX6A4bp3VeoImtgXF8hKwoS6ngiBVedGY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uBEUB0ACRQLq6gIrn8hYxxsl9YMZ82kqb/KunqhF3nIEa6BwdeGqcbZj5RidlGBMP K9pzJQb3lCs4KNE+gfmTz8Wf0C6Bs0VwVb98JYCkJrfc2HaQzvizqu/NzVB3xMkXpt b0JoqchcIR4SR64m++mUVHp6Z0VNdAqe++1lESxI= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9OBenci122198; Thu, 24 Oct 2019 06:40:49 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 24 Oct 2019 06:40:38 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 24 Oct 2019 06:40:48 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9OBeiTB044238; Thu, 24 Oct 2019 06:40:46 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v3 1/3] phy: cadence: Sierra: add phy_reset hook Date: Thu, 24 Oct 2019 14:40:40 +0300 Message-ID: <20191024114042.30237-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191024114042.30237-1-rogerq@ti.com> References: <20191024114042.30237-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms e.g. J721e need lane swap register to be programmed before reset is deasserted. This patch ensures that we propagate the phy_reset back to the reset controller driver. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Reviewed-by: Jyri Sarha --- drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 04c28cbb6d39..7fed61211716 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -339,10 +339,20 @@ static int cdns_sierra_phy_off(struct phy *gphy) return reset_control_assert(ins->lnk_rst); } +static int cdns_sierra_phy_reset(struct phy *gphy) +{ + struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); + + reset_control_assert(sp->phy_rst); + reset_control_deassert(sp->phy_rst); + return 0; +}; + static const struct phy_ops ops = { .init = cdns_sierra_phy_init, .power_on = cdns_sierra_phy_on, .power_off = cdns_sierra_phy_off, + .reset = cdns_sierra_phy_reset, .owner = THIS_MODULE, }; From patchwork Thu Oct 24 11:40:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177411 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2062837ill; Thu, 24 Oct 2019 04:41:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqzBVYrIX9u0XbHdt3J64Ne/WEc4TczRkR10yxYKd3uOqXMa3IiVSsz6U+hZSVwPtk9eZ1+N X-Received: by 2002:a17:906:f2d4:: with SMTP id gz20mr3281978ejb.215.1571917266610; Thu, 24 Oct 2019 04:41:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571917266; cv=none; d=google.com; s=arc-20160816; b=bv/8SyjEPgad6hwBb1MLHtyNqLeMn0LC3oJZMHQNNXhioUjhueiRJrIayHUpqiUwGt Oe7+OYeNyItTb1mp24ES1D196yc9j4G7HN/L1PzhQ3zLk/n5eWmGelSVRRO10dPnrMXV N+EAufL1ZzzM37qIl/HcFrtst3jD3mNxEWU9SJk9y77Jr45q9AAnaSzfV84nx8JCE/tt 9A56A4AW58oEWTGZtly/D/Dft/rNtb3qyYk/CyNJ9/9xf77sFybZeG3A598Qd2A+uJ+f yl5tc0FR68nenGfqjE0Dk2Xi95w0KIKauz8w3/LQiveNs7EMfp7iluH23n2KHlWXya0a ZwDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=lT8Q2O51dUFMd/09/sWikbVNGBZ7VFcHWG+/K0mo8OE=; b=FL0VWDVBOZQYMPaPHRj4x9QJQHqHfPSZlJIxO58804b4LviMs6BeC1i6bbRyYzekgz XHuKcZ9cOpKDy8JoGRykaz20PDsbI59KSsXD5l13MVPyXyVTO0JMDksNqKoi/4+7C/jg nqtdZasL95sZumYq+Cmkpd8nfQ5JhwvV3wIxRM8DQanWSylxU4WDCQ1mZHyt3/atWSDi k8Wo5BhiWErtLQZM9ZPkZxuTA8Z2YzS1ukPIqzSK0cBgBJjtLDVEqZ+TBymhczf4u3JO +QheZZ8n80ugn0mX1iHwkYwo/f+M6o3J8L70tXr4PK3QmQwTDxvsN+X2jWGg45xIvgK1 MeKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="eaWq/kJc"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g31si231887eda.325.2019.10.24.04.41.06; Thu, 24 Oct 2019 04:41:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="eaWq/kJc"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439062AbfJXLk7 (ORCPT + 26 others); Thu, 24 Oct 2019 07:40:59 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:50926 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2439047AbfJXLk4 (ORCPT ); Thu, 24 Oct 2019 07:40:56 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9OBesOA023190; Thu, 24 Oct 2019 06:40:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571917254; bh=lT8Q2O51dUFMd/09/sWikbVNGBZ7VFcHWG+/K0mo8OE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eaWq/kJcdfsPwK31g7TX0FMazPMbeVUVgbWFCkHf9foB6zBAbZAH8Th61Q1s8v11S oMTEir03wGn/ECaIZdRO2CPfg2TvrM3srrkCM2Tfmo6Qb/CD2iCTPZ4VJoikJtAl3K rVMe22kLMcVLaGP7IAPPbVze/83uK7qEqdSueZKE= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9OBesNV128817 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Oct 2019 06:40:54 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 24 Oct 2019 06:40:43 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 24 Oct 2019 06:40:43 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9OBeiTD044238; Thu, 24 Oct 2019 06:40:51 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v3 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir Date: Thu, 24 Oct 2019 14:40:42 +0300 Message-ID: <20191024114042.30237-4-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191024114042.30237-1-rogerq@ti.com> References: <20191024114042.30237-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Reviewed-by: Jyri Sarha --- drivers/phy/ti/phy-j721e-wiz.c | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 2a95da843e9f..02b949406b7b 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -22,6 +24,7 @@ #define WIZ_SERDES_CTRL 0x404 #define WIZ_SERDES_TOP_CTRL 0x408 #define WIZ_SERDES_RST 0x40c +#define WIZ_SERDES_TYPEC 0x410 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) #define WIZ_MAX_LANES 4 @@ -29,6 +32,8 @@ #define WIZ_DIV_NUM_CLOCKS_16G 2 #define WIZ_DIV_NUM_CLOCKS_10G 1 +#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) + enum wiz_lane_standard_mode { LANE_MODE_GEN1, LANE_MODE_GEN2, @@ -94,6 +99,9 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 24, 25), }; +static const struct reg_field typec_ln10_swap = + REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); + struct wiz_clk_mux { struct clk_hw hw; struct regmap_field *field; @@ -201,11 +209,14 @@ struct wiz { struct regmap_field *pma_cmn_refclk_mode; struct regmap_field *pma_cmn_refclk_dig_div; struct regmap_field *pma_cmn_refclk1_dig_div; + struct regmap_field *typec_ln10_swap; struct device *dev; u32 num_lanes; struct platform_device *serdes_pdev; struct reset_controller_dev wiz_phy_reset_dev; + struct gpio_desc *gpio_typec_dir; + int typec_dir_delay; }; static int wiz_reset(struct wiz *wiz) @@ -404,6 +415,13 @@ static int wiz_regfield_init(struct wiz *wiz) } } + wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, + typec_ln10_swap); + if (IS_ERR(wiz->typec_ln10_swap)) { + dev_err(dev, "LN10_SWAP reg field init failed\n"); + return PTR_ERR(wiz->typec_ln10_swap); + } + return 0; } @@ -703,6 +721,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, struct wiz *wiz = dev_get_drvdata(dev); int ret; + /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ + if (id == 0 && wiz->gpio_typec_dir) { + if (wiz->typec_dir_delay) + msleep_interruptible(wiz->typec_dir_delay); + + if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) + regmap_field_write(wiz->typec_ln10_swap, 1); + else + regmap_field_write(wiz->typec_ln10_swap, 0); + } + if (id == 0) { ret = regmap_field_write(wiz->phy_reset_n, true); return ret; @@ -789,6 +818,25 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } + wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", + GPIOD_IN); + if (IS_ERR(wiz->gpio_typec_dir)) { + ret = PTR_ERR(wiz->gpio_typec_dir); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request typec-dir gpio: %d\n", + ret); + goto err_addr_to_resource; + } + + if (wiz->gpio_typec_dir) { + ret = of_property_read_u32(node, "typec-dir-debounce", + &wiz->typec_dir_delay); + if (ret && ret != -EINVAL) { + dev_err(dev, "Invalid typec-dir-debounce property\n"); + goto err_addr_to_resource; + } + } + wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes;