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Wed, 12 Jun 2024 15:52:48 -0700 From: Liming Sun To: Adrian Hunter , Ulf Hansson , David Thompson CC: Liming Sun , , Subject: [PATCH v1 1/2] dw_mmc: support platform specific hw_reset() Date: Wed, 12 Jun 2024 18:52:37 -0400 Message-ID: <3df02ffa8bdaa74f5261c8914d2545b97fb3478a.1718213918.git.limings@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C9:EE_|SA1PR12MB7248:EE_ X-MS-Office365-Filtering-Correlation-Id: 882d289d-c8e6-4a12-7b4b-08dc8b326897 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230034|376008|1800799018|82310400020|36860700007; X-Microsoft-Antispam-Message-Info: 4/AMhA9zC/tr3AC/zPb/YsIMMhiE8REM7SKlL+s03zyN/5PGCLJrK2u7pn6oY1VKKM7EO95AtJD+e0EFZiWpknT762AjnsuCzPFt5mEqeJcWkOxqt/t7GzmktlTsdF6Uo4bmXHuOSemPYB4riFhVzlddCrvwD3E4YbBrQ/LazN3AiuvCNs80NId+FZzfH2wDzb1qRSUmnIlRLYgO0mvXMtwI/WxE0p74RP+9sRJ/dHGUuMRFIINe+mmYcwOcS7didciwXzvZcyTZnqNpDzGHcGhN2aBlc7nzKyRjIdyTQXSvpEt9wWRxsDqlZMp8zTaI0s/eXmsL5eYzYobrUdqCLbntwfU73bWT8d8oQbpMqAHdNWGrobZd3nc80A654RCYcQMFJvo8iflYVnobYnfuSc/zOj8cyvHmTmIQeK5WHIasnnctQw09onjOdP3/SGhtAnivzcWqaWxzKaW1x1kRca19jUKh/UoLI4Za7/jB28cKoD/te1EgAdmIrEwMP6zCIhaPeICmvh1JnDGUnhUDqO7wbyTEhDzj+tLpl2lykF0hZUwkGFtYb4l+NUhPCx2/DkvBBZSJWTaqsaw6e6FNwT3/nRsCW0pBbSXFxmJg68whCU2+TXjjRC+oMGO7Bd20kmHSjLxAL5MckZprpleOx9qoyKlxCYGj75ejvkFZCI/eQ6R9JQciopHXU69HdNiJ+9iMMWlGjWPZmUhan+WZn4VkG5pCTB4DrKVxvydEhswWjODeThuUHSBim3oCPl9S1CIofaYcL+ZSBPPXLlWLeGrQgJCr5sDb4z5zKkLvSlFtwxIB0bykJpU6vtjn3kjx+g9C4slJDEJ48dkrgMvSK9YjzBgVqrxdK2Q4hp1TOlrOKFUgpANEJbzVRdXSLWHNR0sDEVYtlH1/OiLe4OTFhtGuYZLPBSYTxs1EdGaAn0p7YoegQ2q0ipBwyIuISll+pyKu8yJdJsoBAEsgObaq30FemAm1gMKjCdDjsr6uVc9ZqUPLkzCX6qx3L9oRWfhxRf2H+pFWs7aDRexBRTaouQpjxJhNQ2OhyHZKeiEJCsdOkyQ9fFttZFCp+1khyMh7kLkPiV+SDS5HHXcJ4iIDkIDa+z+dTWdgYo9Z4v8sGum7zbgePzfyuUTZ2VMi7ZteOxAE5Q49dIoYVbGIqjcpa63ekKG6v9W74Re9BpGZCOJYlCLxE/42Ane3OKWfoJZuSvb0Vfh5BA8ddrLdvCNS6p6nua8XHVuFCDDG8mjaAvwjGMv5YNWd6m3VV0rT14+VShUNGxmWp1qxlb1omu5bW+6j2wSq3Ieyrw1SuRrwQR/n9731SjKyuxpd/yPOti+xKVgtyr1rs/2h/v54ZpJE3+XngWZIxfLd5G2vaVeuphTniajB+ui+rgb2PuIvJwxTWfVEjbQI7b2mpTfV7/nm0Q== X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Reviewed-by: David Thompson Signed-off-by: Liming Sun --- drivers/mmc/host/dw_mmc.c | 6 ++++++ drivers/mmc/host/dw_mmc.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 8e2d676b9239..2d72da03fdfd 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1617,6 +1617,7 @@ static void dw_mci_hw_reset(struct mmc_host *mmc) { struct dw_mci_slot *slot = mmc_priv(mmc); struct dw_mci *host = slot->host; + const struct dw_mci_drv_data *drv_data = host->drv_data; int reset; if (host->use_dma == TRANS_MODE_IDMAC) @@ -1626,6 +1627,11 @@ static void dw_mci_hw_reset(struct mmc_host *mmc) SDMMC_CTRL_FIFO_RESET)) return; + if (drv_data && drv_data->hw_reset) { + drv_data->hw_reset(host); + return; + } + /* * According to eMMC spec, card reset procedure: * tRstW >= 1us: RST_n pulse width diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f7ca..1b86531a485c 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -565,6 +565,7 @@ struct dw_mci_slot { * @execute_tuning: implementation specific tuning procedure. * @set_data_timeout: implementation specific timeout. * @get_drto_clks: implementation specific cycle count for data read timeout. + * @hw_reset: implementation specific HW reset. * * Provide controller implementation specific extensions. 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230034)(376008)(1800799018)(82310400020)(36860700007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 22:53:00.6651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50a7f900-cce9-41ac-61bb-08dc8b32691f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9128 The eMMC RST_N register is implemented as secure register on BlueField SoC and controlled by ATF. This commit sends SMC call to ATF for the eMMC HW reset. Reviewed-by: David Thompson Signed-off-by: Liming Sun --- drivers/mmc/host/dw_mmc-bluefield.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-bluefield.c b/drivers/mmc/host/dw_mmc-bluefield.c index 4747e5698f48..24e0b604b405 100644 --- a/drivers/mmc/host/dw_mmc-bluefield.c +++ b/drivers/mmc/host/dw_mmc-bluefield.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Mellanox Technologies. */ +#include #include #include #include @@ -20,6 +21,9 @@ #define BLUEFIELD_UHS_REG_EXT_SAMPLE 2 #define BLUEFIELD_UHS_REG_EXT_DRIVE 4 +/* SMC call for RST_N */ +#define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 + static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios *ios) { u32 reg; @@ -34,8 +38,20 @@ static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios *ios) mci_writel(host, UHS_REG_EXT, reg); } +static void dw_mci_bluefield_hw_reset(struct dw_mci *host) +{ + struct arm_smccc_res res = { 0 }; + + arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, + &res); + + if (res.a0) + pr_err("RST_N failed.\n"); +} + static const struct dw_mci_drv_data bluefield_drv_data = { - .set_ios = dw_mci_bluefield_set_ios + .set_ios = dw_mci_bluefield_set_ios, + .hw_reset = dw_mci_bluefield_hw_reset }; static const struct of_device_id dw_mci_bluefield_match[] = {