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Signed-off-by: Srinivas Kandagatla --- .../pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..3968a363aa51 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM4250 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC. + +properties: + compatible: + const: qcom,sm4250-lpass-lpi-pinctrl + + reg: + maxItems: 2 + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm4250-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm4250-lpass-state" + additionalProperties: false + +$defs: + qcom-sm4250-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|1[0-8])$" + minItems: 1 + maxItems: 19 + + function: + enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, + dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a, + ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws, + i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk, + swr_wsa_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@a7c0000 { + compatible = "qcom,sm4250-lpass-lpi-pinctrl"; + reg = <0xa7c0000 0x20000>, + <0xa950000 0x10000>; + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 19>; + + i2s2-active-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio12"; + function = "i2s2_data"; + drive-strength = <2>; + slew-rate = <1>; + }; + }; + + i2s2-sleep-clk-state { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; From patchwork Wed Jun 12 11:55:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 803674 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0173A16F27F for ; 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Wed, 12 Jun 2024 04:56:08 -0700 (PDT) Received: from [192.168.1.195] ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f2f8bd62esm275762266b.141.2024.06.12.04.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 04:56:07 -0700 (PDT) From: Srinivas Kandagatla Date: Wed, 12 Jun 2024 12:55:45 +0100 Subject: [PATCH v2 2/2] pinctrl: qcom: Introduce SM4250 LPI pinctrl driver Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240612-sm4250-lpi-v1-2-f19c33e1cc6e@linaro.org> References: <20240612-sm4250-lpi-v1-0-f19c33e1cc6e@linaro.org> In-Reply-To: <20240612-sm4250-lpi-v1-0-f19c33e1cc6e@linaro.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 236 ++++++++++++++++++++++++ 3 files changed, 246 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 24619e80b2cc..dd9bbe8f3e11 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SM4250_LPASS_LPI + tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform. + config PINCTRL_SM6115_LPASS_LPI tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index e2e76071d268..eb04297b6388 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o +obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c new file mode 100644 index 000000000000..2d2c636a3e20 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_ext_mclk0_a, + LPI_MUX_ext_mclk0_b, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qup_io_00, + LPI_MUX_qup_io_01, + LPI_MUX_qup_io_05, + LPI_MUX_qup_io_10, + LPI_MUX_qup_io_11, + LPI_MUX_qup_io_25, + LPI_MUX_qup_io_21, + LPI_MUX_qup_io_26, + LPI_MUX_qup_io_31, + LPI_MUX_qup_io_36, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_slim_clk, + LPI_MUX_slim_data, + LPI_MUX_sync_out, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_swr_wsa_clk, + LPI_MUX_swr_wsa_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sm4250_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), +}; + +static const char * const dmic01_clk_groups[] = { "gpio6" }; +static const char * const dmic01_data_groups[] = { "gpio7" }; +static const char * const dmic23_clk_groups[] = { "gpio8" }; +static const char * const dmic23_data_groups[] = { "gpio9" }; +static const char * const dmic4_clk_groups[] = { "gpio10" }; +static const char * const dmic4_data_groups[] = { "gpio11" }; +static const char * const ext_mclk0_a_groups[] = { "gpio13" }; +static const char * const ext_mclk0_b_groups[] = { "gpio5" }; +static const char * const ext_mclk1_a_groups[] = { "gpio18" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const ext_mclk1_c_groups[] = { "gpio17" }; +static const char * const slim_clk_groups[] = { "gpio14" }; +static const char * const slim_data_groups[] = { "gpio15" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s3_clk_groups[] = { "gpio14" }; +static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] = { "gpio15" }; +static const char * const qup_io_00_groups[] = { "gpio19" }; +static const char * const qup_io_01_groups[] = { "gpio21" }; +static const char * const qup_io_05_groups[] = { "gpio23" }; +static const char * const qup_io_10_groups[] = { "gpio20" }; +static const char * const qup_io_11_groups[] = { "gpio22" }; +static const char * const qup_io_25_groups[] = { "gpio23" }; +static const char * const qup_io_21_groups[] = { "gpio25" }; +static const char * const qup_io_26_groups[] = { "gpio25" }; +static const char * const qup_io_31_groups[] = { "gpio26" }; +static const char * const qup_io_36_groups[] = { "gpio26" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const sync_out_groups[] = { "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26"}; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" }; +static const char * const swr_wsa_clk_groups[] = { "gpio10" }; +static const char * const swr_wsa_data_groups[] = { "gpio11" }; + + +static const struct lpi_pingroup sm4250_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk0_b, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, swr_wsa_clk, dmic4_clk, _), + LPI_PINGROUP(11, 18, i2s2_ws, swr_wsa_data, dmic4_data, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic23_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic23_data, i2s2_data, ext_mclk0_a, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, slim_clk, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, slim_data, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, ext_mclk1_c, _, _), + LPI_PINGROUP(18, 20, ext_mclk1_a, swr_rx_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, qup_io_00, sync_out, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, qup_io_10, sync_out, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, qup_io_01, sync_out, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, qup_io_11, sync_out, _, _), + LPI_PINGROUP(23, LPI_NO_SLEW, qup_io_25, qup_io_05, sync_out, _), + LPI_PINGROUP(25, LPI_NO_SLEW, qup_io_26, qup_io_21, sync_out, _), + LPI_PINGROUP(26, LPI_NO_SLEW, qup_io_36, qup_io_31, sync_out, _), +}; + +static const struct lpi_function sm4250_functions[] = { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(ext_mclk0_a), + LPI_FUNCTION(ext_mclk0_b), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qup_io_00), + LPI_FUNCTION(qup_io_01), + LPI_FUNCTION(qup_io_05), + LPI_FUNCTION(qup_io_10), + LPI_FUNCTION(qup_io_11), + LPI_FUNCTION(qup_io_25), + LPI_FUNCTION(qup_io_21), + LPI_FUNCTION(qup_io_26), + LPI_FUNCTION(qup_io_31), + LPI_FUNCTION(qup_io_36), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(slim_clk), + LPI_FUNCTION(slim_data), + LPI_FUNCTION(sync_out), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(swr_wsa_clk), + LPI_FUNCTION(swr_wsa_data), +}; + +static const struct lpi_pinctrl_variant_data sm4250_lpi_data = { + .pins = sm4250_lpi_pins, + .npins = ARRAY_SIZE(sm4250_lpi_pins), + .groups = sm4250_groups, + .ngroups = ARRAY_SIZE(sm4250_groups), + .functions = sm4250_functions, + .nfunctions = ARRAY_SIZE(sm4250_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { .compatible = "qcom,sm4250-lpass-lpi-pinctrl", .data = &sm4250_lpi_data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm4250-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove_new = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM4250 LPI GPIO pin control driver"); +MODULE_AUTHOR("Srinivas Kandagatla "); +MODULE_LICENSE("GPL");