From patchwork Tue Oct 22 13:22:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177157 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4858832ill; Tue, 22 Oct 2019 06:23:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqyCI6jwrlRyT8cuPHVgXhqLdrtonjM6CTSp8gWDDkd5SbiuiUoGTGq3A6K8gPo1ZYkhUdUq X-Received: by 2002:a50:ef0d:: with SMTP id m13mr8442770eds.210.1571750609921; Tue, 22 Oct 2019 06:23:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571750609; cv=none; d=google.com; s=arc-20160816; b=P/+KH7RI06p3dxpqKv9rnq21brXBU2/HhEIg1e+s/NLug0RyyTZii4PzLDcEBADb40 sBQtDsVjBytgvLeuY/Y3Tl7P87UzWTUCWPIs9fxIRfg6DndW4pU0SJ/18hG/m9Vuu4fa CTmvOGwinNU7+a3+hh1oLlq5Iysq326BcXlZOqH33EYEBlULx1ALGjy2qnutxB2Lc35Y 63ZjmWaJEfJjHflXD8xSVquaqAJPsw4DOw78+543HkAtiZlAbw94tM2KFnU/zGcbz6UG Jk8s0J5Odd45/5vzLGLKKg7Fh+ze2jFC3LePdNA1bMiKaaf6kTEEuFg+eu7/L8XrP4gF 0O4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=IjFogRcV5VPblbZbB1hDvqvhqSLBqIveS+AehjX8pis=; b=S4lTJ/RSKGO4RBNQ5+Df/x8gjVyO4XFJlo6pCzgDA+7JtaRPVL6qQ4dQOprqlvLlNc 47FQGWiMw6GIvTWXirL4jPZZ80n6E6leOZxrfJWLhKCg8j+cvhXrF278fNtHDXecN1cK RLkKIW4c1skW433fXVUzeA4RIUyr1b6db1FVMcgUe8N/zb4+xzl8m/XyuOgvv6NQ6Q/d OMwDFXhM4MfCvl6qbUEqgjQSUN2eAuACud+sFYNq/DISj252lgINb5b0V/j6HYXxJ81d PNl2kchdnb6KDNkKXb1k46FKyHohXGNJeI1mkPj0nGm1tI4UKKp7XGPdu8ljAHH2GYR2 /f2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MhoFLSVq; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q1si12619641edj.354.2019.10.22.06.23.29; Tue, 22 Oct 2019 06:23:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MhoFLSVq; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731900AbfJVNX3 (ORCPT + 8 others); Tue, 22 Oct 2019 09:23:29 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:42626 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728346AbfJVNX3 (ORCPT ); Tue, 22 Oct 2019 09:23:29 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9MDNROO087130; Tue, 22 Oct 2019 08:23:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571750607; bh=IjFogRcV5VPblbZbB1hDvqvhqSLBqIveS+AehjX8pis=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MhoFLSVqvtpPys7QuSBA59p1W8YLj77oQ93Sy2Yhc3QFXGCEYXYUiqpTtkVo06Vec KWjo2LjCONXFgTfmPnmYFdgzvd2aCd3hHnI9ypXfBjNoId94jMGdM+y7F9vw7QeofR PBP9i0f2oa5nwUhTuRRG2790UVfIfPyvZ9xlNXUc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9MDNC5p068138 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Oct 2019 08:23:12 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 22 Oct 2019 08:23:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 22 Oct 2019 08:23:11 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9MDMplZ126427; Tue, 22 Oct 2019 08:22:54 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH 1/3] phy: cadence: Sierra: add phy_reset hook Date: Tue, 22 Oct 2019 16:22:47 +0300 Message-ID: <20191022132249.869-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191022132249.869-1-rogerq@ti.com> References: <20191022132249.869-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is required if type C driver needs to hold global reset on J7ES to perform LN10 swap. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index affede8c4368..e6d27bdec22a 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -339,10 +339,20 @@ static int cdns_sierra_phy_off(struct phy *gphy) return reset_control_assert(ins->lnk_rst); } +static int cdns_sierra_phy_reset(struct phy *gphy) +{ + struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); + + reset_control_assert(sp->phy_rst); + reset_control_deassert(sp->phy_rst); + return 0; +}; + static const struct phy_ops ops = { .init = cdns_sierra_phy_init, .power_on = cdns_sierra_phy_on, .power_off = cdns_sierra_phy_off, + .reset = cdns_sierra_phy_reset, .owner = THIS_MODULE, }; From patchwork Tue Oct 22 13:22:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177156 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4858552ill; Tue, 22 Oct 2019 06:23:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqxb7Ve7ahm26PM0BombPZlumMqYIZeAhEJSkplsj7BkvFdXMzlZiLPZBq6pWgIdg4Muwo+D X-Received: by 2002:a17:906:6bcd:: with SMTP id t13mr16384879ejs.231.1571750597836; Tue, 22 Oct 2019 06:23:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571750597; cv=none; d=google.com; s=arc-20160816; b=LgXw0iOymjhr7X6ZLgV1wSKXdAJEii1Dmz+nvAE8s6spr0c7RSf7ndOrcsSL27fe03 GTstC4o8dMlFlUW4j7JrMcIJjZH9rxtwIxZ/CLFyVVRdD8yldEoDw08oP74AcEIjfOJH 9Wwqmhzq4J/sGSy2/wsJUUmLBcRX9RYe8H218JNv1thPNwyB1WcKCwCTOwI2SVPje/le xjqom1sjWLzq5cqdpQhKVDh/3+/g28M31mKws1geI2+Ba93ncgMV4D+Wz9FD/ktFChIW K0vFxrIKff9ZGkdr3P9aie0RfLIPrH72RGG7t+URYu5VYDv+Bqtp8u39gj4xo50+pJm7 J0cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=gR7OAXsQc4OiOhV7DWYE58CP8SVL3y7X8+jWjC3qNZ0=; b=x8ptS5qOom90zoVH1PYAqokSuotBrzBoLWNzvfh0bqIR83KRB2JCs50l3m2hINrp7V NwtDBPpsZUN4lYA8kwcF0aoqj2A/vBzrfXceLgMkE0s9vdDSi8i01lA+YssHmNUQUE3Q 8d4r4BPn+3RtOmsU8EaqVg4iVQfXAYGiKenzp6COK51EOIa5AKsQZzGDrhBul3yArLb7 sppSH6M+F3g7Zglq5KGY979RJ/aiX0rtmL8RpJ0vdO0PYgCZnqSNB+iAHH5oDvza6QkS /hklOMaNi9+rb0F/m87BW1QDF8XcFAQNbSnPU7TvUXb4uGpZHAmv3faC9oY4G1w0EPNx SyUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KZY93pcE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ck18si10549547ejb.300.2019.10.22.06.23.17; Tue, 22 Oct 2019 06:23:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KZY93pcE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387997AbfJVNXR (ORCPT + 8 others); Tue, 22 Oct 2019 09:23:17 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:32930 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387966AbfJVNXQ (ORCPT ); Tue, 22 Oct 2019 09:23:16 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9MDNEtS003725; Tue, 22 Oct 2019 08:23:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571750594; bh=gR7OAXsQc4OiOhV7DWYE58CP8SVL3y7X8+jWjC3qNZ0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KZY93pcExSDQEi9oLzUIIiXl5q/7TsnHy7jPRnKLrHCT/ic5AslsO5BpI+RJWXNSz UzZ6hLRY1vnJdVC4MEM4vE9oC56pDT12OHWZSac9Jnze3/RXTEE7PxoAD9cWAeUY6c rVjbxsMV93eHx9x6tavZtyC4A6WmRRQh98BHdcqY= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9MDNEc6068197 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Oct 2019 08:23:14 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 22 Oct 2019 08:23:13 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 22 Oct 2019 08:23:04 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9MDMpla126427; Tue, 22 Oct 2019 08:22:56 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH 2/3] dt-bindings: phy: ti, phy-j721e-wiz: Add Type-C dir GPIO Date: Tue, 22 Oct 2019 16:22:48 +0300 Message-ID: <20191022132249.869-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191022132249.869-1-rogerq@ti.com> References: <20191022132249.869-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is an optional GPIO, if specified will be used to swap lane 0 and lane 1 based on GPIO status. This is required to achieve plug flip support for USB Type-C. Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Allow the DT node to specify the time (in ms) that we need to wait before sampling the DIR line. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.txt | 9 +++++++++ 1 file changed, 9 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt index 19b4c3e855d6..253535a8819f 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt @@ -24,6 +24,15 @@ Optional properties: assigned-clocks and assigned-clock-parents: As documented in the generic clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt + - typec-dir-gpios: GPIO to signal Type-C cable orientation for lane swap. + If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to + achieve the funtionality of an exernal type-C plug flip mux. + + - typec-dir-debounce: Number of milliseconds to wait before sampling + typec-dir-gpio. If not specified, the GPIO will be sampled ASAP. + Type-C spec states minimum CC pin debounce of 100 ms and maximum + of 200 ms. + Required subnodes: - Clock Subnode: WIZ node should have '3' subnodes for each of the clock selects it supports. The clock subnodes should have the following names From patchwork Tue Oct 22 13:22:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177158 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4859250ill; Tue, 22 Oct 2019 06:23:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqzoSxPkf67gXiupwEznzR2AByCJ8hieLdgzoggFI/W6YbUK3SAmq1vkmwuGzrolOMcgoFVI X-Received: by 2002:a17:906:743:: with SMTP id z3mr3897472ejb.142.1571750630311; Tue, 22 Oct 2019 06:23:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571750630; cv=none; d=google.com; s=arc-20160816; b=uYiT9DCqBmhtxzqI0PoLM+aZRP8Axvc8uk1HUc46svG6WoNfjBnGBsUxLCEtIhlTug pdcoUlEjMn3JMh8WY8ccFdOxWY0WMhjMX3VAbfXhyVXZQz3NBItctOovnDJBYTxtKOjY oMF5ThgdXUjKQCmFfCspB8Y8nZJjd1b/n0bncIL960ZNBr1mCUFYHx+Xjf7DOZlCZaOk GDBl7dhr65qOR3x8aZoLsda2Hv524qDyroIv2tUkWazmcBY02Z3VnKg37kWf4FP76nzU GWCSzJg7c+gfhxR7LOslvuEvdW1uh5Gn7i5X5AYDsA0/E2QenDe8k/h/6TjTAFfnWn/S 2PJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WDj6QPyW6ZuJ8MWf4ORoc/EmksLmyGtH8kZua5ibgLg=; b=HOge6KLbCb7vmsC5nMfFdehGFaUiBe5GhP74OSPJtQVvIAq9BiJG5dqap6UwClhTn8 SLDSraz4NavE3sAy2vytCmuYuGNTx2L/wOY0CUapnsCPuHMlljkYdosUCLqlaPUVAPiB THIqygDcOCVDPExb/kGw5STPSoPO5hzd16Qpcrjl1qqGFvKuzwFxzMH5HxYOsEbaLI7P Qb2JrzU13q69qdCb3eTa5RHiZOagOtOJM3gL0LFcJn9J+zdCe0tSDWaCTTKwsK2XedT9 JUubGUVn/J6DCV3XtOxFrRz6MV9k67zitli7ATfMnVAvhMu2hgDT2SR4r+5Mmz6AcWd2 ndlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fhnLAxHZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h34si12840505ede.247.2019.10.22.06.23.50; Tue, 22 Oct 2019 06:23:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fhnLAxHZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389235AbfJVNXt (ORCPT + 8 others); Tue, 22 Oct 2019 09:23:49 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33030 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389226AbfJVNXt (ORCPT ); Tue, 22 Oct 2019 09:23:49 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9MDNkTf003907; Tue, 22 Oct 2019 08:23:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571750626; bh=WDj6QPyW6ZuJ8MWf4ORoc/EmksLmyGtH8kZua5ibgLg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fhnLAxHZYDfYYM2OyO/UElKIsrskrnSj2aYhKyL6+3N3VO1pG7j4DvU8vlBBjTzVM 1xSO4d2lsSsAx72glZk7CP2EC7lWk9i6Y0RLP90bAtZtfh86I0VLgv0AX1uTTHb2lY qrbGY09KeuZVPXeHHDpGd/ZKmihcqDIjdpzICJZw= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9MDNVbd068725 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Oct 2019 08:23:31 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 22 Oct 2019 08:23:21 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 22 Oct 2019 08:23:30 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9MDMplb126427; Tue, 22 Oct 2019 08:22:58 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH 3/3] phy: ti: j721e-wiz: Manage typec-gpio-dir Date: Tue, 22 Oct 2019 16:22:49 +0300 Message-ID: <20191022132249.869-4-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191022132249.869-1-rogerq@ti.com> References: <20191022132249.869-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- drivers/phy/ti/phy-j721e-wiz.c | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 2a95da843e9f..2becdbcb762a 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -22,6 +24,7 @@ #define WIZ_SERDES_CTRL 0x404 #define WIZ_SERDES_TOP_CTRL 0x408 #define WIZ_SERDES_RST 0x40c +#define WIZ_SERDES_TYPEC 0x410 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) #define WIZ_MAX_LANES 4 @@ -29,6 +32,8 @@ #define WIZ_DIV_NUM_CLOCKS_16G 2 #define WIZ_DIV_NUM_CLOCKS_10G 1 +#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) + enum wiz_lane_standard_mode { LANE_MODE_GEN1, LANE_MODE_GEN2, @@ -206,6 +211,8 @@ struct wiz { u32 num_lanes; struct platform_device *serdes_pdev; struct reset_controller_dev wiz_phy_reset_dev; + struct gpio_desc *gpio_typec_dir; + int typec_dir_delay; }; static int wiz_reset(struct wiz *wiz) @@ -703,6 +710,21 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, struct wiz *wiz = dev_get_drvdata(dev); int ret; + /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ + if (id == 0 && wiz->gpio_typec_dir) { + if (wiz->typec_dir_delay) + msleep_interruptible(wiz->typec_dir_delay); + + if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, + WIZ_SERDES_TYPEC_LN10_SWAP); + } else { + regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, + WIZ_SERDES_TYPEC_LN10_SWAP, 0); + } + } + if (id == 0) { ret = regmap_field_write(wiz->phy_reset_n, true); return ret; @@ -789,6 +811,25 @@ static int wiz_probe(struct platform_device *pdev) goto err_addr_to_resource; } + wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", + GPIOD_IN); + if (IS_ERR(wiz->gpio_typec_dir)) { + ret = PTR_ERR(wiz->gpio_typec_dir); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to request typec-dir gpio: %d\n", + ret); + goto err_addr_to_resource; + } + + if (wiz->gpio_typec_dir) { + ret = of_property_read_u32(node, "typec-dir-debounce", + &wiz->typec_dir_delay); + if (ret && ret != -EINVAL) { + dev_err(dev, "Invalid typec-dir-debounce property\n"); + goto err_addr_to_resource; + } + } + wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes;