From patchwork Thu Jun 6 06:04:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802433 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A2944361; Thu, 6 Jun 2024 06:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717654438; cv=none; b=LBDTWllKfEqsncx1kMgxGAUnIam33J53NEAJxC+13GghFjLSRyMJf8HzJkHbaKMruLxev5RLS7/WdqKfkdqF6hNbaTGHzCtaHSpmMV45PhNFdIChUc/p1elZ3uWHGmPYu61kksAY1icT8A93SAQxEkoV4mi46QYfQsF4eNtEraM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717654438; c=relaxed/simple; bh=jePjYwzuWCmU1CZ9/Yom3hqaS1sdLARMt2yKSuKSyTM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CdeflIGusEx8RQCfihL2dkPugrVSuL82q6HpOBAYxmxrkN2foBCSK5dxo1DcemVmLx2ZPo1midFz0cXvdtH4vRpqrQ1/YQ4S6GykKmAQaTc+ps+4dkEs84OanT2nqG1E6I3rtqkvVkuSi8pg/c6tyKt7OUdqj8fb0/o2t4czyiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=sQyl9k2s; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="sQyl9k2s" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717653885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SJyrvJEgIUfczl/GlGYofH0Vf0eBCOnBoq6FdTDHbXo=; b=sQyl9k2s0D2SH6FdsfLkix0QKLdkdaz/12yR2F0BtoD3a0vC2Bsq9F/lXmo77blf507v5V W4dU28yVFLH59Xp+stzowAfar160U97QNsqZjBtC0fb5aQ+sGjjYc0a+KgLXGZduWhZrOc Zq7hKtNo61+NEEiR1XgsbxDg9h6U2P8= To: Linus Walleij , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH 1/3] pinctrl: rockchip: fix RK3328 pinmux bits Date: Thu, 6 Jun 2024 14:04:33 +0800 Message-ID: <20240606060435.765716-2-i@mail.eh5.me> In-Reply-To: <20240606060435.765716-1-i@eh5.me> References: <20240606060435.765716-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is recalculated so it remain unchanged. The pinmux bits for GPIO3-B1 to GPIO3-B6 have different register offset than common rockhip pinmux, set the correct value for those pins in rk3328_mux_recalced_data. The pinmux bits for those pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions, e.g. IO_SPIclkm0_GPIO2B0vccio5 with GRF_GPIO2B_IOMUX[1:0]=2'b01 setting. This fix has been tested on NanoPi R2S for fixing confliting pinmux bits between GPIO2-15 with GPIO2-13. Signed-off-by: Huang-Huang Bao --- drivers/pinctrl/pinctrl-rockchip.c | 59 ++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 3bedf36a0019..23531ea0d088 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -634,23 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -3763,7 +3808,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + 0, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", From patchwork Thu Jun 6 06:04:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802137 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D6C48821; Thu, 6 Jun 2024 06:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717653896; cv=none; b=oKlaor8UDRrtHFK6C3HYi8ALa9AcnZIFOthZH9/GBJTpBgLU2arMVGnV6T+fMseuMnJXX5C7woufTXYIkU3bQixBIsu11FSG7AVbHencyA0/4+BD/fZsxBqhNJw5jEEO8K2cHZC3PfRcZj3YsX6qR4FwWFn3BjBCZ2CvAnyckpU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717653896; c=relaxed/simple; bh=v8/ma7BpGBftxWXl1+PFhZJskdJ03bvSfLJ5cHT8Hpk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sy+V1nNvMCUQzxBF1F8AI9MZrKBPZPcnsq84fFsMnfoij1lmxudQFkLcxgx6WgOy7HN4sVfbBu/20zjWN8/SbCdEaGe3Dl3fIQKrxyVMDdHWvEh2V+Rea2hhqXx+UgKEJLegJnoqxTD6LVWYr7avONQvfOmWlumoR3PeLtSlna4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=bl/uTMwt; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="bl/uTMwt" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717653892; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Fk/BOxyCTjOzgG9SEUwbMyLuyPityyyids3LNWp9eDw=; b=bl/uTMwtS7fyjNqS2GWxVWJM+NAQ0MgTEAHJnskm600p2zmz0PYWrsFYanw+txeeJXnGwB LIFRYq3ahrVTl2jQbCjlwSWORHrEJdRwZ1hzs7Y7fKcjSQomGxxCb0RgwEaFecliTR8fjV L3jgMQi3X2X8VMEfNNBmaUDLCJ1VwFg= To: Linus Walleij , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH 2/3] pinctrl: rockchip: use dedicated pinctrl type for RK3328 Date: Thu, 6 Jun 2024 14:04:34 +0800 Message-ID: <20240606060435.765716-3-i@mail.eh5.me> In-Reply-To: <20240606060435.765716-1-i@eh5.me> References: <20240606060435.765716-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 rk3328_pin_ctrl uses type of RK3288 which has a hack in rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6 at assume, the hack is not applicable to RK3328 as GPIO6 is not even exist in it. So use a dedicated pinctrl type to skip this hack. Signed-off-by: Huang-Huang Bao --- drivers/pinctrl/pinctrl-rockchip.c | 5 ++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 23531ea0d088..24ee88863ce3 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2478,6 +2478,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3188: case RK3288: case RK3308: + case RK3328: case RK3368: case RK3399: case RK3568: @@ -2536,6 +2537,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3188: case RK3288: case RK3308: + case RK3328: case RK3368: case RK3399: case RK3568: @@ -2798,6 +2800,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3188: case RK3288: case RK3308: + case RK3328: case RK3368: case RK3399: case RK3568: @@ -3822,7 +3825,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), .label = "RK3328-GPIO", - .type = RK3288, + .type = RK3328, .grf_mux_offset = 0x0, .iomux_recalced = rk3328_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 4759f336941e..849266f8b191 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -193,6 +193,7 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3328, RK3368, RK3399, RK3568, From patchwork Thu Jun 6 06:04:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802434 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 977843CF73; Thu, 6 Jun 2024 06:04:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717653898; cv=none; b=Hs9+Z5bVz7mPIxJgVnjccUeQFlv6wSlP1XU2/Lm+TRN4424OlqcLYXu10kv86AfqRF8gSytS+D6ZVo03rQpw504nPcTFnLt8Ep8JyaFxVvQ48+95ReVN9/r4mt3nZef/onlsV3ux5WAiJz28v+CjO6hzwbzsjs1LhTA94IsjW/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717653898; c=relaxed/simple; bh=OC/RhDqa8lH6HIJpNtL1mzMJHdYoAMzeaF3gHTb9Itw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cHcORKYRz1yBWqUKdskee7BDFQrxUynqz+wtddgcec0WFNPGsogX7itzncCRyI7h5fbG2fU98foXiQxdNQLNfCfx/GF4h2EAhT258FpLg4w9j3M9+fgvJQ8sZTiqSRHJlXDs1fTfBYe1VAIXQDJqEXRl6Bs1nBHq0vX35PaCFuY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=N0OHZzx7; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="N0OHZzx7" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717653895; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zzFshImQcnkQaOjfbtCDV/5BL1a1t8gOqnWdgJ2CXJI=; b=N0OHZzx7klyLzoJpE6VsKhaSkWRTjimHDHLLqjdY+5zHf4EppQoK2GFyIC31o3a7LsV7I5 SN1aoJH9l37P2YBEV6iBEDTMykibsYsvpt2EtgCLhB5c6wxDRSsbL7flOjxPH8ZCEsc7SO GcpLjlGiQHeIetHlWD+QvfIr1MwPkk0= To: Linus Walleij , Heiko Stuebner Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH 3/3] pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set Date: Thu, 6 Jun 2024 14:04:35 +0800 Message-ID: <20240606060435.765716-4-i@mail.eh5.me> In-Reply-To: <20240606060435.765716-1-i@eh5.me> References: <20240606060435.765716-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error, add missing bank data retrieval in that code to avoid setting mux on unexpected pins. Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux") Signed-off-by: Huang-Huang Bao --- drivers/pinctrl/pinctrl-rockchip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 24ee88863ce3..3f56991f5b89 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2751,8 +2751,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (ret) { /* revert the already done pin settings */ - for (cnt--; cnt >= 0; cnt--) + for (cnt--; cnt >= 0; cnt--) { + bank = pin_to_bank(info, pins[cnt]); rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); + } return ret; }