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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400017)(1800799015)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2024 05:08:56.9376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc66be14-f857-4075-6a9d-08dc851d9a67 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4164 PMU event filter test fails on zen4 architecture because of the unavailability of family and model check for zen4 in use_amd_pmu(). use_amd_pmu() is added to detect architectures that supports event select 0xc2 umask 0 as "retired branch instructions". Model ranges in is_zen1(), is_zen2() and is_zen3() are used only for sever SOCs, so they might not cover all the model ranges which supports retired branch instructions. X86_FEATURE_ZEN is a synthetic feature flag specifically added to recognize all Zen generations by commit 232afb557835d ("x86/CPU/AMD: Add X86_FEATURE_ZEN1"). init_amd_zen_common() uses family >= 0x17 check to enable X86_FEATURE_ZEN. Family 17h+ is where Zen and its successors start and that event 0xc2,0 is supported on all currently released F17h+ processors as branch instruction retired and it is true going forward to maintain the backward compatibility for the branch instruction retired. Since X86_FEATURE_ZEN is not recognized in selftest framework, instead of checking family and model value for all zen architecture, "family >= 0x17" check is added in use_amd_pmu(). Fixes: bef9a701f3eb ("selftests: kvm/x86: Add test for KVM_SET_PMU_EVENT_FILTER") Suggested-by: Sandipan Das Signed-off-by: Manali Shukla --- .../kvm/x86_64/pmu_event_filter_test.c | 32 +++---------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c index 26b3e7efe5dd..f65033fab0c0 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c @@ -353,38 +353,16 @@ static bool use_intel_pmu(void) kvm_pmu_has(X86_PMU_FEATURE_BRANCH_INSNS_RETIRED); } -static bool is_zen1(uint32_t family, uint32_t model) -{ - return family == 0x17 && model <= 0x0f; -} - -static bool is_zen2(uint32_t family, uint32_t model) -{ - return family == 0x17 && model >= 0x30 && model <= 0x3f; -} - -static bool is_zen3(uint32_t family, uint32_t model) -{ - return family == 0x19 && model <= 0x0f; -} - /* - * Determining AMD support for a PMU event requires consulting the AMD - * PPR for the CPU or reference material derived therefrom. The AMD - * test code herein has been verified to work on Zen1, Zen2, and Zen3. - * - * Feel free to add more AMD CPUs that are documented to support event - * select 0xc2 umask 0 as "retired branch instructions." + * Family 17h+ is where Zen and its successors start and that event + * 0xc2,0 is supported on all currently released F17h+ processors as + * branch instruction retired and it is true going forward to maintain + * the backward compatibility for the branch instruction retired. */ static bool use_amd_pmu(void) { uint32_t family = kvm_cpu_family(); - uint32_t model = kvm_cpu_model(); - - return host_cpu_is_amd && - (is_zen1(family, model) || - is_zen2(family, model) || - is_zen3(family, model)); + return family >= 0x17; } /*