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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v2 01/10] target/s390x: Change help_goto_direct to work on displacements Date: Wed, 5 Jun 2024 14:57:30 -0700 Message-Id: <20240605215739.4758-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for CF_PCREL, reduce reliance on absolute values. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index c81e035dea..f25ae02a4e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1073,13 +1073,15 @@ struct DisasInsn { /* ====================================================================== */ /* Miscellaneous helpers, used by several operations. */ -static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) +static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + uint64_t dest = s->base.pc_next + disp; + update_cc_op(s); per_breaking_event(s); per_branch(s, tcg_constant_i64(dest)); - if (dest == s->pc_tmp) { + if (disp == s->ilen) { return DISAS_NEXT; } if (use_goto_tb(s, dest)) { @@ -1105,7 +1107,8 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { - uint64_t dest = s->base.pc_next + (int64_t)imm * 2; + int64_t disp = (int64_t)imm * 2; + uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1120,7 +1123,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, if (c->cond == TCG_COND_ALWAYS || (dest == s->pc_tmp && !(s->base.tb->flags & FLAG_MASK_PER_BRANCH))) { - return help_goto_direct(s, dest); + return help_goto_direct(s, disp); } } else { if (!cdest) { From patchwork Wed Jun 5 21:57:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801654 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48330wrv; Wed, 5 Jun 2024 14:59:10 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWsdgVuIk2+Sp1GpjLfSZN9I7BdgYpfoJ3wvPf0yp6KDROWaWnjhflh+RG+0BvlcWngHHDwUoXCYj+qsscPJ6Vx X-Google-Smtp-Source: AGHT+IGJBLjXhr6hp9157tuPjoEeb9OAXU8/2nGZmlKZmbESR5GVfZeig1y9Gqt44FuZ3ZiM2Lc+ X-Received: by 2002:a05:6808:6187:b0:3d1:d0cc:9230 with SMTP id 5614622812f47-3d2044d9fb1mr4093391b6e.50.1717624750593; Wed, 05 Jun 2024 14:59:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624750; cv=none; d=google.com; s=arc-20160816; b=mXHI038Q43bNRyVlDGQHejLqf388gR6PqYUOYJk1ly8HBf+8RpeZCb6KdJKbDEnZJk Yk3wCon0jlYCurf+HWkzaUxCN2OYRPsnnLQlAIJywSVrKSQ6Z2CmWr9RiQVnvMOevMmt Z4nrTo3M8QW8eSMdZhVim6HpH+P2RzP5huNA3vEQc27fnhNhrE7jppLt9iBvj9C5wF4m NW4DSizu3adyIdTSOU6keSR+O09GkrIxFbgTiKWpbbGt5ulNoKcBvdfhmtRfGTmZyvRc 32a2T3BS3v5p7Mgr3TJYSaY1w6dVzPqdY55r4GVe7f2GgKSqW0A/bMeJbsdejvwJrlsf SdGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JhUXFhxALhRCHAx9BQm8y0zAn9EGdu513/wa3HnMCCc=; fh=2xkb1hkZON85aQlY8H6YQD8NjCAJw799l8+ye3ZWOCA=; b=nbr2iCMrVCJg7m/RKi7p+dpFldQx5S+qQwDwHGnFWIlm2WwncLyY2NRlfNhaP9+hOq ofmxvHy6XcfgrssenSx8WieCIxXYY7TUxCqfofeAb34DGxYKLnaZiyAU1GlVlFCOH+Ov +kySmuZQyqMF5ab2hwrFdGovvuv3a5cLKzzj7RSC0e7WH1cRbq+N9BAgTF1RdTQ+eALI 7aiAGddzeTDAhIy80VztOWi6lzco2Hfrc/yL3lHfKGJNBEc1btGK9xYmlhnzQD5LJ/l8 KKGqJBbW4QUxyXKNLNeBcr8oQBKUnW4zrNyhQbYjpkVItD4nNciwLIDktYgoSKvyrUny axFQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aogdC3sK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v2 02/10] target/s390x: Introduce gen_psw_addr_disp Date: Wed, 5 Jun 2024 14:57:31 -0700 Message-Id: <20240605215739.4758-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f25ae02a4e..bd4ad33802 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -167,6 +167,11 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + tcg_gen_movi_i64(dest, s->base.pc_next + disp); +} + static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { if (s->base.tb->flags & FLAG_MASK_32) { @@ -337,8 +342,7 @@ static void store_freg32_i64(int reg, TCGv_i64 v) static void update_psw_addr(DisasContext *s) { - /* psw.addr */ - tcg_gen_movi_i64(psw_addr, s->base.pc_next); + gen_psw_addr_disp(s, psw_addr, 0); } static void per_branch(DisasContext *s, TCGv_i64 dest) @@ -352,7 +356,7 @@ static void per_branch(DisasContext *s, TCGv_i64 dest) static void per_breaking_event(DisasContext *s) { - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); } static void update_cc_op(DisasContext *s) @@ -1086,11 +1090,11 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) } if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); return DISAS_PC_CC_UPDATED; } } @@ -1121,7 +1125,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, * still need a conditional call to helper_per_branch. */ if (c->cond == TCG_COND_ALWAYS - || (dest == s->pc_tmp && + || (disp == s->ilen && !(s->base.tb->flags & FLAG_MASK_PER_BRANCH))) { return help_goto_direct(s, disp); } @@ -1154,7 +1158,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch taken. */ per_breaking_event(s); if (is_imm) { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); } else { tcg_gen_mov_i64(psw_addr, cdest); } @@ -1170,7 +1174,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, gen_set_label(lab); /* Branch not taken. */ - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); if (use_goto_tb(s, s->pc_tmp)) { tcg_gen_goto_tb(1); tcg_gen_exit_tb(s->base.tb, 1); @@ -5758,7 +5762,8 @@ static TCGv gen_ri2(DisasContext *s) disas_jdest(s, i2, is_imm, imm, ri2); if (is_imm) { - ri2 = tcg_constant_i64(s->base.pc_next + (int64_t)imm * 2); + ri2 = tcg_temp_new_i64(); + gen_psw_addr_disp(s, ri2, (int64_t)imm * 2); } return ri2; @@ -6367,7 +6372,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) s->base.is_jmp = DISAS_PC_CC_UPDATED; /* fall through */ case DISAS_NEXT: - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); break; default: break; From patchwork Wed Jun 5 21:57:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801653 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48323wrv; 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/10] target/s390x: Remove pc argument to pc_to_link_into Date: Wed, 5 Jun 2024 14:57:32 -0700 Message-Id: <20240605215739.4758-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All callers pass s->pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bd4ad33802..14162769a9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -172,8 +172,10 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) tcg_gen_movi_i64(dest, s->base.pc_next + disp); } -static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { + uint64_t pc = s->pc_tmp; + if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -1404,7 +1406,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o) static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); if (o->in2) { return help_goto_indirect(s, o->in2); } else { @@ -1417,7 +1419,7 @@ static void save_link_info(DisasContext *s, DisasOps *o) TCGv_i64 t; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return; } gen_op_calc_cc(s); @@ -1474,7 +1476,7 @@ static DisasJumpType op_basi(DisasContext *s, DisasOps *o) bool is_imm; int imm; - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); disas_jdest(s, i2, is_imm, imm, o->in2); disas_jcc(s, &c, 0xf); From patchwork Wed Jun 5 21:57:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801655 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48407wrv; Wed, 5 Jun 2024 14:59:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVVbEav2cWG53ObpkKKubS1U+IxCIWkpfwXYyLCJUPn7pUj04R9lr/SPTeR1nI+htUOwsZzLaQU+nj9wuLdGs3x X-Google-Smtp-Source: AGHT+IHfSktsdJXTV6uVX9r+2u+tbGEe0Z9SIG8XzjCstsjcNfZ7hKpcVVHT3M+VZOu6aqMh+Fbt X-Received: by 2002:a05:620a:389c:b0:794:850c:8bcd with SMTP id af79cd13be357-79523fc1e75mr342248585a.58.1717624769042; Wed, 05 Jun 2024 14:59:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624769; cv=none; d=google.com; s=arc-20160816; b=IAvdKmBo4TUqh6MYPRvYu9MVFqoPBhz11gs/ejiIA1p73UrNWuldpONiEfIlKqxCsS ByrmkusMm1emx9HQJO5x9Bnl/kawcIAU4fUL2A9Zo4GH8wm/sB2Ypx7aSSjv8wx/FrH+ Jqz7fORg2EZs/3iwjwhRbvIpFQyrmw5AxMxirc9EpLTN/klagSWj9DoFrg4KKuV3znSs Wh4jXv3kvBoFK7pcc9Jaz6CcLa41WM6oawjRlgGGDUwaij8QCB+vS4bho0EZYOhynKUK 5/z2Vu/vhqo/hElhP1Rsw43NyT1jljlza/Mq977rLJ8dRcvTS7HF2fSMkhyDLsXFp7PU qD0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sQiUj0T/PhZH9aPIOQew7TG39LwQbDZ+11m+rsBXajM=; fh=2xkb1hkZON85aQlY8H6YQD8NjCAJw799l8+ye3ZWOCA=; b=RgOspTKIAUSBLU3MyYVcWnZ1oeAva1+0YOuAslg3zubaLzKXcQ6PsjxDbRzzn6MkN8 +OxsNcPnWz8BLokCWp7VVkqQkdNqp/W4IK0bm8mXcMAAcrZtp6Lu/RVANUlxivs6Xwtx oZAl68/vMxREcBQQzdazelyf5/gvX8ngMMVUOSFi9t1M2ldlKkrcgIjHen4wZQZfDDv7 fJc/JO8Kc0K55peuoKI+TrpxbQ7Ush5fScQkkYiR7sozHZW58d5BbORmHCVw4NMErfA8 7uKrvCjdlSqjF2ZmFHID9jjJndM+UNadpwfboArcuOXRtmIwR3nsvEKf2lYFvP2HwmH1 p0/A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oMrCbql9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v2 04/10] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Date: Wed, 5 Jun 2024 14:57:33 -0700 Message-Id: <20240605215739.4758-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is slightly more complicated than a straight displacement for 31 and 24-bit modes. Dont bother with a cant-happen assert. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 14162769a9..2d611da8af 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -174,17 +174,19 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { - uint64_t pc = s->pc_tmp; + TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { - if (s->base.tb->flags & FLAG_MASK_64) { - tcg_gen_movi_i64(out, pc); - return; - } - pc |= 0x80000000; + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; } - assert(!(s->base.tb->flags & FLAG_MASK_64)); - tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); } static TCGv_i64 psw_addr; From patchwork Wed Jun 5 21:57:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801659 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48453wrv; Wed, 5 Jun 2024 14:59:41 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUaZwMxunf8Q1gy3uru667cTECl72/5U/J5DivHQ7/1JltHQvFdFrmQhXaUaHaG2KsRRrd5xctbtpIRd5o5zGPo X-Google-Smtp-Source: AGHT+IG8Nrb+/XcoABGam6k6aE1IlhMwO0bV8iUyZZn4qBe/IiJpxdtprqFntuDaVS1Bv+ptQ2SH X-Received: by 2002:a0d:dd96:0:b0:615:3858:d154 with SMTP id 00721157ae682-62cbb5050c8mr38874357b3.30.1717624781135; Wed, 05 Jun 2024 14:59:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624781; cv=none; d=google.com; s=arc-20160816; b=Y1/c5b3wCKHbP47Blt5xFPAepMssrHN1y2/OfEdFTCYWlm9hD32VQJ5n0dg4S+Mhpw RWjHH//rH98NhtMc4QOdEbldDRvLqXMD/2r5BjdmuMN3vMCwKeeL5b3v4MFXI9uj+OsN pufMlis8bEHPk5wtTE0c+2v2IFCmj3Wg89X4ppqJfCH37Xz2DblmdKfgA2e85j3oBkEp qOo1CYa57Mu8hTxa+3xtsMbd/ur/ja8rExUHHG8zwCRBXArWr3gzajO9Gi4leE9Eu0/p sbzZ+zB76njhTl6D5okYgs0Q/zB9go+G52HscdTw9LhUDyOpZVcGc+wGi1XlvKD+wUZj RMtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=s+cDoZ/Z/Fl9ZwgY0g7zYp6SY7qoD7tDcn18rcDzdj8=; fh=CW0Ta8GpeRJUzZ93UqDx7Xa7lEW9Yy8JEVTiJP7TQHQ=; b=VHM9Beqt5K1aIa+rnuHswZeqtCnq9uDpnCFxC+h8eN32UT8xsQQ8agIQjjpYNUWz/N eQrxTekAjm7/nBkoxM/2Ogx+uQU6g4FsRA9jV+x9mHvz8A4ykTwLrsQVGZQJl0Swf80g vVjomqvsblDUrdg3YLWVRsjHuegFhnnpDyBKvdjZb/VnxHD1ZHG9xieRjPUHYTmFixbQ bRoFBtSs4S5xxolHfrbczjILqghLNdwfJgXmZWaDvQji1zpI4cEJKMphnA33RdhS9plV 94uF+w5BeAWHNGEHiGuucrkhMuzV0LFTT/B463/HN0lCXRzdy3p6kpS/81oHEi/fCTps 95ng==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LXr/qzz0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/10] target/s390x: Use gen_psw_addr_disp in save_link_info Date: Wed, 5 Jun 2024 14:57:34 -0700 Message-Id: <20240605215739.4758-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Trivial but non-mechanical conversion away from pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2d611da8af..2654c85a8e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1425,9 +1425,11 @@ static void save_link_info(DisasContext *s, DisasOps *o) return; } gen_op_calc_cc(s); - tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); - tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp); t = tcg_temp_new_i64(); + tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); + gen_psw_addr_disp(s, t, s->ilen); + tcg_gen_or_i64(o->out, o->out, t); + tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); tcg_gen_shri_i64(t, psw_mask, 16); tcg_gen_andi_i64(t, t, 0x0f000000); tcg_gen_or_i64(o->out, o->out, t); From patchwork Wed Jun 5 21:57:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801656 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48437wrv; Wed, 5 Jun 2024 14:59:38 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVi3au5YhDEo6z2Nh00giCG/ShuFQFKGaCEenyp0VKkGxrgRBZfSTSSS/nZfUdfBqXRzHC1sSbIXVk70EdrCah4 X-Google-Smtp-Source: AGHT+IEqHX63nyfiULt3AalrQTzNoII2B1/AFbr09He0y09t0EKS0ohkW/HqMNo3bd1UGok6QnV4 X-Received: by 2002:a05:620a:2546:b0:795:195a:1716 with SMTP id af79cd13be357-7952f0d6becmr186782085a.15.1717624778169; Wed, 05 Jun 2024 14:59:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624778; cv=none; d=google.com; s=arc-20160816; b=KQwz27TUCFzkRTZ7owwb4UZIlxj8b8GkbqM3Njvb9Vu5iNJoRJ09/0QpGcXCpFUx8/ YvCqnFQcbPEhrqhl7MLUwNx1L7WPlDWpNzrZ0PJNhG2zLjUYw8HHbXW6lZ0oF5vr37K9 qjW4CdxmCoJkVc2BS+sVv26EjwW2r9SBcNL23DRJy9x9CSHlQPV8VKczYb6rp2WwpdPA bf1lUuXExGhXXhxV7+JsxtfUO2XckIq2STAjC3J8yYXZ4WPn8YWZp+06x7uVCIpxM/5U YI0f95jlRbktqf0LkZX5iMSFOVdENLGS8Rj9cc32k1d0o2evUG57gkwvOK+QlJzRiZP5 3OzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WqJiYcxvLTtBfrkGq1JS6zQ0ORon0JfeSUXl0F2Pjw0=; fh=dBGltRZCelj4V8aBoG+OSD7H6rZxxBGgTNXT/erTiSU=; b=aKxjEkaY+tzAowmbjTFQIF+6QJ4xT4uCbjTLzM8irbCAaluzB4WSveHSJYk0E2OoGB M4I9hZJATL4gpRxFPOJu9nlyBvGkdnYiZyNAJKre/bASi5JSAlatZAY2N5UMqG5G68SR /n+ufYbhApyPhyfpm3eMD7JYZJ3EXxinfhADW3FsQONM2gmw8oitQYYYNd8f2vogBNAe yL2ntTsevvBw9rbPCMO/STN/U77kDgWCwGPCLhHYXqZu7i7T9EeKKW1NELL6zWA1xtQm owlWYt1ywjAh2nrtCA6nFB9LOmvF3zXuOi2M+pnBtZfMe7A71Gg9NzqQZJ5urAAHg22G Bpsw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IJjguOA+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH v2 06/10] target/s390x: Use deposit in save_link_info Date: Wed, 5 Jun 2024 14:57:35 -0700 Message-Id: <20240605215739.4758-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace manual masking and oring with deposits. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2654c85a8e..0f0688424f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1418,24 +1418,32 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) static void save_link_info(DisasContext *s, DisasOps *o) { - TCGv_i64 t; + TCGv_i64 t1, t2; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { pc_to_link_info(o->out, s); return; } + gen_op_calc_cc(s); - t = tcg_temp_new_i64(); - tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); - gen_psw_addr_disp(s, t, s->ilen); - tcg_gen_or_i64(o->out, o->out, t); - tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); - tcg_gen_shri_i64(t, psw_mask, 16); - tcg_gen_andi_i64(t, t, 0x0f000000); - tcg_gen_or_i64(o->out, o->out, t); - tcg_gen_extu_i32_i64(t, cc_op); - tcg_gen_shli_i64(t, t, 28); - tcg_gen_or_i64(o->out, o->out, t); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + /* Shift program mask into place, garbage outside of [27:24]. */ + tcg_gen_shri_i64(t1, psw_mask, 16); + /* Deposit pc to replace garbage bits below program mask. */ + gen_psw_addr_disp(s, t2, s->ilen); + tcg_gen_deposit_i64(t1, t1, t2, 0, 24); + /* + * Deposit cc to replace garbage bits above program mask. + * Note that cc is in [0-3], thus [63:30] are set to zero. + */ + tcg_gen_extu_i32_i64(t2, cc_op); + tcg_gen_deposit_i64(t1, t1, t2, 28, 64 - 28); + /* Install ilen. */ + tcg_gen_ori_i64(t1, t1, (s->ilen / 2) << 30); + + tcg_gen_deposit_i64(o->out, o->out, t1, 0, 32); } static DisasJumpType op_bal(DisasContext *s, DisasOps *o) From patchwork Wed Jun 5 21:57:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801650 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48217wrv; Wed, 5 Jun 2024 14:58:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWmgzvY0Bl5xKEx4yWzr0Rswov16Jt4hRKkubQtnvON5EGG1ee71zTc6Fzvoih9IXtraGANCduBWGvsocYtbQOt X-Google-Smtp-Source: AGHT+IERiMi5g4jIhiBpzXxeYoTK6HXKEcTqRqDknpvbdyShFD35qSlkDVHv5a/g5d/N4fGxYJ0M X-Received: by 2002:a05:620a:f97:b0:795:220b:6d5c with SMTP id af79cd13be357-79523fcde48mr348161585a.70.1717624715965; Wed, 05 Jun 2024 14:58:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624715; cv=none; d=google.com; s=arc-20160816; b=W1MUdeKhCTEhWUnxBfC4lexvKvCCUIbGz/PzINEu0EkbgCvf4oodM7tKAJxWMWeYKG wmI7YblMj3hQEHA43y5Jo0rTZ021sits5/SuA2VUvXuDw3nhj8fcYDWZvihk7ZdkOpWG qV5Za0kfSMrnpznvSZtikXUdhPUr3D/Bv3pHDNZ6BLSKkVgPmWVo+IQOlhpd37DBjZ9O 4xMQoNUkmIaRCBewFuqkzWZxa4mVGVVGEPaKWvo1D1RsoQYPht7kmQ91adcVBkXhT82D yDIrX+kFzB71n4vZgkLBCB/7C35+jshQZaZEj21wJPHQteYYLIFFCB+S0O5Gjc+Yqy1A sKpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jd2ISjYQWsrbk5WgCP4+tpczbqrOBDh2pjdAAZ3A5n0=; fh=2xkb1hkZON85aQlY8H6YQD8NjCAJw799l8+ye3ZWOCA=; b=PZVIV1nj6Auf7Ilg3SSrk74Brgakev1Bblg/3K06GUJYJcgXizHnkCQOH8jd+iFoQs gOTxiH0Fq34jcfwWRA1ZSXfsw8u3fQ23iVEAeaVQ4+7Q+06Jx5S6VTuWqgCa0nCC+YaC UXdwlrh/CCIv/B5KeC/+S6k/Ouqm9Z6fEXQboT7C1aj5WbzMLxZ8Z8k7gprrANMNgT96 n7kTYiPxGx9NUFDGyoCojxVdyOF3yUJhC4PaU03HbI/0ydSxCmAv8yTg9e2BOnrlJPfn Ae8YL97DesMQGLa0CrL1Lyl5bKKi7oJjP2VEwrrWGrR2RQairvrmdM5YuMV1y7sfXtEQ dXug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N7ykA1uP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v2 07/10] target/s390x: Use gen_psw_addr_disp in op_sam Date: Wed, 5 Jun 2024 14:57:36 -0700 Message-Id: <20240605215739.4758-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Complicated because we may now require a runtime jump. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 39 +++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0f0688424f..bce9a0aeb0 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -3805,7 +3805,7 @@ static DisasJumpType op_sacf(DisasContext *s, DisasOps *o) static DisasJumpType op_sam(DisasContext *s, DisasOps *o) { int sam = s->insn->data; - TCGv_i64 tsam; + TCGLabel *fault = NULL; uint64_t mask; switch (sam) { @@ -3820,20 +3820,35 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) break; } - /* Bizarre but true, we check the address of the current insn for the - specification exception, not the next to be executed. Thus the PoO - documents that Bad Things Happen two bytes before the end. */ - if (s->base.pc_next & ~mask) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - s->pc_tmp &= mask; + /* + * Bizarre but true, we check the address of the current insn for the + * specification exception, not the next to be executed. Thus the PoO + * documents that Bad Things Happen two bytes before the end. + */ + if (mask != -1) { + TCGv_i64 t = tcg_temp_new_i64(); + fault = gen_new_label(); - tsam = tcg_constant_i64(sam); - tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); + gen_psw_addr_disp(s, t, 0); + tcg_gen_andi_i64(t, t, ~mask); + tcg_gen_brcondi_i64(TCG_COND_NE, t, 0, fault); + } + + update_cc_op(s); + + tcg_gen_deposit_i64(psw_mask, psw_mask, tcg_constant_i64(sam), 31, 2); + + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_andi_i64(psw_addr, psw_addr, mask); /* Always exit the TB, since we (may have) changed execution mode. */ - return DISAS_TOO_MANY; + tcg_gen_lookup_and_goto_ptr(); + + if (mask != -1) { + gen_set_label(fault); + gen_program_exception(s, PGM_SPECIFICATION); + } + return DISAS_NORETURN; } static DisasJumpType op_sar(DisasContext *s, DisasOps *o) From patchwork Wed Jun 5 21:57:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801652 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48301wrv; Wed, 5 Jun 2024 14:59:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWjhBcQ9TIkK4K3Hy9K2jpRqCYj97jVQwZKGB8pezLvrxcSqW8O4KRvgt6Ar+nj/A9l/WZsPKY8G0hO2CN9EzUo X-Google-Smtp-Source: AGHT+IGlDrA1CnzSaXjkBEaTmUdfBdR3ZcEYDFCfkcX64t/0FRzWCbJFpiv1rgn9tWJaf9YI+82R X-Received: by 2002:a05:622a:242:b0:43a:fc66:35d8 with SMTP id d75a77b69052e-4402b57ef6dmr45021781cf.7.1717624742784; Wed, 05 Jun 2024 14:59:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624742; cv=none; d=google.com; s=arc-20160816; b=OoqZhfzor+KOqOlXTQSoRaX6i2IbfA5erQ/Mk9ort7kko+vLzNR/xjh3egk/e6Kuii 27pFv+S3BqF21GS2A4NTxIn2QrwNhJS2TJQiY/Wmi0ZGhi1906mO1+np4soYOJ/8O4ll CcKBxGBM5Jj8K7Q+V2vs98XAjw18L3qQiwHk60PWFohP6jdEJhXa7SUvGdJbSnODEiBm UOjvd46FKdL2iS/wMndnlolorJZ0jz14IaHinbhw8Tv/ngbOdS7JUs2NMOs04tZrm+8D qJqdyoVgd9nVNWkTqDQdGAhXHJNZSlV2PhrETsQmzVyCNf7qBjKsWRc1hr2g9rVZk2+j vmcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RIX7XK6plrFAu/60k76Lx8FovOSuygKS6nD5tM+w8JA=; fh=NRM9GxiQu7lgoFWAiJmbRZwW47I3s36PXFnyEXFStLk=; b=Tri7ZHy3jcJZsKb1z74K3YHUqmLx43xs1yuJOS5blfayx4CkJrZ4FBz0RQiAaqB5R8 Lz277keb0p3/F+HGQRDTg5Mwh2P5lCzOnMS3I6HLu8obHbGdGLjVZGEQI60qP1zUO2uH ++cxPtMW0OPIshAfCbAAmqu4qh7mUGREBgbtiZYmF8NDibUvx1nP2c3KfwHmqWugwMi9 MIlBTNyj8WEh0PQJR6813BZDmpG2t7Wt/h8MpZ1fHrNYixc6uht/zpf1Zj0ebxnS/P7q X4/wIWXDitLY2JyPBfX4svWZ0VS784JsJQ27JbTcvVSg/BVSSvx1Yd+L+kztX8hs6OTc xtGQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U8yR0Ady; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v2 08/10] target/s390x: Use ilen instead in branches Date: Wed, 5 Jun 2024 14:57:37 -0700 Message-Id: <20240605215739.4758-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove the remaining uses of pc_tmp, and remove the variable. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bce9a0aeb0..3014cbea4f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -141,12 +141,6 @@ struct DisasContext { const DisasInsn *insn; DisasFields fields; uint64_t ex_value; - /* - * During translate_one(), pc_tmp is used to determine the instruction - * to be executed after base.pc_next - e.g. next sequential instruction - * or a branch target. - */ - uint64_t pc_tmp; uint32_t ilen; enum cc_op cc_op; bool exit_to_mainloop; @@ -344,11 +338,6 @@ static void store_freg32_i64(int reg, TCGv_i64 v) tcg_gen_st32_i64(v, tcg_env, freg32_offset(reg)); } -static void update_psw_addr(DisasContext *s) -{ - gen_psw_addr_disp(s, psw_addr, 0); -} - static void per_branch(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY @@ -420,7 +409,7 @@ static void gen_program_exception(DisasContext *s, int code) offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ - update_psw_addr(s); + gen_psw_addr_disp(s, psw_addr, 0); /* Save off cc. */ update_cc_op(s); @@ -1179,7 +1168,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ gen_psw_addr_disp(s, psw_addr, s->ilen); - if (use_goto_tb(s, s->pc_tmp)) { + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { tcg_gen_goto_tb(1); tcg_gen_exit_tb(s->base.tb, 1); return DISAS_NORETURN; @@ -2361,7 +2350,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - update_psw_addr(s); + gen_psw_addr_disp(s, psw_addr, 0); update_cc_op(s); if (r1 == 0) { @@ -3085,7 +3074,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o) /* In a parallel context, stop the world and single step. */ if (tb_cflags(s->base.tb) & CF_PARALLEL) { - update_psw_addr(s); + gen_psw_addr_disp(s, psw_addr, 0); update_cc_op(s); gen_exception(EXCP_ATOMIC); return DISAS_NORETURN; @@ -4379,7 +4368,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) { update_cc_op(s); - update_psw_addr(s); + gen_psw_addr_disp(s, psw_addr, 0); gen_helper_per_store_real(tcg_env, tcg_constant_i32(s->ilen)); return DISAS_NORETURN; } @@ -4611,7 +4600,7 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) { TCGv_i32 t; - update_psw_addr(s); + gen_psw_addr_disp(s, psw_addr, 0); update_cc_op(s); t = tcg_constant_i32(get_field(s, i1) & 0xff); @@ -6193,7 +6182,6 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) g_assert_not_reached(); } } - s->pc_tmp = s->base.pc_next + ilen; s->ilen = ilen; /* We can't actually determine the insn format until we've looked up @@ -6413,7 +6401,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) out: /* Advance to the next instruction. */ - s->base.pc_next = s->pc_tmp; + s->base.pc_next += s->ilen; return ret; } @@ -6475,7 +6463,7 @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_TOO_MANY: - update_psw_addr(dc); + gen_psw_addr_disp(dc, psw_addr, 0); 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v2 09/10] target/s390x: Assert masking of psw.addr in cpu_get_tb_cpu_state Date: Wed, 5 Jun 2024 14:57:38 -0700 Message-Id: <20240605215739.4758-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When changing modes via SAM, we raise a specification exception if the new PC is out of range. The masking in s390x_tr_init_disas_context was too late to be correct, but may be removed. Add a debugging assert in cpu_get_tb_cpu_state. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 6 ++++++ target/s390x/tcg/translate.c | 6 +----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 2bbeaca36e..c786767bd1 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -358,6 +358,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, flags |= FLAG_MASK_VECTOR; } *pflags = flags; + + if (!(flags & FLAG_MASK_32)) { + tcg_debug_assert(*pc <= 0x00ffffff); + } else if (!(flags & FLAG_MASK_64)) { + tcg_debug_assert(*pc <= 0x7fffffff); + } } static const TCGCPUOps s390_tcg_ops = { diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3014cbea4f..0ee14484d0 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6409,11 +6409,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - /* 31-bit mode */ - if (!(dc->base.tb->flags & FLAG_MASK_64)) { - dc->base.pc_first &= 0x7fffffff; - dc->base.pc_next = dc->base.pc_first; - } + /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */ dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; From patchwork Wed Jun 5 21:57:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 801660 Delivered-To: patch@linaro.org Received: by 2002:a5d:5610:0:b0:35b:5a80:51b4 with SMTP id l16csp48487wrv; Wed, 5 Jun 2024 14:59:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXkqBBKNBLT8g9joXFBx6QUBJ+Z6RSe/js+4H3bOrx5pJ5FOnFYLQy+KrxlBdozE7tKgUmZrZSaKf8se4yKCQWq X-Google-Smtp-Source: AGHT+IGEnbYz3NmtXiYmDI9V541olgbkcM+wEhuSUuT3UvuqF6JTqKa2fGbFIPtefdBLrvss1+2z X-Received: by 2002:a05:622a:134a:b0:43a:fce1:f520 with SMTP id d75a77b69052e-4402b6e6fb2mr49931791cf.65.1717624789140; Wed, 05 Jun 2024 14:59:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1717624789; cv=none; d=google.com; s=arc-20160816; b=YkVoffnFHqpRsAfqLfd1l5jPu78vg7+vfebIMnjLTucAVRVYpi+9mXZJL01/XWvfqL RS5GoT8QLWETSal+1dI16KvwkH6DJk2Pp6ql7WrKLc2OV5v0qNcrUR3hPhcaKsoNg2+p YN5OJxzMW4RKthLsh7s3y7dMjEEcTaAUQ+ofJIaSxJDEu5YjfyHbnlS9RWtJOt+IH3wC CmfV9cL1b0RFY/7YovNe0pACbA6v/kPUMQU6d6PbtGjZcvzAYXSoWOmWXQoD6XGHuh0T prfdmGfZnS+GbdRIgFgTQrQMSLwUpgimxb8j+zwh/EuWM6aSlugeL1hbVelj5tvaui3m YM0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LRuvGrqklc35nzRDLd0HrPdmqm1+emdl+BYV+uq1dAc=; fh=dBGltRZCelj4V8aBoG+OSD7H6rZxxBGgTNXT/erTiSU=; b=wF3fHOn7eGP3qvqAYLw7s/rNyWkOSVte1VAsgxz4Ck+2ggewShHucq5xdufd6i6z/U SS6bFOgW2g5s2lY6C0ITEPBGjtKQEj3Xd6CxemggyGFcgS1JWxinU1S/VdQSn5BDnmQT fo2Qy6i/XGa3ymPVWZBy7N0NSbBrAtWG8/x1mRBFSSXedcayx3gi8HJYiObNxDBJdszH flFwxlbPy9Y/KReUfAn6qnEAO0p3gYsYAXcmihX090kHblMD8CvDSidUOrBq7FV8bMkr hbQa2YpAhtODA3yaUc5Ozo0s14Nxrl8MwALUFOCu3a1gxI0yEzl7KmiD8UFIqsiERazj NzZQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HzLxhWhZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70242b2ff9dsm9091509b3a.212.2024.06.05.14.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 14:57:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH v2 10/10] target/s390x: Enable CF_PCREL Date: Wed, 5 Jun 2024 14:57:39 -0700 Message-Id: <20240605215739.4758-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605215739.4758-1-richard.henderson@linaro.org> References: <20240605215739.4758-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/s390x/cpu.c | 17 +++++++++ target/s390x/tcg/translate.c | 71 +++++++++++++++++++++++------------- 2 files changed, 62 insertions(+), 26 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index c786767bd1..9f03190c35 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -39,6 +39,7 @@ #include "sysemu/reset.h" #endif #include "hw/s390x/cpu-topology.h" +#include "exec/translation-block.h" #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; @@ -111,6 +112,16 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) return r; } +static void s390_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + /* The program counter is always up to date with CF_PCREL. */ + if (!(tb_cflags(tb) & CF_PCREL)) { + CPUS390XState *env = cpu_env(cs); + env->psw.addr = tb->pc; + } +} + static void s390_cpu_set_pc(CPUState *cs, vaddr value) { S390CPU *cpu = S390_CPU(cs); @@ -246,6 +257,11 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp) S390CPUClass *scc = S390_CPU_GET_CLASS(dev); Error *err = NULL; +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + /* Use pc-relative instructions in system-mode */ + cs->tcg_cflags |= CF_PCREL; +#endif + /* the model has to be realized before qemu_init_vcpu() due to kvm */ s390_realize_cpu_model(cs, &err); if (err) { @@ -368,6 +384,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, static const TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, + .synchronize_from_tb = s390_cpu_synchronize_from_tb, .restore_state_to_opc = s390x_restore_state_to_opc, #ifdef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0ee14484d0..6961ad7c67 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -139,6 +139,7 @@ struct DisasFields { struct DisasContext { DisasContextBase base; const DisasInsn *insn; + target_ulong pc_save; DisasFields fields; uint64_t ex_value; uint32_t ilen; @@ -161,28 +162,6 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif -static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) -{ - tcg_gen_movi_i64(dest, s->base.pc_next + disp); -} - -static void pc_to_link_info(TCGv_i64 out, DisasContext *s) -{ - TCGv_i64 tmp; - - if (s->base.tb->flags & FLAG_MASK_64) { - gen_psw_addr_disp(s, out, s->ilen); - return; - } - - tmp = tcg_temp_new_i64(); - gen_psw_addr_disp(s, tmp, s->ilen); - if (s->base.tb->flags & FLAG_MASK_32) { - tcg_gen_ori_i64(tmp, tmp, 0x80000000); - } - tcg_gen_deposit_i64(out, out, tmp, 0, 32); -} - static TCGv_i64 psw_addr; static TCGv_i64 psw_mask; static TCGv_i64 gbea; @@ -338,6 +317,34 @@ static void store_freg32_i64(int reg, TCGv_i64 v) tcg_gen_st32_i64(v, tcg_env, freg32_offset(reg)); } +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + assert(s->pc_save != -1); + if (tb_cflags(s->base.tb) & CF_PCREL) { + disp += s->base.pc_next - s->pc_save; + tcg_gen_addi_i64(dest, psw_addr, disp); + } else { + tcg_gen_movi_i64(dest, s->base.pc_next + disp); + } +} + +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) +{ + TCGv_i64 tmp; + + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; + } + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); +} + static void per_branch(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY @@ -1081,13 +1088,13 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) if (disp == s->ilen) { return DISAS_NEXT; } + gen_psw_addr_disp(s, psw_addr, disp); if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - gen_psw_addr_disp(s, psw_addr, disp); + s->pc_save = dest; return DISAS_PC_CC_UPDATED; } } @@ -1097,6 +1104,7 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) update_cc_op(s); per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); + s->pc_save = -1; per_branch(s, psw_addr); return DISAS_PC_CC_UPDATED; } @@ -1173,6 +1181,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, tcg_gen_exit_tb(s->base.tb, 1); return DISAS_NORETURN; } + s->pc_save = s->base.pc_next + s->ilen; return DISAS_PC_CC_UPDATED; } @@ -2351,6 +2360,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) } gen_psw_addr_disp(s, psw_addr, 0); + s->pc_save = s->base.pc_next; update_cc_op(s); if (r1 == 0) { @@ -6411,6 +6421,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */ + dc->pc_save = dc->base.pc_first; dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; dc->exit_to_mainloop = dc->ex_value; @@ -6423,9 +6434,13 @@ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_arg = dc->base.pc_next; + if (tb_cflags(dc->base.tb) & CF_PCREL) { + pc_arg &= ~TARGET_PAGE_MASK; + } /* Delay the set of ilen until we've read the insn. */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); } static target_ulong get_next_pc(CPUS390XState *env, DisasContext *s, @@ -6517,7 +6532,11 @@ void s390x_restore_state_to_opc(CPUState *cs, CPUS390XState *env = cpu_env(cs); int cc_op = data[1]; - env->psw.addr = data[0]; + if (tb_cflags(tb) & CF_PCREL) { + env->psw.addr = (env->psw.addr & TARGET_PAGE_MASK) | data[0]; + } else { + env->psw.addr = data[0]; + } /* Update the CC opcode if it is not already up-to-date. */ if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {