From patchwork Mon Oct 21 13:13:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177077 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3404407ill; Mon, 21 Oct 2019 06:14:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNiaEPxnaHkvPjBXsXvp5a1CRe77I08yCbUzMnnPrK9VV/hVjHzg/FEkRrgxWc2Q/TPbNq X-Received: by 2002:a17:906:c28c:: with SMTP id r12mr1529171ejz.163.1571663673622; Mon, 21 Oct 2019 06:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571663673; cv=none; d=google.com; s=arc-20160816; b=VtoSCxx5OjdOx1YioCUBVX1bZgnWolmLjDVPq9yEgAlR4bVocCHlwAeyzkaQkiBhMH Ni4xyHWrjWloo3rT6d+l8vZXP5NEfO86Ip8gVI6uiN40Mh9F1lOyubrmFbMWEjIjlCp1 zKn0bl8wpb41NdVgS48q+HQYgoDucgNY//jQG+71yzlHk9wC+x04Nm5FuPpOdDfEOt1p d2Q8VTfS6dvlFbZfASdxzfeK4u308HxIRnRAq19b5kF6uV2KNou7k1iFU8b+cUKClyHz LKGJc+soNa6tC1LFS86FNOIoSIsMF+reSKGsthmrlsS0ImR/hKOdnL1361MYtSHHKs7I 6DQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HV6iaivoaFG9onDrZhTj+eWHfIehxFTqG6sv4XHOH80=; b=KHxAaayNbBvoUuA5kyXxrNBFbWNB0g34XgSALDdF0xB0JGq5EOUYRs9f/GrMBNWfI/ rNRb35Bng+ur+rfLxQUC4N2rtblUl4TJG8EhKIaumOor+6VxBBoQDqN6Z5bPed1GkLNW d5iQRSc9c6xnrTN7Jx/F8mpiTH9w+RTkoyAozsYj0+80XOQzdYz9FOnZhPvrncciucvM iP4SR1Oq503X4n7UVEtpsZsqcTHjm8KM2IdC6oKDFYh0gVa4VeTNYg1zGlzhcAeh0bQe GiLfYkADHecvxe1rwALr3qLRHySMXr7G/bHxbAEDJHzN5BpG5H/aDIPz0f6aCXULi5xc qBmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vx3vntD3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id np3si8471526ejb.384.2019.10.21.06.14.33; Mon, 21 Oct 2019 06:14:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vx3vntD3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728899AbfJUNO3 (ORCPT + 26 others); Mon, 21 Oct 2019 09:14:29 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33406 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728840AbfJUNO2 (ORCPT ); Mon, 21 Oct 2019 09:14:28 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9LDEKJ6083939; Mon, 21 Oct 2019 08:14:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571663660; bh=HV6iaivoaFG9onDrZhTj+eWHfIehxFTqG6sv4XHOH80=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vx3vntD3GVVm6efCVc5xOZ3unu/awcqin8fki0KiMBfcpeLns31LNr9BY+PJc9l1M JbeFSBs6gLlOs/xzrDpr8aOPF5mIOMb1GiThOrI9OawPGJ5JueD1b1v/7hURrI+pkb 9JR7OPkp7yQ8XndeXQU/WFRJ+wxNF40adFjuJX0w= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9LDE5nu044321 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 21 Oct 2019 08:14:05 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 21 Oct 2019 08:13:55 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 21 Oct 2019 08:14:04 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9LDDE7f017365; Mon, 21 Oct 2019 08:13:17 -0500 From: Roger Quadros To: , CC: , , , , , , , Roger Quadros , Rob Herring Subject: [PATCH v2 1/2] dt-bindings: usb: Add binding for the TI wrapper for Cadence USB3 controller Date: Mon, 21 Oct 2019 16:13:04 +0300 Message-ID: <20191021131305.8689-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191021131305.8689-1-rogerq@ti.com> References: <20191021131305.8689-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI platforms have a wrapper module around the Cadence USB3 controller. Add binding information for that. Cc: Rob Herring Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- .../devicetree/bindings/usb/ti,j721e-usb.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,j721e-usb.txt -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/usb/ti,j721e-usb.txt b/Documentation/devicetree/bindings/usb/ti,j721e-usb.txt new file mode 100644 index 000000000000..bac57c26b09b --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,j721e-usb.txt @@ -0,0 +1,52 @@ +Binding for the TI specific wrapper for the Cadence USBSS-DRD controller + +Required properties: + - compatible: Should contain "ti,j721e-usb" + - reg: Physical base address and size of the wrappers register area. + - power-domains: Should contain a phandle to a PM domain provider node + and an args specifier containing the USB device id + value. This property is as per the binding documentation: + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + - clocks: Clock phandles to usb2_refclk and lpm_clk + - clock-names: Should contain "ref" and "lpm" + +Optional properties: + - ti,usb2-only: If present, it restricts the controller to USB2.0 mode of + operation. Must be present if USB3 PHY is not available + for USB. + - ti,vbus-divider: Should be present if USB VBUS line is connected to the + VBUS pin of the SoC via a 1/3 voltage divider. + +Sub-nodes: +The USB2 PHY and the Cadence USB3 controller should be the sub-nodes. + +Example: + + ti_usb0: cdns_usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + };