From patchwork Tue Jun 4 14:10:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Yashin X-Patchwork-Id: 801472 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E18D9179AF; Tue, 4 Jun 2024 14:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717510336; cv=none; b=Lmdxs2VAiwhMqQ9bqVAsgVFxEJND0xzUWrCOWafM0notqUDJB5MDITcwR/zTlyFgSRCAafgFuBvNHQq8ts+DppmlPw/enMPbfiuJ9vdPgvg6hOG6U1ArHGED5m2AbP+m1zUyf2qmY+xRQFwdhOEuO5+0T7UiwTpEqPp6j0vIGEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717510336; c=relaxed/simple; bh=eMyXSOQOT43iLqcN4yT0wGM8KoO/1+7sYYREbBUtemg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CyDoPVCWdlnni12hax7P2muu5QVLV1njOVp7aw0r9rfnz4kRnS8LTYOv1qNJCMVSbJXp1K5Uz5JI6jsyx3hq/dHseCyrg7FQMZzDPbunbiyTCiuRkDCs5YrwYgCD7WtrQdHOosgZ+Hs2hUPMD5+qYVPiQE43w4ctasTfrpk1zkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gPjrhY/7; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gPjrhY/7" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-52b8d483a08so4545517e87.1; Tue, 04 Jun 2024 07:12:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717510333; x=1718115133; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SmSb1T/VVTzErPc/hVH5RhenzFyIr1nmaXQZzXj2G2k=; b=gPjrhY/7aed5GNF3G3yn6GhuzI5oiwHL+WhEuN5wyAgQsbU+fIL1HimwHHfTpJqpJF qn1agwYPDZkrDQrXLKqGVwpWDnvstncP31xQNZsozut/9Pq91sNlP45iW0YyWbhRai64 C5BSuqB6Ww/6ZoQ57DRjXIx3h1S5VXuG1a0TFCdmLhwlmZ274a1hDl/ayktmtu2SROOn 9OeRFYFNNDNt4m83BnTotwRch59MyLL7iwOcG4ggygxVwFZmnaF7KGV0mXoRE97LO6Th cN25UDWv9inbjXxaLAr9p6/7n8HKLNN9WC/DS+D73yfj5ao5KL/F0MFbq4tRLGN2BEEZ OF4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717510333; x=1718115133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SmSb1T/VVTzErPc/hVH5RhenzFyIr1nmaXQZzXj2G2k=; b=mip0d3F7PZIXkhIC+Pru/h9TGKmKibbIGRp3ZmDb0e4Qvi1d7tJj3ypQ8pt8PGVhuY 8ouo82UbZqrDT5/qlTwZJbF+paOP5ied48mghxCsZDoVe7k654eluBC1Z086yTxyrZJx VpklAKanc6VOz46JRVWJuMjO7mxB53hY46KuwfapKiy0rti4FstopK4Z0IRg1SILh8VL M2ENgYZtYOlfKgZdrzr/Z8Skv3bpV4eE9kJUXi6audHk0Ht7wmnW03RjCU8bJUoRSe/i PRQErZV0D61R7SwNx7EA1IHB7gQUk31YiiM+xPrJ34l9fOyGtt6kInbTbY33Qme0Th4z yl2Q== X-Forwarded-Encrypted: i=1; AJvYcCUtQJEp29hj0meGKRV15NxFM2fM8+o4qurlg7+lU6m4c/Zdd1Ls4KqBAxPd9bCms9FhQuS6tIWXnUK8eBC5YZDOpNR+WCubrI4Pw8WrTdG5FVpNzQZhG8Uv3nHBc5qvGe7bHPD49uIQTkne1tqEcOtYpoG/s/vRWPgcBgYs3ZsbleWSbVQ= X-Gm-Message-State: AOJu0YwWEjRMyqyD7Ce6oHunN+SiEdTIYAtsvT+C0Z+cZo+tDskwrgMU 2BxKi7H/5IwOn2mXlYUXQwSs0pT0iVh18GoIniHZ0LBadBV8WTvq X-Google-Smtp-Source: AGHT+IHYQNbt+cYQfc7+Uhr8tfuad6kxVxl6LzEFNoBOEmCGkZdeactT1NLRjFLrcC/X7wM3oRe0vA== X-Received: by 2002:a05:6512:7b:b0:52b:8843:b084 with SMTP id 2adb3069b0e04-52b896bfa33mr8318743e87.47.1717510333160; Tue, 04 Jun 2024 07:12:13 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52b982d3de7sm742743e87.2.2024.06.04.07.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 07:12:12 -0700 (PDT) From: Dmitry Yashin To: Linus Walleij , Heiko Stuebner Cc: Luca Ceresoli , Jianqun Xu , Jonas Karlman , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v3 1/2] pinctrl: rockchip: delay recalced_mask and route_mask init Date: Tue, 4 Jun 2024 19:10:19 +0500 Message-ID: <20240604141020.21725-2-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240604141020.21725-1-dmt.yashin@gmail.com> References: <20240604141020.21725-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For some SoC's like rk3308 additional runtime setup needed, so delay recalced_mask and route_mask init. Signed-off-by: Dmitry Yashin --- drivers/pinctrl/pinctrl-rockchip.c | 52 ++++++++++++++++++------------ 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index cc647db76927..b252d1454ce0 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3170,6 +3170,36 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, return 0; } +static void iomux_recalced_routes_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int i, j; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + + /* calculate the per-bank recalced_mask */ + for (j = 0; j < ctrl->niomux_recalced; j++) { + int pin = 0; + + if (ctrl->iomux_recalced[j].num == bank->bank_num) { + pin = ctrl->iomux_recalced[j].pin; + bank->recalced_mask |= BIT(pin); + } + } + + /* calculate the per-bank route_mask */ + for (j = 0; j < ctrl->niomux_routes; j++) { + int pin = 0; + + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { + pin = ctrl->iomux_routes[j].pin; + bank->route_mask |= BIT(pin); + } + } + } +} + static const struct of_device_id rockchip_pinctrl_dt_match[]; /* retrieve the soc specific data */ @@ -3265,26 +3295,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } - - /* calculate the per-bank recalced_mask */ - for (j = 0; j < ctrl->niomux_recalced; j++) { - int pin = 0; - - if (ctrl->iomux_recalced[j].num == bank->bank_num) { - pin = ctrl->iomux_recalced[j].pin; - bank->recalced_mask |= BIT(pin); - } - } - - /* calculate the per-bank route_mask */ - for (j = 0; j < ctrl->niomux_routes; j++) { - int pin = 0; - - if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { - pin = ctrl->iomux_routes[j].pin; - bank->route_mask |= BIT(pin); - } - } } return ctrl; @@ -3403,6 +3413,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(info->regmap_pmu); } + iomux_recalced_routes_init(info); + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret; From patchwork Tue Jun 4 14:10:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Yashin X-Patchwork-Id: 801778 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBA3A84E1C; Tue, 4 Jun 2024 14:12:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717510338; cv=none; b=ej7bHOvbXC0+oYwB61jdGRiCwi/7+44ZwqFAUULkOAGOdwcbUuRUIHe6kdMBbhfXf/bgaSsZVza/uTU5stziuNCcp9YZGlCS7zF6WFGftndmvCajIo82YpQ6Yac5qCjKLXBVRCcH1XiYURdYtlmyVzNpZWcwcFgNZxR2iPIwcic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 04 Jun 2024 07:12:14 -0700 (PDT) From: Dmitry Yashin To: Linus Walleij , Heiko Stuebner Cc: Luca Ceresoli , Jianqun Xu , Jonas Karlman , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v3 2/2] pinctrl: rockchip: add rk3308b SoC support Date: Tue, 4 Jun 2024 19:10:20 +0500 Message-ID: <20240604141020.21725-3-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240604141020.21725-1-dmt.yashin@gmail.com> References: <20240604141020.21725-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pinctrl support for rk3308b. This pin controller much the same as rk3308's, but with additional iomux routes and 3bit iomuxes selected via gpio##_sel_src_ctrl registers. Set them up in the function rk3308b_soc_sel_src_init to use new 3bit iomuxes over some 2bit old ones and update iomux_recalced and iomux_routes for the new SoC's. Fixes: 1f3e25a06883 ("pinctrl: rockchip: fix RK3308 pinmux bits") Signed-off-by: Dmitry Yashin Reviewed-by: Luca Ceresoli --- drivers/pinctrl/pinctrl-rockchip.c | 234 +++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 235 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index b252d1454ce0..b6a0eadfeed2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -632,6 +632,115 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { }, }; +static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { + { + /* gpio1b6_sel */ + .num = 1, + .pin = 14, + .reg = 0x28, + .bit = 12, + .mask = 0xf + }, { + /* gpio1b7_sel */ + .num = 1, + .pin = 15, + .reg = 0x2c, + .bit = 0, + .mask = 0x3 + }, { + /* gpio1c2_sel */ + .num = 1, + .pin = 18, + .reg = 0x30, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c3_sel */ + .num = 1, + .pin = 19, + .reg = 0x30, + .bit = 8, + .mask = 0xf + }, { + /* gpio1c4_sel */ + .num = 1, + .pin = 20, + .reg = 0x30, + .bit = 12, + .mask = 0xf + }, { + /* gpio1c5_sel */ + .num = 1, + .pin = 21, + .reg = 0x34, + .bit = 0, + .mask = 0xf + }, { + /* gpio1c6_sel */ + .num = 1, + .pin = 22, + .reg = 0x34, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c7_sel */ + .num = 1, + .pin = 23, + .reg = 0x34, + .bit = 8, + .mask = 0xf + }, { + /* gpio2a2_sel_plus */ + .num = 2, + .pin = 2, + .reg = 0x608, + .bit = 0, + .mask = 0x7 + }, { + /* gpio2a3_sel_plus */ + .num = 2, + .pin = 3, + .reg = 0x608, + .bit = 4, + .mask = 0x7 + }, { + /* gpio2c0_sel_plus */ + .num = 2, + .pin = 16, + .reg = 0x610, + .bit = 8, + .mask = 0x7 + }, { + /* gpio3b2_sel_plus */ + .num = 3, + .pin = 10, + .reg = 0x610, + .bit = 0, + .mask = 0x7 + }, { + /* gpio3b3_sel_plus */ + .num = 3, + .pin = 11, + .reg = 0x610, + .bit = 4, + .mask = 0x7 + }, { + /* gpio3b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x68, + .bit = 8, + .mask = 0xf + }, { + /* gpio3b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x68, + .bit = 12, + .mask = 0xf + }, +}; + static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { .num = 2, @@ -882,6 +991,35 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ }; +static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { + RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ + RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ + RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ + RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ + RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ + RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ + RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ + RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ + RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ + RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ + RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ + RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ + RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ + RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ + RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ + RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ + RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ + RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ + RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ +}; + static struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ @@ -2420,6 +2558,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3368: case RK3399: case RK3568: @@ -2478,6 +2617,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3368: case RK3399: case RK3568: @@ -2740,6 +2880,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3368: case RK3399: case RK3568: @@ -3348,6 +3489,93 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume); +#define RK3308B_GRF_SOC_CON13 0x608 +#define RK3308B_GRF_SOC_CON15 0x610 + +/* RK3308B_GRF_SOC_CON13 */ +#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) +#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* RK3308B_GRF_SOC_CON15 */ +#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) +#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* + * RK3308B has 3bit gpio##_sel_plus iomuxes over some 2bit old ones. + * Put them in use by initializing gpio##_sel_src_ctrl registers. + */ +static int rk3308b_soc_sel_src_init(struct rockchip_pinctrl *info) +{ + int ret; + + ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13, + RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | + RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); + if (ret) + return ret; + + ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15, + RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); + + return ret; +}; + +#define RK3308_GRF_CHIP_ID 0x800 + +static int rk3308_soc_update_type(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + unsigned int chip_id; + int ret; + + ret = regmap_read(info->regmap_base, RK3308_GRF_CHIP_ID, &chip_id); + if (ret) + return ret; + + switch (chip_id) { + /* From RK3308 TRM: "Errata: The read only chip id value is 32'h0cea(32'd3306)" */ + case 0xcea: + break; + case 0x3308: + case 0x3308c: + ctrl->type = RK3308B; + break; + default: + return dev_err_probe(info->dev, -EINVAL, "Unknown chip_id: 0x%x\n", chip_id); + } + + return 0; +} + +static int rk3308_soc_data_update(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + int ret; + + ret = rk3308_soc_update_type(info); + if (ret) + return ret; + + if (ctrl->type == RK3308B) { + /* Replace iomux data for RK3308B and RK3308BS */ + ctrl->iomux_recalced = rk3308b_mux_recalced_data; + ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); + ctrl->iomux_routes = rk3308b_mux_route_data; + ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); + + ret = rk3308b_soc_sel_src_init(info); + if (ret) + return ret; + } + + return 0; +} + static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; @@ -3413,6 +3641,12 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(info->regmap_pmu); } + if (ctrl->type == RK3308) { + ret = rk3308_soc_data_update(info); + if (ret) + return ret; + } + iomux_recalced_routes_init(info); ret = rockchip_pinctrl_register(pdev, info); diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 4759f336941e..3af5b1bd626b 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -193,6 +193,7 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3308B, RK3368, RK3399, RK3568,