From patchwork Mon Oct 21 06:44:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 177032 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3000499ill; Sun, 20 Oct 2019 23:44:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqzobRyy87W+Yxpr9n3yDNGLcWQEYdqWhY78bF+PrZH1kH5g2jUBAScz0Bw72FCo28ldwQKy X-Received: by 2002:a17:906:48d4:: with SMTP id d20mr15442406ejt.246.1571640273644; Sun, 20 Oct 2019 23:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571640273; cv=none; d=google.com; s=arc-20160816; b=qBrhf4wM/Oe7XfgJOGlrTDUb/VqcQgnLNxad2HjlGnQrg43FOu25MPeCD3Hsj+BSey xCCbt3Sk0QxMLQEIo+A/Oayn6PhPgRXUqh151af+lN3LnXX805n3bivRwDQ7Jet97Itc nLuui6hm1gmMAkFP77IDRiq2WPz18k1TBA0zuo9cJrHBX5xSKVYlpac+L1WRirADjGJb YKYW94EEEr6yhYtoVVbrVSuctTxwiG6r2zbS/5U8DIkWA+i7vT6prW5DxXqGxu7xloIk vzsf7iShgnXDZVg8jAUf3FPAjp2SiP0TUKHpYhS4hhdKeOut4cITiW631U4thjHyky7W tgnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=P585Wb4GdNSdANLbtZBTejDHy0hzt6pLG6Y0SHAZ9bU=; b=X728T8DRXU+n0greq18r7KSonj/E8+Igt8tOs3utx+vodwYIcvpKYh6IEjd3t7KqQG SsOLEkT2xCI2O5akojMIHPeJ3W/7DmBtDDEBuCIJDEG0Eb1qajPVzUTkbODfCWYZBnZh avaTxALs+j3CedXZzuY5JrR94kCI1sTM1Dvl9yNz5+MkCO/0e0ZKJ/8e46LZFIRTtxjE Ua/P2P/qpngbjNrIME9wWWnPTJ4GKyHE9UOZDb0OWc/FgfZRZDSD1UIVUkGw9393eTW9 QU30b+Rjuw6WBtn1RfsCPVYUcMmOQGczOfV4Q8uGoZM0NXmPOVXkT86Pt5kpnk6soRU8 mS0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o2UCcVa9; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m21si9479066edc.153.2019.10.20.23.44.33; Sun, 20 Oct 2019 23:44:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o2UCcVa9; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727136AbfJUGoa (ORCPT + 5 others); Mon, 21 Oct 2019 02:44:30 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:46429 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726039AbfJUGoa (ORCPT ); Mon, 21 Oct 2019 02:44:30 -0400 Received: by mail-pg1-f194.google.com with SMTP id e15so7129898pgu.13 for ; Sun, 20 Oct 2019 23:44:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P585Wb4GdNSdANLbtZBTejDHy0hzt6pLG6Y0SHAZ9bU=; b=o2UCcVa98LWeVYND0PE/v8hZfB6qvv7otuszYHpwOafbshMElcl2fopVc68goHvkSU 4osSwuadu1/VmaP0pLtxQKWtvAHZjAbwXkJelhOa3PgwYAHDSwuEH9Ggv1L6RW1qguu1 FWyVBRvOZbpj9GlVvA40GiIUh8M0+AJVzBXrFHzz9zAU1HElW1NHOHZctsx/WFe/jdQI 3MjIj195CY/+vzsde3JHST48qEYNuagUXETObyQdmtnR6EfpH5aEy8B0HvhyYmbPmVgS 9Ppwb539dHA3fbb/ONOn8qyo0Asm7y4sNhwbi6Eotg5qRu5+H/iYKdxJ7OsyHlLKFRc1 V/9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P585Wb4GdNSdANLbtZBTejDHy0hzt6pLG6Y0SHAZ9bU=; b=O35J9hGLo7HwnHtoTtz61w+OnElDeCO0aBgkUH0Eee73T8v2fq45l59iIB1k9vMa// BIAzx+6zpex5cH6WCM+d3/SdQEuY25JaNyp/gZJaApegP+7ofkHZxSauTZ1n6bIvjYLt WOETnvVHVFU5fuZrwUnvI7KzfiWtPF6AFD6dtOzt8ij8uWyLKhelAUn7h667kdAAe+NT 6tZ5qguDWk04USMJ2cOsDi+jdg7c6QqpOLx40VoG8Zu0F0TcjiICiudlK8ra8DsCG0ev cptfEjfd9LwGUU9g2QZZbiGi4XnZT2hwKaEfg3syAz4Svd2NMNVn/wPBrMbgpqpqM1O9 qySA== X-Gm-Message-State: APjAAAWYjKlhghjYy3iyoZrcUnCme45McK4OZdomjMjxbwtBz0hU2Vrb /eOdez0IjKqExQ7ziNCFKnBN X-Received: by 2002:a63:a02:: with SMTP id 2mr106677pgk.389.1571640269210; Sun, 20 Oct 2019 23:44:29 -0700 (PDT) Received: from localhost.localdomain ([2405:204:700f:8db6:2442:890f:ac37:8127]) by smtp.gmail.com with ESMTPSA id d4sm13156624pjs.9.2019.10.20.23.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2019 23:44:28 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, bgolaszewski@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, orsonzhai@gmail.com, Manivannan Sadhasivam Subject: [PATCH v3 1/4] dt-bindings: gpio: Add devicetree binding for RDA Micro GPIO controller Date: Mon, 21 Oct 2019 12:14:10 +0530 Message-Id: <20191021064413.19840-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191021064413.19840-1-manivannan.sadhasivam@linaro.org> References: <20191021064413.19840-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add YAML devicetree binding for RDA Micro GPIO controller. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/gpio/gpio-rda.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-rda.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/gpio/gpio-rda.yaml b/Documentation/devicetree/bindings/gpio/gpio-rda.yaml new file mode 100644 index 000000000000..6ece555f074f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-rda.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-rda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro GPIO controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: rda,8810pl-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + ngpios: + description: + Number of available gpios in a bank. + minimum: 1 + maximum: 32 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - ngpios + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +... 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This GPIO controller is an in house IP, developed by RDA Micro (now Unisoc) for the use in RDA88* series of SoCs. There are multiple GPIO ports present in all SoCs, each capable of addressing 32 GPIOs. But only first 8 pins have the interrupt capability. Signed-off-by: Manivannan Sadhasivam --- drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rda.c | 294 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 304 insertions(+) create mode 100644 drivers/gpio/gpio-rda.c -- 2.17.1 Reviewed-by: Bartosz Golaszewski diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 38e096e6925f..a896f0820a21 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -435,6 +435,15 @@ config GPIO_RCAR help Say yes here to support GPIO on Renesas R-Car SoCs. +config GPIO_RDA + bool "RDA Micro GPIO controller support" + depends on ARCH_RDA || COMPILE_TEST + depends on OF_GPIO + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y here to support RDA Micro GPIO controller. + config GPIO_REG bool help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d2fd19c15bae..5c68c9a48fa3 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -115,6 +115,7 @@ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o +obj-$(CONFIG_GPIO_RDA) += gpio-rda.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_REG) += gpio-reg.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c new file mode 100644 index 000000000000..28dcbb58b76b --- /dev/null +++ b/drivers/gpio/gpio-rda.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RDA Micro GPIO driver + * + * Copyright (C) 2012 RDA Micro Inc. + * Copyright (C) 2019 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include + +#define RDA_GPIO_OEN_VAL 0x00 +#define RDA_GPIO_OEN_SET_OUT 0x04 +#define RDA_GPIO_OEN_SET_IN 0x08 +#define RDA_GPIO_VAL 0x0c +#define RDA_GPIO_SET 0x10 +#define RDA_GPIO_CLR 0x14 +#define RDA_GPIO_INT_CTRL_SET 0x18 +#define RDA_GPIO_INT_CTRL_CLR 0x1c +#define RDA_GPIO_INT_CLR 0x20 +#define RDA_GPIO_INT_STATUS 0x24 + +#define RDA_GPIO_IRQ_RISE_SHIFT 0 +#define RDA_GPIO_IRQ_FALL_SHIFT 8 +#define RDA_GPIO_DEBOUCE_SHIFT 16 +#define RDA_GPIO_LEVEL_SHIFT 24 + +#define RDA_GPIO_IRQ_MASK 0xff + +/* Each bank consists of 32 GPIOs */ +#define RDA_GPIO_BANK_NR 32 + +struct rda_gpio { + struct gpio_chip chip; + void __iomem *base; + spinlock_t lock; + struct irq_chip irq_chip; + int irq; +}; + +static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, + u16 reg, int val) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(&rda_gpio->lock, flags); + tmp = readl_relaxed(base + reg); + + if (val) + tmp |= BIT(offset); + else + tmp &= ~BIT(offset); + + writel_relaxed(tmp, base + reg); + spin_unlock_irqrestore(&rda_gpio->lock, flags); +} + +static void rda_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + u32 offset = irqd_to_hwirq(data); + u32 value; + + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); +} + +static void rda_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1); +} + +static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset, + unsigned int flow_type) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + u32 value; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + /* Set rising edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_EDGE_FALLING: + /* Set falling edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_EDGE_BOTH: + /* Set both edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_LEVEL_HIGH: + /* Set high level trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + + /* Switch to level trigger interrupt */ + value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + break; + + case IRQ_TYPE_LEVEL_LOW: + /* Set low level trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + + /* Switch to level trigger interrupt */ + value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static void rda_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + u32 trigger = irqd_get_trigger_type(data); + + rda_gpio_set_irq(chip, offset, trigger); +} + +static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + int ret; + + ret = rda_gpio_set_irq(chip, offset, flow_type); + if (ret) + return ret; + + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + irq_set_handler_locked(data, handle_level_irq); + else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + irq_set_handler_locked(data, handle_edge_irq); + + return 0; +} + +static void rda_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *ic = irq_desc_get_chip(desc); + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + unsigned long status; + u32 n, girq; + + chained_irq_enter(ic, desc); + + status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS); + /* Only lower 8 bits are capable of generating interrupts */ + status &= RDA_GPIO_IRQ_MASK; + + for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) { + girq = irq_find_mapping(chip->irq.domain, n); + generic_handle_irq(girq); + } + + chained_irq_exit(ic, desc); +} + +static int rda_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + struct rda_gpio *rda_gpio; + u32 ngpios; + int ret; + + rda_gpio = devm_kzalloc(dev, sizeof(*rda_gpio), GFP_KERNEL); + if (!rda_gpio) + return -ENOMEM; + + ret = device_property_read_u32(dev, "ngpios", &ngpios); + if (ret < 0) + return ret; + + /* + * Not all ports have interrupt capability. For instance, on + * RDA8810PL, GPIOC doesn't support interrupt. So we must handle + * those also. + */ + rda_gpio->irq = platform_get_irq(pdev, 0); + + rda_gpio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rda_gpio->base)) + return PTR_ERR(rda_gpio->base); + + spin_lock_init(&rda_gpio->lock); + + ret = bgpio_init(&rda_gpio->chip, dev, 4, + rda_gpio->base + RDA_GPIO_VAL, + rda_gpio->base + RDA_GPIO_SET, + rda_gpio->base + RDA_GPIO_CLR, + rda_gpio->base + RDA_GPIO_OEN_SET_OUT, + rda_gpio->base + RDA_GPIO_OEN_SET_IN, + BGPIOF_READ_OUTPUT_REG_SET); + if (ret) { + dev_err(dev, "bgpio_init failed\n"); + return ret; + } + + rda_gpio->chip.label = dev_name(dev); + rda_gpio->chip.ngpio = ngpios; + rda_gpio->chip.base = -1; + rda_gpio->chip.parent = dev; + rda_gpio->chip.of_node = np; + + if (rda_gpio->irq >= 0) { + rda_gpio->irq_chip.name = "rda-gpio", + rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack, + rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask, + rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask, + rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type, + rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE, + + girq = &rda_gpio->chip.irq; + girq->chip = &rda_gpio->irq_chip; + girq->handler = handle_bad_irq; + girq->default_type = IRQ_TYPE_NONE; + girq->parent_handler = rda_gpio_irq_handler; + girq->parent_handler_data = rda_gpio; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = rda_gpio->irq; + } + + platform_set_drvdata(pdev, rda_gpio); + + return devm_gpiochip_add_data(dev, &rda_gpio->chip, rda_gpio); +} + +static const struct of_device_id rda_gpio_of_match[] = { + { .compatible = "rda,8810pl-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rda_gpio_of_match); + +static struct platform_driver rda_gpio_driver = { + .probe = rda_gpio_probe, + .driver = { + .name = "rda-gpio", + .of_match_table = rda_gpio_of_match, + }, +}; + +module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe); + +MODULE_DESCRIPTION("RDA Micro GPIO driver"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2"); From patchwork Mon Oct 21 06:44:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 177035 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3000699ill; Sun, 20 Oct 2019 23:44:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTUlLbr7NSV6XjBdZwtAMJGK6qsmZR3YidfmIf/4Fx56VfsG/hamoUfz8wM0qhMUeW8yY1 X-Received: by 2002:a17:906:bfcb:: with SMTP id us11mr20446307ejb.299.1571640289572; Sun, 20 Oct 2019 23:44:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571640289; cv=none; d=google.com; s=arc-20160816; b=dZeC2/QWHMXuSdAbl1h/29J5+nbJ0EP8T/Kj+xu9bCyv1ptNgDH6wVN2+Hsb8LyYlT GH+QER3ADKWx/hztJrTje64yFjYxm71sGzhtIwlamWRc1XNW7+w70Fx/XFw1d/8oML4d wEwJvvacDCQktF8R8O1iCKudEOtNBae/f4ZJF6zfudniwNrk7M+Sr6nrgBnzyeQZAShJ vVuDDtHZtGOccmGlBpLkaRML2GWfRs0gpXNxD/xcx699g5vLFIDtr4JULtKJuiUVS/ug 9f3d4pVCweZ+RrbeughXZwwMN1VOWoQgR65wjl6VvZTXchNxEDcuIx5NWvgBJCq+/Ofb 0YIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=7S85Z16eqmxjvMi+R450sz/jCD08hapdQq20bxkJhIQ=; b=ZjW002TjT1Ic0aoUInMFt0h9wECuUGnj6i5IVhG6oN+XZV8l6dEttu7LEMD5mVZkJ9 hZpLgBMsap9KA5dWoSEk9Eq8vUYTdrSIIfFKFXVYWWxkrpzUjZhH6Nhmqxu3kl1ivWiU 5wxsZ2TTYWQZV2aWRawTLx1D20LtxVka4XzDUN+b/9GFKU//oyJzCv+o02aCxZvnUNgZ 5gkbd9SnVay7XDPACwJ5Y/+owtb23NdZslE1dtqzTqAQfPs6Ygr+2o94L82rj+QrjXSp BDt7++0bztqRovpckNLKh5kd1HT2SKi2M/8+oMJAvIKhLY2fp67I5gq2fiNs23DlWFk5 vF6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GuRCYZtG; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s17si650061ejr.229.2019.10.20.23.44.49; Sun, 20 Oct 2019 23:44:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GuRCYZtG; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726702AbfJUGos (ORCPT + 5 others); Mon, 21 Oct 2019 02:44:48 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:42465 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726645AbfJUGos (ORCPT ); Mon, 21 Oct 2019 02:44:48 -0400 Received: by mail-pg1-f193.google.com with SMTP id f14so7137664pgi.9 for ; Sun, 20 Oct 2019 23:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7S85Z16eqmxjvMi+R450sz/jCD08hapdQq20bxkJhIQ=; b=GuRCYZtGI6OJa6X8+/Ffb8CLtebpBzKn0NZw6zffUn9sUbMUSQw/2smdjQAyEdECD3 dMQoJ9gWZR/CRhS+tkhIG7O7tZtUVlouDhfhyiAQw2z97JpcLK7xPgBnhtxfLaA8tn65 uLzm7NNQq95muYyOqE612+gA7JyzPHObNYoj3nDvcwncyUqmu2oYZUqEOp2ew25NMmgo KN93tzSSewsfwDec/nSg8XESFTYjDhbU13AGcEXLTB3GLYNzOv7oMORl1H01diaRc26p bkEp1OO+6DilyontJxPS9m3bzCDZfJRqYjI5195khDfCWjZv4xw6ht9zGQk0/ZCOL6cw nQ2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7S85Z16eqmxjvMi+R450sz/jCD08hapdQq20bxkJhIQ=; b=lyGm4RTykzhvzRVfDd/jC/91yMGJyU+HxPx8wMDUqsENKWQddkRwex/d0y93uc3R5l FFVWQfZvrcT6AK1U9jYEXt1XxK+EmIbHm0MMwisGy7ZxDpipIdE15JTHgQwnhih8aNpi C1Z1c2YcQK6g4F6GoqA+RFxgZEHj9ZMfOfAT5N7eXjkgXa7g7BodoZpQzhsRKRWZnxdN HThH3wKHi/PrTcosfYnDse6OSl35U6N//0+nb5uXNz4Kt2VcscpJiWZ1TrSWBCOw+b3e 3lTkg+5yvst8WvFJPrx8VUJqzn1dBatFfoZFDpFb0trRANtmsZmsVnAL19npWI68Pf/J SMXw== X-Gm-Message-State: APjAAAXKMJ7AKH43ztlWODnfOZ9ru1Y0McHe7s0mr5P0u3gP015iGjlX 3gJWx5TOTfSmJpXxOJEV7RUC X-Received: by 2002:a63:2889:: with SMTP id o131mr24222845pgo.444.1571640285755; Sun, 20 Oct 2019 23:44:45 -0700 (PDT) Received: from localhost.localdomain ([2405:204:700f:8db6:2442:890f:ac37:8127]) by smtp.gmail.com with ESMTPSA id d4sm13156624pjs.9.2019.10.20.23.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2019 23:44:45 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, bgolaszewski@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, orsonzhai@gmail.com, Manivannan Sadhasivam Subject: [PATCH v3 4/4] MAINTAINERS: Add entry for RDA Micro GPIO driver and binding Date: Mon, 21 Oct 2019 12:14:13 +0530 Message-Id: <20191021064413.19840-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191021064413.19840-1-manivannan.sadhasivam@linaro.org> References: <20191021064413.19840-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add MAINTAINERS entry for RDA Micro GPIO driver and devicetree binding. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index a69e6db80c79..0303502cd146 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2150,9 +2150,11 @@ L: linux-unisoc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/rda8810pl-* F: drivers/clocksource/timer-rda.c +F: drivers/gpio/gpio-rda.c F: drivers/irqchip/irq-rda-intc.c F: drivers/tty/serial/rda-uart.c F: Documentation/devicetree/bindings/arm/rda.yaml +F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt