From patchwork Wed Jun 14 15:33:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105560 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp386171obh; Wed, 14 Jun 2017 08:25:48 -0700 (PDT) X-Received: by 10.101.75.134 with SMTP id t6mr579616pgq.191.1497453948037; Wed, 14 Jun 2017 08:25:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453948; cv=none; d=google.com; s=arc-20160816; b=D0mWN8q3tzaJ3c7tWEzxQ6YV+i7S/XRcBQd2p5Ux46KK47NrxTE5VOq1yFz8Zt+A4r XfIcUy5O+yrwRk3KdSDuncGncDbiqqqE0ZXJwl5KV2FTkdNISwqsjvIqbjMj1xXt5VtU URFmm6ARKV2HJ7SStiUHKxP4HimY2VstVxYEOLC+Un8TqOPtmOnubvaaIOZx7FFlMnue X9SH7BLHOKPqeG6NbMw+CxGHWafAt610Awjbf8LEc+iFE33dNs5KsspmNScYWPp1i8mJ qgATU0fG5qJtZcUHz+umoPfnxvc1yDWtU3i6w1Ni6qyf/ULW/RV8PUbdKMt5sbZxFSCb 6fmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=4Pep7ZyeMDlfuhXLRMkurEwtLRDkHm0fkdfkuIG7hMc=; b=oTTXQeriGrKKcTIH8U1boPZ2SZ+fOPvUYRHWEIy8QLABHtZAVRzObzvh5gA4Ej8mSS Wrc9aGbEinNpq7eQ+70YfebuMsklosD6W2xzQpSzfl6YMAGU0AKaUDGasvbPy6zEUIQ/ HEsQwitZ1BbXkOZz2j60oYCAJTUwW9/FkJ1fwQZoW/Fdce7q6Y6jeWpWLxsYeLsnJcxc YdfsKPiCTvRVnIUOxNVU+qjzOy9EfKFJadZoa62VeVWO+BP5g46PitaDQScWrGckD77e gW/ivbGztnwclrBhQ3hzWjmCycp9ZCUx3sRIiO25Z4FV/ZkIebORmxEA+hsivbmAoCkY bAoA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 27si192890pfr.232.2017.06.14.08.25.47; Wed, 14 Jun 2017 08:25:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752553AbdFNPZ1 (ORCPT + 25 others); Wed, 14 Jun 2017 11:25:27 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7836 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752444AbdFNPEF (ORCPT ); Wed, 14 Jun 2017 11:04:05 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60190; Wed, 14 Jun 2017 23:03:27 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:12 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 01/22] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() Date: Wed, 14 Jun 2017 23:33:11 +0800 Message-ID: <1497454412-91194-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.5941503F.0179, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 381afd88a4d56caf0efc618bfba7443e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen We need to check for timeout before task status, or the task will be mistook as completed internal abort command. Also add protection for sas_task.task_state_flags in hisi_sas_tmf_timedout(). Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index f720d3c..3605d28 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -691,8 +691,13 @@ static void hisi_sas_task_done(struct sas_task *task) static void hisi_sas_tmf_timedout(unsigned long data) { struct sas_task *task = (struct sas_task *)data; + unsigned long flags; + + spin_lock_irqsave(&task->task_state_lock, flags); + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) + task->task_state_flags |= SAS_TASK_STATE_ABORTED; + spin_unlock_irqrestore(&task->task_state_lock, flags); - task->task_state_flags |= SAS_TASK_STATE_ABORTED; complete(&task->slow_task->completion); } @@ -1247,6 +1252,17 @@ static int hisi_sas_query_task(struct sas_task *task) wait_for_completion(&task->slow_task->completion); res = TMF_RESP_FUNC_FAILED; + /* Internal abort timed out */ + if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) { + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { + struct hisi_sas_slot *slot = task->lldd_task; + + if (slot) + slot->task = NULL; + dev_err(dev, "internal task abort: timeout.\n"); + } + } + if (task->task_status.resp == SAS_TASK_COMPLETE && task->task_status.stat == TMF_RESP_FUNC_COMPLETE) { res = TMF_RESP_FUNC_COMPLETE; @@ -1259,13 +1275,6 @@ static int hisi_sas_query_task(struct sas_task *task) goto exit; } - /* Internal abort timed out */ - if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) { - if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { - dev_err(dev, "internal task abort: timeout.\n"); - } - } - exit: dev_dbg(dev, "internal task abort: task to dev %016llx task=%p " "resp: 0x%x sts 0x%x\n", From patchwork Wed Jun 14 15:33:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105534 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp338615qgd; Wed, 14 Jun 2017 08:05:27 -0700 (PDT) X-Received: by 10.84.228.201 with SMTP id y9mr598863pli.300.1497452727093; Wed, 14 Jun 2017 08:05:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452727; cv=none; d=google.com; s=arc-20160816; b=C7KwwkVcDM8cV3l/Tbe9igO9BtyPnX7TNhEnGVS1v7m1zphDhhY486v1Y4yytz2O1n MfQ1EiLQVWb6g85VHSS5qMtlJTXMhuK2AyBEo7vOG1V5Q9YOWKRaQ0vnPmHmBu/hF5u2 9aOcNvqlKXn+U0oJkrfcY+1a2oUCN8IT2BxkQ4Gg8cMWGTSIYnEe+xvKc0/1vAly/N5m 8R/lo3nG2NI2CYXQMcdFPe7cPan1J+1PSUSkqQwTNWcZ9rF+LWmvcCX/0RzZ4XUH2Yh3 KxvmPpSBUAbiTJCYXeCd0S7wfJU9L4X3Y+4RCWYRChCqKdFgZ8PTyPkDoIcSPz0erru9 mpLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=W3ZENiT6rbuOaL1qWYIvO/P+NXsy2fHe91r2sPp9dZ8=; b=koyUKAGaA+BSFfVY41HVR2V0e36XyJWDDgwjjCq7frNdi7IB/G/S9fltouoSqm3mF7 KNMg8pEzP2NEtVmcgNNhGqExNuCIxd/TrbKV4KyyT50mZwd2pkfubzdwDjMZ0lbgevfT BHJHXuBPBE2o3f3ckEeQVjNCD2EsnSb0CfYOEzYz5liEhoom6pbvWbLcLIGUG/f03TZH 5lHJBd6e8NPkDi1VoHzX8m2uwrDTxiuueVcIP3bQayqwbHIAmW83Gv4k3ItyN76L4yJc D+pu1ssNx1XjTXKkljeHw8qcxo3a5qqzDRoK36cNSeWc+UztvGAFvNnVmMxmgWeHTIkA 1FBw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h26si166442pfk.157.2017.06.14.08.05.26; Wed, 14 Jun 2017 08:05:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752702AbdFNPFF (ORCPT + 25 others); Wed, 14 Jun 2017 11:05:05 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7849 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752611AbdFNPEU (ORCPT ); Wed, 14 Jun 2017 11:04:20 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60188; Wed, 14 Jun 2017 23:03:27 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:12 +0800 From: John Garry To: , CC: , , , , , "John Garry" Subject: [PATCH v6 02/22] scsi: hisi_sas: define hisi_sas_device.device_id as int Date: Wed, 14 Jun 2017 23:33:12 +0800 Message-ID: <1497454412-91194-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503F.013D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7cc3aac2cd29781ac2cb0fff08d9c811 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently hisi_sas_device.device_id is a u64. This can create a problem in selecting the queue for a device, in that this code does a 64b division on device id. For some 32b systems, 64b division is slow and the lib reference must be explicitly included. The device id does not need to be 64b in size, so, as a solution, just make as an int. Also, struct hisi_sas_device elements are re-ordered to improve packing efficiency. Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 8 ++++---- drivers/scsi/hisi_sas/hisi_sas_main.c | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 4e28f32..b4e96fa9 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -107,15 +107,15 @@ struct hisi_sas_dq { }; struct hisi_sas_device { - enum sas_device_type dev_type; struct hisi_hba *hisi_hba; struct domain_device *sas_device; + struct list_head list; u64 attached_phy; - u64 device_id; atomic64_t running_req; - struct list_head list; - u8 dev_status; + enum sas_device_type dev_type; + int device_id; int sata_idx; + u8 dev_status; }; struct hisi_sas_slot { diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 3605d28..54e0cf2 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -209,7 +209,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, if (DEV_IS_GONE(sas_dev)) { if (sas_dev) - dev_info(dev, "task prep: device %llu not ready\n", + dev_info(dev, "task prep: device %d not ready\n", sas_dev->device_id); else dev_info(dev, "task prep: device %016llx not ready\n", @@ -627,9 +627,9 @@ static void hisi_sas_dev_gone(struct domain_device *device) struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); struct device *dev = &hisi_hba->pdev->dev; - u64 dev_id = sas_dev->device_id; + int dev_id = sas_dev->device_id; - dev_info(dev, "found dev[%lld:%x] is gone\n", + dev_info(dev, "found dev[%d:%x] is gone\n", sas_dev->device_id, sas_dev->dev_type); hisi_sas_internal_task_abort(hisi_hba, device, @@ -1082,7 +1082,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun) } out: if (rc != TMF_RESP_FUNC_COMPLETE) - dev_err(dev, "lu_reset: for device[%llx]:rc= %d\n", + dev_err(dev, "lu_reset: for device[%d]:rc= %d\n", sas_dev->device_id, rc); return rc; } @@ -1129,7 +1129,7 @@ static int hisi_sas_query_task(struct sas_task *task) } static int -hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, u64 device_id, +hisi_sas_internal_abort_task_exec(struct hisi_hba *hisi_hba, int device_id, struct sas_task *task, int abort_flag, int task_tag) { From patchwork Wed Jun 14 15:33:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105539 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp380227obh; Wed, 14 Jun 2017 08:11:28 -0700 (PDT) X-Received: by 10.84.195.129 with SMTP id j1mr604880pld.191.1497453088549; Wed, 14 Jun 2017 08:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453088; cv=none; d=google.com; s=arc-20160816; b=Ady9X2pSBszJnuYzs9SzMCeWU31HhnxAYK0TXlM9Kx3/Nx+j/HjNxUImeqhBOriJTv hGLF+wuiv7gPSh+zBDVpP9xdLyz01dZIzhgl3BKQ035cX6ngUTOuz6AulTK0lqd8Pk3L EmAN8X+pzpv+FIaGWe3O7CM8tNZZgbpjvjYZQ+YegrMabvyvb4mMG8kAUpAgcUIz9kUX 3mFjYjjfsp8QBhvgGFknbc4XwZdZVWnsjYvvyfqQ0kp/VHyubVEVM5PLQUsg0oKDmdcz 5145OjS9PKZezACHsrL3C1Xi+If9U1Xzmjw7ITXPP5zlEViDP0MB2We0vnFuixBXssIL 0T3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=TfF64U3Usr7N02B3pGFPW0oB61XQu0OpA3EIMP8Llro=; b=kL0xM+qTOWojAJW8Qs46/rzbpwMe5ZvsQDL4ZudDZ88SS8mp9BM9F3XMz+BBSVG5gI 2INs58ZEp+k3zGu3s60fUB0/Bmd4EB7vQNnRhyugk2b5MNzccfs9EHbi0Dt1wSYlopO5 V4sbzneaRPPe/0ppd6eMN6u0ToLYUVOFYNyjHjWERuLi++uuph//yBgFOYLXy5ZjIcf0 4BIWrcftGIDyF3dXT9VBvpiOYd4UOHj+Vvoeq8sWt67pGlVFT3Akm0x18GVAH8KcmFol qNw9jS0Z1T4y9s62gpH5/q6dVsbnDrQ3JjWhPIETeIETKv42nzT29et/xgBGmlgnybjS 78gg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a1si204377pln.417.2017.06.14.08.11.28; Wed, 14 Jun 2017 08:11:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752590AbdFNPEQ (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:16 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7846 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752523AbdFNPEM (ORCPT ); Wed, 14 Jun 2017 11:04:12 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60185; Wed, 14 Jun 2017 23:03:26 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:13 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 03/22] scsi: hisi_sas: optimise the usage of hisi_hba.lock Date: Wed, 14 Jun 2017 23:33:13 +0800 Message-ID: <1497454412-91194-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503E.01F2, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 0639bf043732e8a24193886ee645e68a Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Currently hisi_hba.lock is locked to deliver and receive a command to/from any hw queue. This causes much contention at high data-rates. To boost performance, lock on a per queue basis for sending and receiving commands to/from hw. Certain critical regions still need to be locked in the delivery and completion stages with hisi_hba.lock. New element hisi_sas_device.dq is added to store the delivery queue for a device, so it does not need to be needlessly re-calculated for every task. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 9 +++-- drivers/scsi/hisi_sas/hisi_sas_main.c | 69 +++++++++++++++++++++++----------- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 23 ++++-------- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 34 ++++++++--------- 4 files changed, 77 insertions(+), 58 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index b4e96fa9..68ba7bd 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -102,6 +102,8 @@ struct hisi_sas_cq { struct hisi_sas_dq { struct hisi_hba *hisi_hba; + struct hisi_sas_slot *slot_prep; + spinlock_t lock; int wr_point; int id; }; @@ -109,6 +111,7 @@ struct hisi_sas_dq { struct hisi_sas_device { struct hisi_hba *hisi_hba; struct domain_device *sas_device; + struct hisi_sas_dq *dq; struct list_head list; u64 attached_phy; atomic64_t running_req; @@ -154,9 +157,8 @@ struct hisi_sas_hw { struct domain_device *device); struct hisi_sas_device *(*alloc_dev)(struct domain_device *device); void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no); - int (*get_free_slot)(struct hisi_hba *hisi_hba, u32 dev_id, - int *q, int *s); - void (*start_delivery)(struct hisi_hba *hisi_hba); + int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq); + void (*start_delivery)(struct hisi_sas_dq *dq); int (*prep_ssp)(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, int is_tmf, struct hisi_sas_tmf_task *tmf); @@ -217,7 +219,6 @@ struct hisi_hba { struct hisi_sas_port port[HISI_SAS_MAX_PHYS]; int queue_count; - struct hisi_sas_slot *slot_prep; struct dma_pool *sge_page_pool; struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES]; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 54e0cf2..4e78cbc 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -179,10 +179,11 @@ static void hisi_sas_slot_abort(struct work_struct *work) task->task_done(task); } -static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, - int is_tmf, struct hisi_sas_tmf_task *tmf, - int *pass) +static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq + *dq, int is_tmf, struct hisi_sas_tmf_task *tmf, + int *pass) { + struct hisi_hba *hisi_hba = dq->hisi_hba; struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_sas_port *port; @@ -240,18 +241,24 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, } else n_elem = task->num_scatter; + spin_lock_irqsave(&hisi_hba->lock, flags); if (hisi_hba->hw->slot_index_alloc) rc = hisi_hba->hw->slot_index_alloc(hisi_hba, &slot_idx, device); else rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx); - if (rc) + if (rc) { + spin_unlock_irqrestore(&hisi_hba->lock, flags); goto err_out; - rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id, - &dlvry_queue, &dlvry_queue_slot); + } + spin_unlock_irqrestore(&hisi_hba->lock, flags); + + rc = hisi_hba->hw->get_free_slot(hisi_hba, dq); if (rc) goto err_out_tag; + dlvry_queue = dq->id; + dlvry_queue_slot = dq->wr_point; slot = &hisi_hba->slot_info[slot_idx]; memset(slot, 0, sizeof(struct hisi_sas_slot)); @@ -316,7 +323,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); - hisi_hba->slot_prep = slot; + dq->slot_prep = slot; atomic64_inc(&sas_dev->running_req); ++(*pass); @@ -335,7 +342,9 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba, err_out_slot_buf: /* Nothing to be done */ err_out_tag: + spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_slot_index_free(hisi_hba, slot_idx); + spin_unlock_irqrestore(&hisi_hba->lock, flags); err_out: dev_err(dev, "task prep: failed[%d]!\n", rc); if (!sas_protocol_ata(task->task_proto)) @@ -354,19 +363,22 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags, unsigned long flags; struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev); struct device *dev = &hisi_hba->pdev->dev; + struct domain_device *device = task->dev; + struct hisi_sas_device *sas_dev = device->lldd_dev; + struct hisi_sas_dq *dq = sas_dev->dq; if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))) return -EINVAL; /* protect task_prep and start_delivery sequence */ - spin_lock_irqsave(&hisi_hba->lock, flags); - rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass); + spin_lock_irqsave(&dq->lock, flags); + rc = hisi_sas_task_prep(task, dq, is_tmf, tmf, &pass); if (rc) dev_err(dev, "task exec: failed[%d]!\n", rc); if (likely(pass)) - hisi_hba->hw->start_delivery(hisi_hba); - spin_unlock_irqrestore(&hisi_hba->lock, flags); + hisi_hba->hw->start_delivery(dq); + spin_unlock_irqrestore(&dq->lock, flags); return rc; } @@ -421,12 +433,16 @@ static struct hisi_sas_device *hisi_sas_alloc_dev(struct domain_device *device) spin_lock(&hisi_hba->lock); for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { + int queue = i % hisi_hba->queue_count; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; + hisi_hba->devices[i].device_id = i; sas_dev = &hisi_hba->devices[i]; sas_dev->dev_status = HISI_SAS_DEV_NORMAL; sas_dev->dev_type = device->dev_type; sas_dev->hisi_hba = hisi_hba; sas_dev->sas_device = device; + sas_dev->dq = dq; INIT_LIST_HEAD(&hisi_hba->devices[i].list); break; } @@ -1140,8 +1156,9 @@ static int hisi_sas_query_task(struct sas_task *task) struct hisi_sas_slot *slot; struct asd_sas_port *sas_port = device->port; struct hisi_sas_cmd_hdr *cmd_hdr_base; + struct hisi_sas_dq *dq = sas_dev->dq; int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx; - unsigned long flags; + unsigned long flags, flags_dq; if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))) return -EINVAL; @@ -1152,14 +1169,22 @@ static int hisi_sas_query_task(struct sas_task *task) port = to_hisi_sas_port(sas_port); /* simply get a slot and send abort command */ + spin_lock_irqsave(&hisi_hba->lock, flags); rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx); - if (rc) + if (rc) { + spin_unlock_irqrestore(&hisi_hba->lock, flags); goto err_out; - rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id, - &dlvry_queue, &dlvry_queue_slot); + } + spin_unlock_irqrestore(&hisi_hba->lock, flags); + + spin_lock_irqsave(&dq->lock, flags_dq); + rc = hisi_hba->hw->get_free_slot(hisi_hba, dq); if (rc) goto err_out_tag; + dlvry_queue = dq->id; + dlvry_queue_slot = dq->wr_point; + slot = &hisi_hba->slot_info[slot_idx]; memset(slot, 0, sizeof(struct hisi_sas_slot)); @@ -1186,17 +1211,21 @@ static int hisi_sas_query_task(struct sas_task *task) task->task_state_flags |= SAS_TASK_AT_INITIATOR; spin_unlock_irqrestore(&task->task_state_lock, flags); - hisi_hba->slot_prep = slot; + dq->slot_prep = slot; atomic64_inc(&sas_dev->running_req); - /* send abort command to our chip */ - hisi_hba->hw->start_delivery(hisi_hba); + /* send abort command to the chip */ + hisi_hba->hw->start_delivery(dq); + spin_unlock_irqrestore(&dq->lock, flags_dq); return 0; err_out_tag: + spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_slot_index_free(hisi_hba, slot_idx); + spin_unlock_irqrestore(&hisi_hba->lock, flags); + spin_unlock_irqrestore(&dq->lock, flags_dq); err_out: dev_err(dev, "internal abort task prep: failed[%d]!\n", rc); @@ -1221,7 +1250,6 @@ static int hisi_sas_query_task(struct sas_task *task) struct hisi_sas_device *sas_dev = device->lldd_dev; struct device *dev = &hisi_hba->pdev->dev; int res; - unsigned long flags; if (!hisi_hba->hw->prep_abort) return -EOPNOTSUPP; @@ -1238,11 +1266,8 @@ static int hisi_sas_query_task(struct sas_task *task) task->slow_task->timer.expires = jiffies + msecs_to_jiffies(110); add_timer(&task->slow_task->timer); - /* Lock as we are alloc'ing a slot, which cannot be interrupted */ - spin_lock_irqsave(&hisi_hba->lock, flags); res = hisi_sas_internal_abort_task_exec(hisi_hba, sas_dev->device_id, task, abort_flag, tag); - spin_unlock_irqrestore(&hisi_hba->lock, flags); if (res) { del_timer(&task->slow_task->timer); dev_err(dev, "internal task abort: executing internal task failed: %d\n", diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c index fc1c1b2..7d7d2a7 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c @@ -900,22 +900,17 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) return bitmap; } -/** - * This function allocates across all queues to load balance. - * Slots are allocated from queues in a round-robin fashion. - * +/* * The callpath to this function and upto writing the write * queue pointer should be safe from interruption. */ -static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id, - int *q, int *s) +static int +get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { struct device *dev = &hisi_hba->pdev->dev; - struct hisi_sas_dq *dq; + int queue = dq->id; u32 r, w; - int queue = dev_id % hisi_hba->queue_count; - dq = &hisi_hba->dq[queue]; w = dq->wr_point; r = hisi_sas_read32_relaxed(hisi_hba, DLVRY_Q_0_RD_PTR + (queue * 0x14)); @@ -924,16 +919,14 @@ static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id, return -EAGAIN; } - *q = queue; - *s = w; return 0; } -static void start_delivery_v1_hw(struct hisi_hba *hisi_hba) +static void start_delivery_v1_hw(struct hisi_sas_dq *dq) { - int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; - int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; - struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index e241921..2607aac 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -695,6 +695,9 @@ hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) if (sata_dev && (i & 1)) continue; if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { + int queue = i % hisi_hba->queue_count; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; + hisi_hba->devices[i].device_id = i; sas_dev = &hisi_hba->devices[i]; sas_dev->dev_status = HISI_SAS_DEV_NORMAL; @@ -702,6 +705,7 @@ hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) sas_dev->hisi_hba = hisi_hba; sas_dev->sas_device = device; sas_dev->sata_idx = sata_idx; + sas_dev->dq = dq; INIT_LIST_HEAD(&hisi_hba->devices[i].list); break; } @@ -1454,22 +1458,17 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) return bitmap; } -/** - * This function allocates across all queues to load balance. - * Slots are allocated from queues in a round-robin fashion. - * +/* * The callpath to this function and upto writing the write * queue pointer should be safe from interruption. */ -static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id, - int *q, int *s) +static int +get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { struct device *dev = &hisi_hba->pdev->dev; - struct hisi_sas_dq *dq; + int queue = dq->id; u32 r, w; - int queue = dev_id % hisi_hba->queue_count; - dq = &hisi_hba->dq[queue]; w = dq->wr_point; r = hisi_sas_read32_relaxed(hisi_hba, DLVRY_Q_0_RD_PTR + (queue * 0x14)); @@ -1479,16 +1478,14 @@ static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id, return -EAGAIN; } - *q = queue; - *s = w; return 0; } -static void start_delivery_v2_hw(struct hisi_hba *hisi_hba) +static void start_delivery_v2_hw(struct hisi_sas_dq *dq) { - int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; - int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; - struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), @@ -2344,7 +2341,9 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, spin_lock_irqsave(&task->task_state_lock, flags); task->task_state_flags |= SAS_TASK_STATE_DONE; spin_unlock_irqrestore(&task->task_state_lock, flags); + spin_lock_irqsave(&hisi_hba->lock, flags); hisi_sas_slot_task_free(hisi_hba, task, slot); + spin_unlock_irqrestore(&hisi_hba->lock, flags); sts = ts->stat; if (task->task_done) @@ -3162,13 +3161,14 @@ static void cq_tasklet_v2_hw(unsigned long val) struct hisi_sas_complete_v2_hdr *complete_queue; u32 rd_point = cq->rd_point, wr_point, dev_id; int queue = cq->id; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; if (unlikely(hisi_hba->reject_stp_links_msk)) phys_try_accept_stp_links_v2_hw(hisi_hba); complete_queue = hisi_hba->complete_hdr[queue]; - spin_lock(&hisi_hba->lock); + spin_lock(&dq->lock); wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + (0x14 * queue)); @@ -3218,7 +3218,7 @@ static void cq_tasklet_v2_hw(unsigned long val) /* update rd_point */ cq->rd_point = rd_point; hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); - spin_unlock(&hisi_hba->lock); + spin_unlock(&dq->lock); } static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) From patchwork Wed Jun 14 15:33:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105536 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp338956qgd; Wed, 14 Jun 2017 08:06:01 -0700 (PDT) X-Received: by 10.84.233.130 with SMTP id l2mr609245plk.212.1497452761038; Wed, 14 Jun 2017 08:06:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452761; cv=none; d=google.com; s=arc-20160816; b=aYLgdks+0B4pRemnRSxC2ErE9UIbFxFxsU6oQFJobllA7q+8//hvnpwYPK7nbpdomt jLNPTnqGTHsiq6J/ch4VZHL7WJjPEHli7VjNXdwWJODZVwRCuuRqp2H72+yRmy5BtgpR fUiwc6yDF+G5P3tw1Z46leuWyVUagVwwv1z8nt4IH6Pi1d0U5ywlNxG069r7uGyDz7Hl Rno8qJ6QWKmkvqAgzVf/2EcMCntWoJex8dZQS92rwdCgQtN8jv+lFw3Uhflcy/x+f1eH pLee/GrK8OMFk+O0ff3FbI69/drvY39llYjnJf5c0QRr4wbv9SeW7enha5/DIWowrrq9 /lkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=2gpXJGR3uuM9PFXzdAd4AuxxZb4yhFmXiL7s8bQDfR4=; b=G1mMNYrr/i85lvnZHrtEUeYDQDmscXBiqQijnM9ArNera137fSmaw0mYVALOS1uJXA BGDcvv5fNeCLZj+sy3Cd3TtwilusqrntShxJoQnp8ctbI1Sx1IqBKeQc2yjOsWKutG8d 1z1ViC8qQwTEs7lt+vloWLBOIxekygISkKCweaHbptSG6Bpkn+zduDyWB0ukcMA89DRC 5BQ7UNGW7EsNsUvOEtlGDgtQSl7lYYSzMNAJCsuPVhFnvMx9ucasoJJAGqp0+lip81s7 7y8EbMMrsFT44Hes2/FXvjaOZ5R8oMEcLw74s2hmfsYIyHCr6RLKl8FgZLNuazK7iSs2 j6tA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x127si160312pfx.257.2017.06.14.08.06.00; Wed, 14 Jun 2017 08:06:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752746AbdFNPFp (ORCPT + 25 others); Wed, 14 Jun 2017 11:05:45 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7850 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752583AbdFNPER (ORCPT ); Wed, 14 Jun 2017 11:04:17 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60181; Wed, 14 Jun 2017 23:03:25 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:13 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 04/22] scsi: hisi_sas: relocate get_ata_protocol() Date: Wed, 14 Jun 2017 23:33:14 +0800 Message-ID: <1497454412-91194-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.5941503F.006F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 529bc35ccf2770e8690fcf7c306e3b6c Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Relocate get_ata_protocol() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 7 ++++ drivers/scsi/hisi_sas/hisi_sas_main.c | 59 ++++++++++++++++++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 67 +--------------------------------- 3 files changed, 68 insertions(+), 65 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 68ba7bd..a50c699 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -46,6 +46,12 @@ ((type == SAS_EDGE_EXPANDER_DEVICE) || \ (type == SAS_FANOUT_EXPANDER_DEVICE)) +#define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1 +#define HISI_SAS_SATA_PROTOCOL_PIO 0x2 +#define HISI_SAS_SATA_PROTOCOL_DMA 0x4 +#define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8 +#define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10 + struct hisi_hba; enum { @@ -356,6 +362,7 @@ struct hisi_sas_command_table_ssp { struct hisi_sas_command_table_stp stp; }; +extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction); extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 4e78cbc..5b51d9a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -23,6 +23,65 @@ static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device, int abort_flag, int tag); static int hisi_sas_softreset_ata_disk(struct domain_device *device); +u8 hisi_sas_get_ata_protocol(u8 cmd, int direction) +{ + switch (cmd) { + case ATA_CMD_FPDMA_WRITE: + case ATA_CMD_FPDMA_READ: + case ATA_CMD_FPDMA_RECV: + case ATA_CMD_FPDMA_SEND: + case ATA_CMD_NCQ_NON_DATA: + return HISI_SAS_SATA_PROTOCOL_FPDMA; + + case ATA_CMD_DOWNLOAD_MICRO: + case ATA_CMD_ID_ATA: + case ATA_CMD_PMP_READ: + case ATA_CMD_READ_LOG_EXT: + case ATA_CMD_PIO_READ: + case ATA_CMD_PIO_READ_EXT: + case ATA_CMD_PMP_WRITE: + case ATA_CMD_WRITE_LOG_EXT: + case ATA_CMD_PIO_WRITE: + case ATA_CMD_PIO_WRITE_EXT: + return HISI_SAS_SATA_PROTOCOL_PIO; + + case ATA_CMD_DSM: + case ATA_CMD_DOWNLOAD_MICRO_DMA: + case ATA_CMD_PMP_READ_DMA: + case ATA_CMD_PMP_WRITE_DMA: + case ATA_CMD_READ: + case ATA_CMD_READ_EXT: + case ATA_CMD_READ_LOG_DMA_EXT: + case ATA_CMD_READ_STREAM_DMA_EXT: + case ATA_CMD_TRUSTED_RCV_DMA: + case ATA_CMD_TRUSTED_SND_DMA: + case ATA_CMD_WRITE: + case ATA_CMD_WRITE_EXT: + case ATA_CMD_WRITE_FUA_EXT: + case ATA_CMD_WRITE_QUEUED: + case ATA_CMD_WRITE_LOG_DMA_EXT: + case ATA_CMD_WRITE_STREAM_DMA_EXT: + return HISI_SAS_SATA_PROTOCOL_DMA; + + case ATA_CMD_CHK_POWER: + case ATA_CMD_DEV_RESET: + case ATA_CMD_EDD: + case ATA_CMD_FLUSH: + case ATA_CMD_FLUSH_EXT: + case ATA_CMD_VERIFY: + case ATA_CMD_VERIFY_EXT: + case ATA_CMD_SET_FEATURES: + case ATA_CMD_STANDBY: + case ATA_CMD_STANDBYNOW1: + return HISI_SAS_SATA_PROTOCOL_NONDATA; + default: + if (direction == DMA_NONE) + return HISI_SAS_SATA_PROTOCOL_NONDATA; + return HISI_SAS_SATA_PROTOCOL_PIO; + } +} +EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 2607aac..d9314c4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -554,12 +554,6 @@ enum { #define DIR_TO_DEVICE 2 #define DIR_RESERVED 3 -#define SATA_PROTOCOL_NONDATA 0x1 -#define SATA_PROTOCOL_PIO 0x2 -#define SATA_PROTOCOL_DMA 0x4 -#define SATA_PROTOCOL_FPDMA 0x8 -#define SATA_PROTOCOL_ATAPI 0x10 - #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \ err_phase == 0x4 || err_phase == 0x8 ||\ err_phase == 0x6 || err_phase == 0xa) @@ -2352,64 +2346,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, return sts; } -static u8 get_ata_protocol(u8 cmd, int direction) -{ - switch (cmd) { - case ATA_CMD_FPDMA_WRITE: - case ATA_CMD_FPDMA_READ: - case ATA_CMD_FPDMA_RECV: - case ATA_CMD_FPDMA_SEND: - case ATA_CMD_NCQ_NON_DATA: - return SATA_PROTOCOL_FPDMA; - - case ATA_CMD_DOWNLOAD_MICRO: - case ATA_CMD_ID_ATA: - case ATA_CMD_PMP_READ: - case ATA_CMD_READ_LOG_EXT: - case ATA_CMD_PIO_READ: - case ATA_CMD_PIO_READ_EXT: - case ATA_CMD_PMP_WRITE: - case ATA_CMD_WRITE_LOG_EXT: - case ATA_CMD_PIO_WRITE: - case ATA_CMD_PIO_WRITE_EXT: - return SATA_PROTOCOL_PIO; - - case ATA_CMD_DSM: - case ATA_CMD_DOWNLOAD_MICRO_DMA: - case ATA_CMD_PMP_READ_DMA: - case ATA_CMD_PMP_WRITE_DMA: - case ATA_CMD_READ: - case ATA_CMD_READ_EXT: - case ATA_CMD_READ_LOG_DMA_EXT: - case ATA_CMD_READ_STREAM_DMA_EXT: - case ATA_CMD_TRUSTED_RCV_DMA: - case ATA_CMD_TRUSTED_SND_DMA: - case ATA_CMD_WRITE: - case ATA_CMD_WRITE_EXT: - case ATA_CMD_WRITE_FUA_EXT: - case ATA_CMD_WRITE_QUEUED: - case ATA_CMD_WRITE_LOG_DMA_EXT: - case ATA_CMD_WRITE_STREAM_DMA_EXT: - return SATA_PROTOCOL_DMA; - - case ATA_CMD_CHK_POWER: - case ATA_CMD_DEV_RESET: - case ATA_CMD_EDD: - case ATA_CMD_FLUSH: - case ATA_CMD_FLUSH_EXT: - case ATA_CMD_VERIFY: - case ATA_CMD_VERIFY_EXT: - case ATA_CMD_SET_FEATURES: - case ATA_CMD_STANDBY: - case ATA_CMD_STANDBYNOW1: - return SATA_PROTOCOL_NONDATA; - default: - if (direction == DMA_NONE) - return SATA_PROTOCOL_NONDATA; - return SATA_PROTOCOL_PIO; - } -} - static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) { struct ata_queued_cmd *qc = task->uldd_task; @@ -2464,7 +2400,8 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, (task->ata_task.fis.control & ATA_SRST)) dw1 |= 1 << CMD_HDR_RESET_OFF; - dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir)) + dw1 |= (hisi_sas_get_ata_protocol( + task->ata_task.fis.command, task->data_dir)) << CMD_HDR_FRAME_TYPE_OFF; dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; hdr->dw1 = cpu_to_le32(dw1); From patchwork Wed Jun 14 15:33:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105544 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp380721obh; Wed, 14 Jun 2017 08:12:32 -0700 (PDT) X-Received: by 10.99.109.196 with SMTP id i187mr581563pgc.56.1497453152126; Wed, 14 Jun 2017 08:12:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453152; cv=none; d=google.com; s=arc-20160816; b=Rs07OLeox86OLsWgQJhfLU/tfD6QqWsHVz+U/UCLURSvmcbN6ccANv6EF0WI2Qa7gl 6P01/03qvtWqVEA47LVwUkl2+6ajwXMWs9NismrIdYaUnMYLWpaQTkH3tJkphU2pVqAU tNK5tQ7gXMwT+KCFsADoM+SiWZeCiZPUfmLy6gBXxGjYGlqPQIhb4nXsLYa02e1OsNAf T0NE+5Qmmxad/rAfUb4ahoVvsoCHG44NOVm+nWUX25LoCcUwGi+n0tupboCwZdJU/ou8 LIfdl2dULCFS9IQnaUMpYGsU7YoM9h/J2eTUDYxSlh1Pvp3JuoBgJfdaahkhbc++KZH0 L2nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=hTU6FcKRzYn4MeODggqcO6fzk0wM5EkizSeHBSEik5A=; b=aTTjw5lDy2kGTyJ7N3xRYNqZtrOVNxFduVPDMeuBRySj8DTPmq7BGeeUg/C7HURlD6 ar5N9aIpiZoRj+BgXkTyBDrMWJG8IBq7wVChDL+484p91rs9yZ8RnPwrGFjl9VcKeG4H YZ9E+oWBq90janvrs+JmNzB46VeyMvYU+/R6eWX+Gwgq5AvqkIQY9eAq+z0FFVuSSklj xuIuNqHZVMHQebkjN0yPg0nRvg5WGZIp6A8FOwlmc97LbJMriQQ3ZX0CCIdPrdaZgLRV 1b7mapIIm/jW3v5wVvF+UUi3JoUuoMDVYfCZP6ezC4UfK3jOMFUUgs7eFUd48tofeBmI 0AAQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v30si168561pfl.262.2017.06.14.08.12.26; Wed, 14 Jun 2017 08:12:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752723AbdFNPMZ (ORCPT + 25 others); Wed, 14 Jun 2017 11:12:25 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7845 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752186AbdFNPEL (ORCPT ); Wed, 14 Jun 2017 11:04:11 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60189; Wed, 14 Jun 2017 23:03:27 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:13 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 05/22] scsi: hisi_sas: relocate sata_done_v2_hw() Date: Wed, 14 Jun 2017 23:33:15 +0800 Message-ID: <1497454412-91194-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503F.01C4, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 104afa7725abb94c2f99473c54215405 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Relocate get_ata_protocol() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 18 ++---------------- 3 files changed, 19 insertions(+), 16 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index a50c699..1dcdf66 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -364,6 +364,8 @@ struct hisi_sas_command_table_ssp { extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction); extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); +extern void hisi_sas_sata_done(struct sas_task *task, + struct hisi_sas_slot *slot); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); extern int hisi_sas_remove(struct platform_device *pdev); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 5b51d9a..ab133d4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -82,6 +82,21 @@ u8 hisi_sas_get_ata_protocol(u8 cmd, int direction) } EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol); +void hisi_sas_sata_done(struct sas_task *task, + struct hisi_sas_slot *slot) +{ + struct task_status_struct *ts = &task->task_status; + struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; + struct dev_to_host_fis *d2h = slot->status_buffer + + sizeof(struct hisi_sas_err_record); + + resp->frame_len = sizeof(struct dev_to_host_fis); + memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); + + ts->buf_valid_size = sizeof(*resp); +} +EXPORT_SYMBOL_GPL(hisi_sas_sata_done); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index d9314c4..fdd7019 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -1683,20 +1683,6 @@ static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba, return 0; } -static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, - struct hisi_sas_slot *slot) -{ - struct task_status_struct *ts = &task->task_status; - struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; - struct dev_to_host_fis *d2h = slot->status_buffer + - sizeof(struct hisi_sas_err_record); - - resp->frame_len = sizeof(struct dev_to_host_fis); - memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); - - ts->buf_valid_size = sizeof(*resp); -} - #define TRANS_TX_ERR 0 #define TRANS_RX_ERR 1 #define DMA_TX_ERR 2 @@ -2189,7 +2175,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, break; } } - sata_done_v2_hw(hisi_hba, task, slot); + hisi_sas_sata_done(task, slot); } break; default: @@ -2317,7 +2303,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: { ts->stat = SAM_STAT_GOOD; - sata_done_v2_hw(hisi_hba, task, slot); + hisi_sas_sata_done(task, slot); break; } default: From patchwork Wed Jun 14 15:33:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105545 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp381082obh; Wed, 14 Jun 2017 08:13:20 -0700 (PDT) X-Received: by 10.99.151.1 with SMTP id n1mr527788pge.255.1497453198669; Wed, 14 Jun 2017 08:13:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453198; cv=none; d=google.com; s=arc-20160816; b=NkWF5lJTXyjb9djzWRVmUwJNenvb1f/LVgBguPivNsPAYD655iReFuwJSsrW+FdIAP w/hLzVUDiT+D+6B/XALQnjzlCwe5S0tgezfXgqtKKNlFLLWkjj9IsZ6gdr8cdsfg6fL7 +1TaAWsN1DYFjUzXMFfOx8adqEY6M17ta1MH1qc+syT8ugzAd0X1xlmBUh4SFxg8c0aL hJIomhqucDOkLXQn7qvwfaOWK1FrwMBd2Kty2T1kg7+Y7UjioJ19yZv+R0LEWrRYOoEs ZneZG2B0Vkm31HtvEiqyymYgcZ6VRA3KpmWn+VxhY1X07/Iu0mSBqKJ9h1kk6ojTrS9N ewbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=3qetzJhlNea2SLJPJxyfx/Tr1rkcl4DBR6zp8uGoOCI=; b=C+eRXDAgjMLeDgBd6q78eBFfZUO6bDQY/MH+H5yZ7SZG8rTGvGY+x3jiOijWoSIOSr /iVM2XXFOofuJXktsvwEx+k8K/alG7IRlZHbyhpHpRMNuULRpoewQ/oBaiEsbyDbKRpl 1Mgn/9gommc7d4QQeJZ/lh9Qhx1N4c/yr77jPlmZ/4S4vVyUXRlCfjcAqCm6bTu7gnAB Lj0dg1Wsr6OrAKwjxdh3jwY+i4s6iej5OmYPuxFV+4Xg2xp2n1u9ZUuO7rSkGb6W2fce vTlXC0caAuFe+38FVCPJG++SA4kFE+ot/rXP4qbzH5UWTLrWjqGO8+h/VX4rfU1o8JFS dvoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s9si182514pge.240.2017.06.14.08.13.18; Wed, 14 Jun 2017 08:13:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752904AbdFNPNE (ORCPT + 25 others); Wed, 14 Jun 2017 11:13:04 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7842 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752493AbdFNPEJ (ORCPT ); Wed, 14 Jun 2017 11:04:09 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60172; Wed, 14 Jun 2017 23:03:24 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:14 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 06/22] scsi: hisi_sas: relocate get_ncq_tag_v2_hw() Date: Wed, 14 Jun 2017 23:33:16 +0800 Message-ID: <1497454412-91194-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503D.0145, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: abb83c53368b9001589ed74f7cab0461 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Relocate get_ncq_tag_v2_hw() to a common location, as future hw versions will require it. Also rename with "hisi_sas_" prefix for consistency. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 1 + drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 16 +--------------- 3 files changed, 17 insertions(+), 15 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 1dcdf66..19c6ffd 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -366,6 +366,7 @@ struct hisi_sas_command_table_ssp { extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); extern void hisi_sas_sata_done(struct sas_task *task, struct hisi_sas_slot *slot); +extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag); extern int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *ops); extern int hisi_sas_remove(struct platform_device *pdev); diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index ab133d4..f53a93b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -97,6 +97,21 @@ void hisi_sas_sata_done(struct sas_task *task, } EXPORT_SYMBOL_GPL(hisi_sas_sata_done); +int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag) +{ + struct ata_queued_cmd *qc = task->uldd_task; + + if (qc) { + if (qc->tf.command == ATA_CMD_FPDMA_WRITE || + qc->tf.command == ATA_CMD_FPDMA_READ) { + *tag = qc->tag; + return 1; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag); + static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device) { return device->port->ha->lldd_ha; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index fdd7019..9cc5435 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -2332,20 +2332,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, return sts; } -static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) -{ - struct ata_queued_cmd *qc = task->uldd_task; - - if (qc) { - if (qc->tf.command == ATA_CMD_FPDMA_WRITE || - qc->tf.command == ATA_CMD_FPDMA_READ) { - *tag = qc->tag; - return 1; - } - } - return 0; -} - static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { @@ -2393,7 +2379,7 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, hdr->dw1 = cpu_to_le32(dw1); /* dw2 */ - if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) { + if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; } From patchwork Wed Jun 14 15:33:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105546 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp381220obh; Wed, 14 Jun 2017 08:13:35 -0700 (PDT) X-Received: by 10.84.129.97 with SMTP id 88mr629949plb.111.1497453215380; Wed, 14 Jun 2017 08:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453215; cv=none; d=google.com; s=arc-20160816; b=0zoE/ohu4HTh6AexrmvGOoIbaY0kn+JWLVcY5318mnWJty+N5+lrc3pGHuPas3UexN 99TUIcE6CWWzMWalIrmYzPFwMKST1X6zStjjqNboBpWrSMGZuzNErDyT52UOQxwAPq+5 lPmlo6HKfSsZQ5pRSUffTQycoD9Xj6n+HJI/XD9CCfhJM4Xkd5w+RFtG/8Weqxm8xbXs 49xCRNZ/7Ks7s57cSdW4HFkJ5mjo1TZp19IR4+gibvG7ZVhxKF3bnGfq5stCSBPdInuI R1EzgRZQl7RwIhoq9r1i+ZpYPnGLSYcf839R8+cUkAIcXRppsH/DA/Alhm4/sp0qTJ4I QZVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=R2imjnQhoRKQwlSVtJdV/rDOH3U0a6fpYaFsotAkaJE=; b=fVoAEprKIA8vkUIyHpe8TG1yWT62nlyEZtClqE7Sx4lHTy8Ulp+HwOydJgpjTzeZZo IJmxXaHM28e2cAOKXAQXrsJkQ5PzhfqOuuqgmN0EJPTP3COarbna/yIugV4Q4DkVRFgm oeLmwdrZpxJ+428mHef3s9G8BG96ImNO8dAMoarj+gvTgvchQuyofcDsN2z1RP/JTMcu KCotZZ2VzuIpQwXexpGFfpj93j4cOc1I4hQJf9Lrz8tjgDPRBjCE6uivpHS8cfBRUEx1 ct12kD9Zhi7YUHhoGBx7eudfKDZqQom1MKjsbG/FtTjTKwCFhbbgEY7S6W4fbhvudBEN m8MQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a6si172661pgc.392.2017.06.14.08.13.35; Wed, 14 Jun 2017 08:13:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752845AbdFNPND (ORCPT + 25 others); Wed, 14 Jun 2017 11:13:03 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7844 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752515AbdFNPEK (ORCPT ); Wed, 14 Jun 2017 11:04:10 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60179; Wed, 14 Jun 2017 23:03:24 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:14 +0800 From: John Garry To: , CC: , , , , , "John Garry" , Xiang Chen Subject: [PATCH v6 07/22] scsi: hisi_sas: add pci_dev in hisi_hba struct Date: Wed, 14 Jun 2017 23:33:17 +0800 Message-ID: <1497454412-91194-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503E.00C0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e81d3035be517284d11408d966636e35 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since hip08 SAS controller is based on pci device, add hisi_hba.pci_dev for hip08 (will be v3), and also rename hisi_hba.pdev to .platform_dev for clarity. In addition, for common code which wants to reference the controller device struct, add hisi_hba.dev, and change the common code to use it. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas.h | 6 ++++- drivers/scsi/hisi_sas/hisi_sas_main.c | 36 ++++++++++++++-------------- drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 28 +++++++++++----------- drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 44 +++++++++++++++++----------------- 4 files changed, 59 insertions(+), 55 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 19c6ffd..84cac98 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -196,7 +197,10 @@ struct hisi_hba { /* This must be the first element, used by SHOST_TO_SAS_HA */ struct sas_ha_struct *p; - struct platform_device *pdev; + struct platform_device *platform_dev; + struct pci_dev *pci_dev; + struct device *dev; + void __iomem *regs; struct regmap *ctrl; u32 ctrl_reset_reg; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index f53a93b..139df45 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -168,7 +168,7 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task, { if (task) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -245,7 +245,7 @@ static void hisi_sas_slot_abort(struct work_struct *work) struct scsi_cmnd *cmnd = task->uldd_task; struct hisi_sas_tmf_task tmf_task; struct scsi_lun lun; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int tag = abort_slot->idx; unsigned long flags; @@ -279,7 +279,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq struct hisi_sas_slot *slot; struct hisi_sas_cmd_hdr *cmd_hdr_base; struct asd_sas_port *sas_port = device->port; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx; unsigned long flags; @@ -451,7 +451,7 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags, u32 pass = 0; unsigned long flags; struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_sas_dq *dq = sas_dev->dq; @@ -546,7 +546,7 @@ static int hisi_sas_dev_found(struct domain_device *device) struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); struct domain_device *parent_dev = device->parent; struct hisi_sas_device *sas_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; if (hisi_hba->hw->alloc_dev) sas_dev = hisi_hba->hw->alloc_dev(device); @@ -731,7 +731,7 @@ static void hisi_sas_dev_gone(struct domain_device *device) { struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int dev_id = sas_dev->device_id; dev_info(dev, "found dev[%d:%x] is gone\n", @@ -814,7 +814,7 @@ static int hisi_sas_exec_internal_tmf_task(struct domain_device *device, { struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = sas_dev->hisi_hba; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct sas_task *task; int res, retry; @@ -931,7 +931,7 @@ static int hisi_sas_softreset_ata_disk(struct domain_device *device) struct ata_link *link; int rc = TMF_RESP_FUNC_FAILED; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int s = sizeof(struct host_to_dev_fis); unsigned long flags; @@ -989,7 +989,7 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) return -1; if (!test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct sas_ha_struct *sas_ha = &hisi_hba->sha; unsigned long flags; @@ -1022,7 +1022,7 @@ static int hisi_sas_abort_task(struct sas_task *task) struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int rc = TMF_RESP_FUNC_FAILED; unsigned long flags; @@ -1151,7 +1151,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun) { struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_hba *hisi_hba = dev_to_hisi_hba(device); - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; unsigned long flags; int rc = TMF_RESP_FUNC_FAILED; @@ -1240,7 +1240,7 @@ static int hisi_sas_query_task(struct sas_task *task) { struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_port *port; struct hisi_sas_slot *slot; struct asd_sas_port *sas_port = device->port; @@ -1337,7 +1337,7 @@ static int hisi_sas_query_task(struct sas_task *task) { struct sas_task *task; struct hisi_sas_device *sas_dev = device->lldd_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int res; if (!hisi_hba->hw->prep_abort) @@ -1547,8 +1547,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba) static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) { - struct platform_device *pdev = hisi_hba->pdev; - struct device *dev = &pdev->dev; + struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; spin_lock_init(&hisi_hba->lock); @@ -1668,7 +1667,7 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) static void hisi_sas_free(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; for (i = 0; i < hisi_hba->queue_count; i++) { @@ -1749,7 +1748,8 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); hisi_hba->hw = hw; - hisi_hba->pdev = pdev; + hisi_hba->platform_dev = pdev; + hisi_hba->dev = dev; hisi_hba->shost = shost; SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; @@ -1866,7 +1866,7 @@ int hisi_sas_probe(struct platform_device *pdev, shost->cmd_per_lun = hisi_hba->hw->max_command_entries; sha->sas_ha_name = DRV_NAME; - sha->dev = &hisi_hba->pdev->dev; + sha->dev = hisi_hba->dev; sha->lldd_module = THIS_MODULE; sha->sas_addr = &hisi_hba->sas_addr[0]; sha->num_phys = hisi_hba->n_phy; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c index 7d7d2a7..afa87d4 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c @@ -505,7 +505,7 @@ static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { struct domain_device *device = sas_dev->sas_device; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u64 qw0, device_id = sas_dev->device_id; struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; struct asd_sas_port *sas_port = device->port; @@ -571,7 +571,7 @@ static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) int i; unsigned long end_time; u32 val; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; for (i = 0; i < hisi_hba->n_phy; i++) { u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); @@ -756,7 +756,7 @@ static void init_reg_v1_hw(struct hisi_hba *hisi_hba) static int hw_init_v1_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int rc; rc = reset_hw_v1_hw(hisi_hba); @@ -907,7 +907,7 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int queue = dq->id; u32 r, w; @@ -939,7 +939,7 @@ static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, struct scatterlist *scatter, int n_elem) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct scatterlist *sg; int i; @@ -976,7 +976,7 @@ static int prep_smp_v1_hw(struct hisi_hba *hisi_hba, struct sas_task *task = slot->task; struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; struct domain_device *device = task->dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_port *port = slot->port; struct scatterlist *sg_req, *sg_resp; struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -1148,7 +1148,7 @@ static void slot_err_v1_hw(struct hisi_hba *hisi_hba, { struct task_status_struct *ts = &task->task_status; struct hisi_sas_err_record_v1 *err_record = slot->status_buffer; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; switch (task->task_proto) { case SAS_PROTOCOL_SSP: @@ -1274,7 +1274,7 @@ static int slot_complete_v1_hw(struct hisi_hba *hisi_hba, { struct sas_task *task = slot->task; struct hisi_sas_device *sas_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct task_status_struct *ts; struct domain_device *device; enum exec_status sts; @@ -1423,7 +1423,7 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) { struct hisi_sas_phy *phy = p; struct hisi_hba *hisi_hba = phy->hisi_hba; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct asd_sas_phy *sas_phy = &phy->sas_phy; int i, phy_no = sas_phy->id; u32 irq_value, context, port_id, link_rate; @@ -1504,7 +1504,7 @@ static irqreturn_t int_bcast_v1_hw(int irq, void *p) struct hisi_hba *hisi_hba = phy->hisi_hba; struct asd_sas_phy *sas_phy = &phy->sas_phy; struct sas_ha_struct *sha = &hisi_hba->sha; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int phy_no = sas_phy->id; u32 irq_value; irqreturn_t res = IRQ_HANDLED; @@ -1531,7 +1531,7 @@ static irqreturn_t int_abnormal_v1_hw(int irq, void *p) { struct hisi_sas_phy *phy = p; struct hisi_hba *hisi_hba = phy->hisi_hba; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct asd_sas_phy *sas_phy = &phy->sas_phy; u32 irq_value, irq_mask_old; int phy_no = sas_phy->id; @@ -1634,7 +1634,7 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) { struct hisi_hba *hisi_hba = p; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { @@ -1693,7 +1693,7 @@ static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) { struct hisi_hba *hisi_hba = p; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); @@ -1731,7 +1731,7 @@ static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) { - struct platform_device *pdev = hisi_hba->pdev; + struct platform_device *pdev = hisi_hba->platform_dev; struct device *dev = &pdev->dev; int i, j, irq, rc, idx; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 9cc5435..341a0bf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -653,7 +653,7 @@ static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx) { unsigned int index; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; void *bitmap = hisi_hba->sata_dev_bitmap; index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW); @@ -754,7 +754,7 @@ static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { struct domain_device *device = sas_dev->sas_device; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u64 qw0, device_id = sas_dev->device_id; struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; struct domain_device *parent_dev = device->parent; @@ -807,7 +807,7 @@ static void free_device_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { u64 dev_id = sas_dev->device_id; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); int i; @@ -851,7 +851,7 @@ static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) int i, reset_val; u32 val; unsigned long end_time; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; /* The mask needs to be set depending on the number of phys */ if (hisi_hba->n_phy == 9) @@ -987,7 +987,7 @@ static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba) static void init_reg_v2_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int i; /* Global registers init */ @@ -1168,7 +1168,7 @@ static void set_link_timer_quirk(struct hisi_hba *hisi_hba) static int hw_init_v2_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int rc; rc = reset_hw_v2_hw(hisi_hba); @@ -1217,7 +1217,7 @@ static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no) static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { int i, max_loop = 1000; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 status, axi_status, dfx_val, dfx_tx_val; for (i = 0; i < max_loop; i++) { @@ -1243,7 +1243,7 @@ static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no) static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { int i, max_loop = 1000; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 status, tx_dfx0; for (i = 0; i < max_loop; i++) { @@ -1281,7 +1281,7 @@ static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { u32 cfg, axi_val, dfx0_val, txid_auto; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; /* Close axi bus. */ axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + @@ -1459,7 +1459,7 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; int queue = dq->id; u32 r, w; @@ -1492,7 +1492,7 @@ static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, struct scatterlist *scatter, int n_elem) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct scatterlist *sg; int i; @@ -1529,7 +1529,7 @@ static int prep_smp_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task = slot->task; struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; struct domain_device *device = task->dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_port *port = slot->port; struct scatterlist *sg_req, *sg_resp; struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -2188,7 +2188,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, { struct sas_task *task = slot->task; struct hisi_sas_device *sas_dev; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct task_status_struct *ts; struct domain_device *device; enum exec_status sts; @@ -2486,7 +2486,7 @@ static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) u32 port_id, link_rate, hard_phy_linkrate; struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; struct asd_sas_phy *sas_phy = &phy->sas_phy; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; @@ -2673,7 +2673,7 @@ static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) { struct hisi_hba *hisi_hba = p; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 ent_msk, ent_tmp, irq_msk; int phy_no = 0; @@ -2733,7 +2733,7 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) static void one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 reg_val; if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) { @@ -2822,7 +2822,7 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) { u32 reg_val; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) { reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR); @@ -2972,7 +2972,7 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) { struct hisi_hba *hisi_hba = p; u32 irq_value, irq_msk, err_value; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); @@ -3148,7 +3148,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p) struct hisi_sas_phy *phy = p; struct hisi_hba *hisi_hba = phy->hisi_hba; struct asd_sas_phy *sas_phy = &phy->sas_phy; - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; struct hisi_sas_initial_fis *initial_fis; struct dev_to_host_fis *fis; u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; @@ -3250,7 +3250,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p) */ static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) { - struct platform_device *pdev = hisi_hba->pdev; + struct platform_device *pdev = hisi_hba->platform_dev; struct device *dev = &pdev->dev; int i, irq, rc, irq_map[128]; @@ -3364,7 +3364,7 @@ static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba) { - struct platform_device *pdev = hisi_hba->pdev; + struct platform_device *pdev = hisi_hba->platform_dev; int i; for (i = 0; i < hisi_hba->queue_count; i++) @@ -3386,7 +3386,7 @@ static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba) static int soft_reset_v2_hw(struct hisi_hba *hisi_hba) { - struct device *dev = &hisi_hba->pdev->dev; + struct device *dev = hisi_hba->dev; u32 old_state, state; int rc, cnt; int phy_no; From patchwork Wed Jun 14 15:33:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105531 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp338142qgd; Wed, 14 Jun 2017 08:04:38 -0700 (PDT) X-Received: by 10.98.59.92 with SMTP id i89mr529480pfa.122.1497452677939; Wed, 14 Jun 2017 08:04:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452677; cv=none; d=google.com; s=arc-20160816; b=jmyvVREPeRn/i+B0+i/2WPGLsvOeM832ctmKdMDauWFCkSNhzO8Fd1pW4hfMvThQdz XHWuaKOvrrItxYSR7gaGRT7YgFurJ/G4PwMOWAh4MfwxfdiWxPdtpscKr/hPBnp89pwF stHqotHzWEBTZ07gZhi3ZUwc5FtJZl/qYRIg+d6pS12Y9Azm7wdnW14qsrXRXvW3Cjvt 7Mc8IlGBqQCvRHcUOdYZ5f2qQBJzf+YrE/vw+MUZ1gxrsGsOA8YDcORdrcbst11l1SNk +DDI6bpgPmGmCfk6X5my3xBq3GBdBrBSnH9Z8aFJImWoEdpJdX5rSFfpPVUQwlvmS7xY qNxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=UVtS07djwRGFOJCnBbIhVVaQkHpqS3tQJwpoHetTftY=; b=0W9+Pac0KiK9QS/dhsLhKdWhq05fPC12EMgZd2cBmfju/0+0xx+GyU++/6+j1+BbyZ OTxhpbIo4zlsGsb/u6RV3U2Mvte00p+WJjT0i3HseW75ilhFVUqcQ7SXM12YbntYXDOZ sSqF8nYyz6U6QscSHybWej6JXdzNrQUspsbJCJJB2ZZ/ZkAxv5tk4NiDoVJFf73VsNZA UY6zWzVqHlCqie+Xilay148CxGEnUXqAjI923r5SUhjkWx2M2yCyY3vtRdusxMqQpB5C Y5NgLY2ITG+bDD9fOlzx+n+X9mLM6grvse6dt8YJVcwxe/2FTNA9oxCM3C8Azg4kgtfy vztQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d80si160754pfk.223.2017.06.14.08.04.37; Wed, 14 Jun 2017 08:04:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752672AbdFNPE0 (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:26 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7838 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752555AbdFNPEX (ORCPT ); Wed, 14 Jun 2017 11:04:23 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60186; Wed, 14 Jun 2017 23:03:26 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:15 +0800 From: John Garry To: , CC: , , , , , "John Garry" , Xiang Chen Subject: [PATCH v6 10/22] scsi: hisi_sas: add initialisation for v3 pci-based controller Date: Wed, 14 Jun 2017 23:33:20 +0800 Message-ID: <1497454412-91194-11-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503F.004C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8b8329fc58ff6a3aa98f34aa63ce1c17 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the code to initialise the controller which is based on pci device in hisi_sas_v3_hw.c The core controller routines are still in hisi_sas_main.c; some common initialisation functions are also exported from hisi_sas_main.c For pci-based controller, the device properties, like phy count and sas address are read from the firmware, same as platform device-based controller. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas.h | 6 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 18 ++-- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 154 +++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+), 6 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index c1f6669..e89f6ae 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -366,6 +366,12 @@ struct hisi_sas_command_table_ssp { struct hisi_sas_command_table_stp stp; }; +extern struct scsi_transport_template *hisi_sas_stt; +extern struct scsi_host_template *hisi_sas_sht; + +extern void hisi_sas_init_add(struct hisi_hba *hisi_hba); +extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost); +extern void hisi_sas_free(struct hisi_hba *hisi_hba); extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction); extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); extern void hisi_sas_sata_done(struct sas_task *task, diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 81c053c..0a32211 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1476,9 +1476,10 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state, } EXPORT_SYMBOL_GPL(hisi_sas_rescan_topology); -static struct scsi_transport_template *hisi_sas_stt; +struct scsi_transport_template *hisi_sas_stt; +EXPORT_SYMBOL_GPL(hisi_sas_stt); -static struct scsi_host_template hisi_sas_sht = { +static struct scsi_host_template _hisi_sas_sht = { .module = THIS_MODULE, .name = DRV_NAME, .queuecommand = sas_queuecommand, @@ -1498,6 +1499,8 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state, .target_destroy = sas_target_destroy, .ioctl = sas_ioctl, }; +struct scsi_host_template *hisi_sas_sht = &_hisi_sas_sht; +EXPORT_SYMBOL_GPL(hisi_sas_sht); static struct sas_domain_function_template hisi_sas_transport_ops = { .lldd_dev_found = hisi_sas_dev_found, @@ -1545,7 +1548,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba) } EXPORT_SYMBOL_GPL(hisi_sas_init_mem); -static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) +int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) { struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; @@ -1664,8 +1667,9 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) err_out: return -ENOMEM; } +EXPORT_SYMBOL_GPL(hisi_sas_alloc); -static void hisi_sas_free(struct hisi_hba *hisi_hba) +void hisi_sas_free(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; int i, s, max_command_entries = hisi_hba->hw->max_command_entries; @@ -1720,6 +1724,7 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba) if (hisi_hba->wq) destroy_workqueue(hisi_hba->wq); } +EXPORT_SYMBOL_GPL(hisi_sas_free); static void hisi_sas_rst_work_handler(struct work_struct *work) { @@ -1805,7 +1810,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, struct hisi_hba *hisi_hba; struct device *dev = &pdev->dev; - shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba)); + shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba)); if (!shost) { dev_err(dev, "scsi host alloc failed\n"); return NULL; @@ -1847,7 +1852,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev, return NULL; } -static void hisi_sas_init_add(struct hisi_hba *hisi_hba) +void hisi_sas_init_add(struct hisi_hba *hisi_hba) { int i; @@ -1856,6 +1861,7 @@ static void hisi_sas_init_add(struct hisi_hba *hisi_hba) hisi_hba->sas_addr, SAS_ADDR_SIZE); } +EXPORT_SYMBOL_GPL(hisi_sas_init_add); int hisi_sas_probe(struct platform_device *pdev, const struct hisi_sas_hw *hw) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index cf72577..e9a9fb0 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -11,14 +11,168 @@ #include "hisi_sas.h" #define DRV_NAME "hisi_sas_v3_hw" +static const struct hisi_sas_hw hisi_sas_v3_hw = { +}; + +static struct Scsi_Host * +hisi_sas_shost_alloc_pci(struct pci_dev *pdev) +{ + struct Scsi_Host *shost; + struct hisi_hba *hisi_hba; + struct device *dev = &pdev->dev; + + shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba)); + if (!shost) + goto err_out; + hisi_hba = shost_priv(shost); + + hisi_hba->hw = &hisi_sas_v3_hw; + hisi_hba->pci_dev = pdev; + hisi_hba->dev = dev; + hisi_hba->shost = shost; + SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; + + init_timer(&hisi_hba->timer); + + if (hisi_sas_get_fw_info(hisi_hba) < 0) + goto err_out; + + if (hisi_sas_alloc(hisi_hba, shost)) { + hisi_sas_free(hisi_hba); + goto err_out; + } + + return shost; +err_out: + dev_err(dev, "shost alloc failed\n"); + return NULL; +} + static int hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) { + struct Scsi_Host *shost; + struct hisi_hba *hisi_hba; + struct device *dev = &pdev->dev; + struct asd_sas_phy **arr_phy; + struct asd_sas_port **arr_port; + struct sas_ha_struct *sha; + int rc, phy_nr, port_nr, i; + + rc = pci_enable_device(pdev); + if (rc) + goto err_out; + + pci_set_master(pdev); + + rc = pci_request_regions(pdev, DRV_NAME); + if (rc) + goto err_out_disable_device; + + if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || + (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { + if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || + (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { + dev_err(dev, "No usable DMA addressing method\n"); + rc = -EIO; + goto err_out_regions; + } + } + + shost = hisi_sas_shost_alloc_pci(pdev); + if (!shost) { + rc = -ENOMEM; + goto err_out_regions; + } + + sha = SHOST_TO_SAS_HA(shost); + hisi_hba = shost_priv(shost); + dev_set_drvdata(dev, sha); + + hisi_hba->regs = pcim_iomap(pdev, 5, 0); + if (!hisi_hba->regs) { + dev_err(dev, "cannot map register.\n"); + rc = -ENOMEM; + goto err_out_ha; + } + + phy_nr = port_nr = hisi_hba->n_phy; + + arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); + arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); + if (!arr_phy || !arr_port) { + rc = -ENOMEM; + goto err_out_ha; + } + + sha->sas_phy = arr_phy; + sha->sas_port = arr_port; + sha->core.shost = shost; + sha->lldd_ha = hisi_hba; + + shost->transportt = hisi_sas_stt; + shost->max_id = HISI_SAS_MAX_DEVICES; + shost->max_lun = ~0; + shost->max_channel = 1; + shost->max_cmd_len = 16; + shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); + shost->can_queue = hisi_hba->hw->max_command_entries; + shost->cmd_per_lun = hisi_hba->hw->max_command_entries; + + sha->sas_ha_name = DRV_NAME; + sha->dev = dev; + sha->lldd_module = THIS_MODULE; + sha->sas_addr = &hisi_hba->sas_addr[0]; + sha->num_phys = hisi_hba->n_phy; + sha->core.shost = hisi_hba->shost; + + for (i = 0; i < hisi_hba->n_phy; i++) { + sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; + sha->sas_port[i] = &hisi_hba->port[i].sas_port; + } + + hisi_sas_init_add(hisi_hba); + + rc = scsi_add_host(shost, dev); + if (rc) + goto err_out_ha; + + rc = sas_register_ha(sha); + if (rc) + goto err_out_register_ha; + + rc = hisi_hba->hw->hw_init(hisi_hba); + if (rc) + goto err_out_register_ha; + + scsi_scan_host(shost); + return 0; + +err_out_register_ha: + scsi_remove_host(shost); +err_out_ha: + kfree(shost); +err_out_regions: + pci_release_regions(pdev); +err_out_disable_device: + pci_disable_device(pdev); +err_out: + return rc; } static void hisi_sas_v3_remove(struct pci_dev *pdev) { + struct device *dev = &pdev->dev; + struct sas_ha_struct *sha = dev_get_drvdata(dev); + struct hisi_hba *hisi_hba = sha->lldd_ha; + + sas_unregister_ha(sha); + sas_remove_host(sha->core.shost); + + hisi_sas_free(hisi_hba); + pci_release_regions(pdev); + pci_disable_device(pdev); } enum { From patchwork Wed Jun 14 15:33:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105535 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp338895qgd; Wed, 14 Jun 2017 08:05:54 -0700 (PDT) X-Received: by 10.84.140.133 with SMTP id 5mr614778plt.224.1497452754627; Wed, 14 Jun 2017 08:05:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452754; cv=none; d=google.com; s=arc-20160816; b=CR+6qw61A8lkFczgtRAPvg7ZYut24EFxw7dDYD3r/1OoGevYKOgEh5rmN+62d9S7Pi BN6SwtSb2QKn3x5qk9JSbIHTEJ+6IP8hLkeb1Njd/9+atKaZIVULQelOvQPM9p1n24uI PpZwmG73d2s+l+CxGYQCYJGnPX7VdRHnH8RSYxym+RtW3UpDn5a1RpMPIeA5FMV2RLXS cCa+JfumDcFBF+Y/A4zUQ87J9X3SSVz2ynHD2PPeWDAE4AFFp1RTkOELK+NwKOvH1van UF9HEOo1p/RIQGt3ZAfqg2MYwPRjx08kh0q6A7wwbkTpeY6wx2EuDdPAvjgTYmJOq3Ct RWbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=SwWChT0166M5r8FoxB1vt00O9sOPrDqhwaIiUD0IDHE=; b=f8DYO7WI2qtAwvhwXZVfpV6jE8FDgFVoMYw4sCmIUBsuYKAtdPB2Q9FEC6JOmPWf+Q 76iSEE2G0guezcVM33ux5CUaDVuOjjtBg218t1iHd8XLwJx4z18Er9ufgNf40Acz/vF8 xwhg6/4sRYL8tHLqELgNBOlr1/c1rKhQwvbFSHxHBRPR6pwdmJRVuBeN0YM7uy9txak9 Kbn4O7IfGEPpoGSdGnww66jteE2Ph1+Pdyq3gS0Wnj0jVxHtc7vWjZdi02L2dmubP2JF 4Z+Ichc9mR09ozjcd6GLsOjCwKtw3NWlfbv34oFDuJ7rJ8gcYJNf8Op4wIJB6dpDTmDP c6MQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x127si160312pfx.257.2017.06.14.08.05.54; Wed, 14 Jun 2017 08:05:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752767AbdFNPFq (ORCPT + 25 others); Wed, 14 Jun 2017 11:05:46 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7852 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752594AbdFNPER (ORCPT ); Wed, 14 Jun 2017 11:04:17 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60180; Wed, 14 Jun 2017 23:03:25 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:15 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 11/22] scsi: hisi_sas: add v3 hw init Date: Wed, 14 Jun 2017 23:33:21 +0800 Message-ID: <1497454412-91194-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5941503D.01E4, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d9a997cdf63c2b9a41050c52184c359d Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to initialise v3 hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 277 +++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index e9a9fb0..1a5eae6 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -11,7 +11,283 @@ #include "hisi_sas.h" #define DRV_NAME "hisi_sas_v3_hw" +/* global registers need init*/ +#define DLVRY_QUEUE_ENABLE 0x0 +#define IOST_BASE_ADDR_LO 0x8 +#define IOST_BASE_ADDR_HI 0xc +#define ITCT_BASE_ADDR_LO 0x10 +#define ITCT_BASE_ADDR_HI 0x14 +#define IO_BROKEN_MSG_ADDR_LO 0x18 +#define IO_BROKEN_MSG_ADDR_HI 0x1c +#define AXI_AHB_CLK_CFG 0x3c +#define AXI_USER1 0x48 +#define AXI_USER2 0x4c +#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 +#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c +#define SATA_INITI_D2H_STORE_ADDR_LO 0x60 +#define SATA_INITI_D2H_STORE_ADDR_HI 0x64 +#define CFG_MAX_TAG 0x68 +#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 +#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 +#define HGC_GET_ITV_TIME 0x90 +#define DEVICE_MSG_WORK_MODE 0x94 +#define OPENA_WT_CONTI_TIME 0x9c +#define I_T_NEXUS_LOSS_TIME 0xa0 +#define MAX_CON_TIME_LIMIT_TIME 0xa4 +#define BUS_INACTIVE_LIMIT_TIME 0xa8 +#define REJECT_TO_OPEN_LIMIT_TIME 0xac +#define CFG_AGING_TIME 0xbc +#define HGC_DFX_CFG2 0xc0 +#define CFG_ABT_SET_QUERY_IPTT 0xd4 +#define CFG_SET_ABORTED_IPTT_OFF 0 +#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) +#define CFG_1US_TIMER_TRSH 0xcc +#define INT_COAL_EN 0x19c +#define OQ_INT_COAL_TIME 0x1a0 +#define OQ_INT_COAL_CNT 0x1a4 +#define ENT_INT_COAL_TIME 0x1a8 +#define ENT_INT_COAL_CNT 0x1ac +#define OQ_INT_SRC 0x1b0 +#define OQ_INT_SRC_MSK 0x1b4 +#define ENT_INT_SRC1 0x1b8 +#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 +#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) +#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 +#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) +#define ENT_INT_SRC2 0x1bc +#define ENT_INT_SRC3 0x1c0 +#define ENT_INT_SRC3_WP_DEPTH_OFF 8 +#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 +#define ENT_INT_SRC3_RP_DEPTH_OFF 10 +#define ENT_INT_SRC3_AXI_OFF 11 +#define ENT_INT_SRC3_FIFO_OFF 12 +#define ENT_INT_SRC3_LM_OFF 14 +#define ENT_INT_SRC3_ITC_INT_OFF 15 +#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) +#define ENT_INT_SRC3_ABT_OFF 16 +#define ENT_INT_SRC_MSK1 0x1c4 +#define ENT_INT_SRC_MSK2 0x1c8 +#define ENT_INT_SRC_MSK3 0x1cc +#define CHNL_PHYUPDOWN_INT_MSK 0x1d0 +#define CHNL_ENT_INT_MSK 0x1d4 +#define HGC_COM_INT_MSK 0x1d8 +#define SAS_ECC_INTR 0x1e8 +#define SAS_ECC_INTR_MSK 0x1ec +#define HGC_ERR_STAT_EN 0x238 +#define DLVRY_Q_0_BASE_ADDR_LO 0x260 +#define DLVRY_Q_0_BASE_ADDR_HI 0x264 +#define DLVRY_Q_0_DEPTH 0x268 +#define DLVRY_Q_0_WR_PTR 0x26c +#define DLVRY_Q_0_RD_PTR 0x270 +#define HYPER_STREAM_ID_EN_CFG 0xc80 +#define OQ0_INT_SRC_MSK 0xc90 +#define COMPL_Q_0_BASE_ADDR_LO 0x4e0 +#define COMPL_Q_0_BASE_ADDR_HI 0x4e4 +#define COMPL_Q_0_DEPTH 0x4e8 +#define COMPL_Q_0_WR_PTR 0x4ec +#define COMPL_Q_0_RD_PTR 0x4f0 +#define AWQOS_AWCACHE_CFG 0xc84 +#define ARQOS_ARCACHE_CFG 0xc88 + +/* phy registers requiring init */ +#define PORT_BASE (0x2000) +#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) +#define PHY_CTRL (PORT_BASE + 0x14) +#define PHY_CTRL_RESET_OFF 0 +#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) +#define SL_CFG (PORT_BASE + 0x84) +#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) +#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) +#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) +#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) +#define CHL_INT0 (PORT_BASE + 0x1b4) +#define CHL_INT0_HOTPLUG_TOUT_OFF 0 +#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) +#define CHL_INT0_SL_RX_BCST_ACK_OFF 1 +#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) +#define CHL_INT0_SL_PHY_ENABLE_OFF 2 +#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) +#define CHL_INT0_NOT_RDY_OFF 4 +#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) +#define CHL_INT0_PHY_RDY_OFF 5 +#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) +#define CHL_INT1 (PORT_BASE + 0x1b8) +#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 +#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) +#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 +#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) +#define CHL_INT2 (PORT_BASE + 0x1bc) +#define CHL_INT0_MSK (PORT_BASE + 0x1c0) +#define CHL_INT1_MSK (PORT_BASE + 0x1c4) +#define CHL_INT2_MSK (PORT_BASE + 0x1c8) +#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) +#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) +#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) +#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) +#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) +#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) +#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) + +struct hisi_sas_complete_v3_hdr { + __le32 dw0; + __le32 dw1; + __le32 act; + __le32 dw3; +}; + +#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 + +static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) +{ + void __iomem *regs = hisi_hba->regs + off; + + writel(val, regs); +} + +static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, + u32 off, u32 val) +{ + void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; + + writel(val, regs); +} + +static void init_reg_v3_hw(struct hisi_hba *hisi_hba) +{ + int i; + + /* Global registers init */ + hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, + (u32)((1ULL << hisi_hba->queue_count) - 1)); + hisi_sas_write32(hisi_hba, AXI_USER1, 0x0); + hisi_sas_write32(hisi_hba, AXI_USER2, 0x40000060); + hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); + hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd); + hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); + hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); + hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); + hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); + hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); + hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); + hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); + hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30); + hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); + hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); + for (i = 0; i < hisi_hba->queue_count; i++) + hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); + + hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); + hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); + hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff07fff); + + for (i = 0; i < hisi_hba->n_phy; i++) { + hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801); + hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); + hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); + hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); + hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); + hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); + hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff); + hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x83f801fc); + hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); + hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); + hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); + hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); + hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); + hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); + hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa); + hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, + 0xa0064); + hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG, + 0xa0064); + } + for (i = 0; i < hisi_hba->queue_count; i++) { + /* Delivery queue */ + hisi_sas_write32(hisi_hba, + DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), + upper_32_bits(hisi_hba->cmd_hdr_dma[i])); + + hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), + lower_32_bits(hisi_hba->cmd_hdr_dma[i])); + + hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), + HISI_SAS_QUEUE_SLOTS); + + /* Completion queue */ + hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), + upper_32_bits(hisi_hba->complete_hdr_dma[i])); + + hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), + lower_32_bits(hisi_hba->complete_hdr_dma[i])); + + hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), + HISI_SAS_QUEUE_SLOTS); + } + + /* itct */ + hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, + lower_32_bits(hisi_hba->itct_dma)); + + hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, + upper_32_bits(hisi_hba->itct_dma)); + + /* iost */ + hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, + lower_32_bits(hisi_hba->iost_dma)); + + hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, + upper_32_bits(hisi_hba->iost_dma)); + + /* breakpoint */ + hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, + lower_32_bits(hisi_hba->breakpoint_dma)); + + hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, + upper_32_bits(hisi_hba->breakpoint_dma)); + + /* SATA broken msg */ + hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, + lower_32_bits(hisi_hba->sata_breakpoint_dma)); + + hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, + upper_32_bits(hisi_hba->sata_breakpoint_dma)); + + /* SATA initial fis */ + hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, + lower_32_bits(hisi_hba->initial_fis_dma)); + + hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, + upper_32_bits(hisi_hba->initial_fis_dma)); +} + +static int hw_init_v3_hw(struct hisi_hba *hisi_hba) +{ + init_reg_v3_hw(hisi_hba); + + return 0; +} + +static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) +{ + int rc; + + rc = hw_init_v3_hw(hisi_hba); + if (rc) + return rc; + + return 0; +} + static const struct hisi_sas_hw hisi_sas_v3_hw = { + .hw_init = hisi_sas_v3_init, + .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, + .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), }; static struct Scsi_Host * @@ -175,6 +451,7 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) pci_disable_device(pdev); } + enum { /* instances of the controller */ hip08, From patchwork Wed Jun 14 15:33:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105540 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp380285obh; Wed, 14 Jun 2017 08:11:35 -0700 (PDT) X-Received: by 10.101.87.206 with SMTP id q14mr518255pgr.153.1497453095510; Wed, 14 Jun 2017 08:11:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453095; cv=none; d=google.com; s=arc-20160816; b=nPX6+OQPIXCK7aheyMrduJPNDmSe9B9QrWWArjWhY7WlQDtVqSWWyzEgwL6EzIaX93 Yn+Rs5YhfGC3O5NlkuFhhlcsubVMFRFwYwJPSzmSzM4Koyww1PTKvgIvbltILBW/ekAj xMUrYDOZNe34d8zqf9yX1ejpnHuXekFKiy9hxecEqEi29GiSA7a1xr1RT4A/tOqtYZYR LyMiuEN6B7bGLUsaqyVCJ4IUPoAGnp8Wd5W5wneBa98xspeTMWiHJBFAVKAu2WBbW6Zn PqHc+lV/THGotCewqPpEhsq2e3RKGczPcF7GjOUT8uSRp9CFT9z1PJt9qW8FmpJF88da 5mhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=LoLFaaBLby+MF/GbzEU7+WPSotrKx8bRGAkjrKGk/wU=; b=yH/4hEVagfyutgD8eLtSJoN6HWqMHq83aIcMoquSBpOyFU2McY/VyAmT0G6tyVsOhD tHleR908wJ6tb8OTVJDtX2KvaLjtK50iCFRKQxue3ZTpXvTWUqVAXdARFstLgl05nMYM k8TiRAEdspIKP0ZM1eH82H4Dheq6yJXwCoyLr552lmMtb3V0IL8uXJ2+vbSVZ828WRfb xh5Mvsh1MdB3sjpCuA3G/lxenXbWRybdpxMEzAJkw3PzYq8bfbU3LQWgFdvjl9F+lal4 iuQRlNZSst1DjJcnFZG1gUhaw43QDKFtoXC0n2toGDXRNv4wvY7s7p+lIcXt10y42IiZ wxcQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a1si204377pln.417.2017.06.14.08.11.34; Wed, 14 Jun 2017 08:11:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752572AbdFNPEO (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:14 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7841 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752310AbdFNPEJ (ORCPT ); Wed, 14 Jun 2017 11:04:09 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60183; Wed, 14 Jun 2017 23:03:25 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:16 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 12/22] scsi: hisi_sas: add v3 hw PHY init Date: Wed, 14 Jun 2017 23:33:22 +0800 Message-ID: <1497454412-91194-13-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5941503E.00BE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d62b9bf31688e3dff7aecf5a74c63d34 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to configure PHYs for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 127 ++++++++++++++++++++++++++++++++- 1 file changed, 126 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 1a5eae6..5580250 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -19,6 +19,10 @@ #define ITCT_BASE_ADDR_HI 0x14 #define IO_BROKEN_MSG_ADDR_LO 0x18 #define IO_BROKEN_MSG_ADDR_HI 0x1c +#define PHY_CONTEXT 0x20 +#define PHY_STATE 0x24 +#define PHY_PORT_NUM_MA 0x28 +#define PHY_CONN_RATE 0x30 #define AXI_AHB_CLK_CFG 0x3c #define AXI_USER1 0x48 #define AXI_USER2 0x4c @@ -42,6 +46,7 @@ #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) #define CFG_1US_TIMER_TRSH 0xcc +#define CHNL_INT_STATUS 0x148 #define INT_COAL_EN 0x19c #define OQ_INT_COAL_TIME 0x1a0 #define OQ_INT_COAL_CNT 0x1a4 @@ -68,9 +73,11 @@ #define ENT_INT_SRC_MSK1 0x1c4 #define ENT_INT_SRC_MSK2 0x1c8 #define ENT_INT_SRC_MSK3 0x1cc +#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 #define CHNL_ENT_INT_MSK 0x1d4 #define HGC_COM_INT_MSK 0x1d8 +#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) #define SAS_ECC_INTR 0x1e8 #define SAS_ECC_INTR_MSK 0x1ec #define HGC_ERR_STAT_EN 0x238 @@ -91,11 +98,33 @@ /* phy registers requiring init */ #define PORT_BASE (0x2000) +#define PHY_CFG (PORT_BASE + 0x0) +#define HARD_PHY_LINKRATE (PORT_BASE + 0x4) +#define PHY_CFG_ENA_OFF 0 +#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) +#define PHY_CFG_DC_OPT_OFF 2 +#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) #define PHY_CTRL (PORT_BASE + 0x14) #define PHY_CTRL_RESET_OFF 0 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) #define SL_CFG (PORT_BASE + 0x84) +#define SL_CONTROL (PORT_BASE + 0x94) +#define SL_CONTROL_NOTIFY_EN_OFF 0 +#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) +#define SL_CTA_OFF 17 +#define SL_CTA_MSK (0x1 << SL_CTA_OFF) +#define TX_ID_DWORD0 (PORT_BASE + 0x9c) +#define TX_ID_DWORD1 (PORT_BASE + 0xa0) +#define TX_ID_DWORD2 (PORT_BASE + 0xa4) +#define TX_ID_DWORD3 (PORT_BASE + 0xa8) +#define TX_ID_DWORD4 (PORT_BASE + 0xaC) +#define TX_ID_DWORD5 (PORT_BASE + 0xb0) +#define TX_ID_DWORD6 (PORT_BASE + 0xb4) +#define TXID_AUTO (PORT_BASE + 0xb8) +#define CT3_OFF 1 +#define CT3_MSK (0x1 << CT3_OFF) +#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) @@ -136,6 +165,13 @@ struct hisi_sas_complete_v3_hdr { }; #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 +#define HISI_SAS_MSI_COUNT_V3_HW 32 + +enum { + HISI_SAS_PHY_PHY_UPDOWN, + HISI_SAS_PHY_CHNL_INT, + HISI_SAS_PHY_INT_NR +}; static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { @@ -152,6 +188,14 @@ static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, writel(val, regs); } +static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, + int phy_no, u32 off) +{ + void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; + + return readl(regs); +} + static void init_reg_v3_hw(struct hisi_hba *hisi_hba) { int i; @@ -266,6 +310,45 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) upper_32_bits(hisi_hba->initial_fis_dma)); } +static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg &= ~PHY_CFG_DC_OPT_MSK; + cfg |= 1 << PHY_CFG_DC_OPT_OFF; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + +static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct sas_identify_frame identify_frame; + u32 *identify_buffer; + + memset(&identify_frame, 0, sizeof(identify_frame)); + identify_frame.dev_type = SAS_END_DEVICE; + identify_frame.frame_type = 0; + identify_frame._un1 = 1; + identify_frame.initiator_bits = SAS_PROTOCOL_ALL; + identify_frame.target_bits = SAS_PROTOCOL_NONE; + memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); + memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); + identify_frame.phy_id = phy_no; + identify_buffer = (u32 *)(&identify_frame); + + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, + __swab32(identify_buffer[0])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, + __swab32(identify_buffer[1])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, + __swab32(identify_buffer[2])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, + __swab32(identify_buffer[3])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, + __swab32(identify_buffer[4])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, + __swab32(identify_buffer[5])); +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -273,6 +356,47 @@ static int hw_init_v3_hw(struct hisi_hba *hisi_hba) return 0; } +static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg |= PHY_CFG_ENA_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + +static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + config_id_frame_v3_hw(hisi_hba, phy_no); + config_phy_opt_mode_v3_hw(hisi_hba, phy_no); + enable_phy_v3_hw(hisi_hba, phy_no); +} + +static void start_phys_v3_hw(struct hisi_hba *hisi_hba) +{ + int i; + + for (i = 0; i < hisi_hba->n_phy; i++) + start_phy_v3_hw(hisi_hba, i); +} + +static void phys_init_v3_hw(struct hisi_hba *hisi_hba) +{ + start_phys_v3_hw(hisi_hba); +} + +static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 sl_control; + + sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + sl_control |= SL_CONTROL_NOTIFY_EN_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); + msleep(1); + sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); +} + static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) { int rc; @@ -288,6 +412,8 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .hw_init = hisi_sas_v3_init, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .sl_notify = sl_notify_v3_hw, + .phys_init = phys_init_v3_hw, }; static struct Scsi_Host * @@ -451,7 +577,6 @@ static void hisi_sas_v3_remove(struct pci_dev *pdev) pci_disable_device(pdev); } - enum { /* instances of the controller */ hip08, From patchwork Wed Jun 14 15:33:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105561 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp386457obh; Wed, 14 Jun 2017 08:26:33 -0700 (PDT) X-Received: by 10.84.232.199 with SMTP id x7mr672160plm.193.1497453993670; Wed, 14 Jun 2017 08:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453993; cv=none; d=google.com; s=arc-20160816; b=oOeHt3+WqAJyVyMkfJz9/+QjyBJSozbvU7KsMVLxTLBBvgaX+V5ZJCmIhlh3WSi5jz Q1ViBaQ+MCN21LcT/9WYCrajre+3KD6VreC3QcQ5AKf0kkouufrm5nae9BQkUHTIjmKN /PP45KuWlp9uPvGfTyQN4bW/vtYwhaHCriEhtwQFesrKaaL8zImh+5QMZTsg92ljm7DJ 5cmI8KXiEgq+fi2jCrael6XhEycXxMyXx2PsOPuuK52aQMRCmGK14mksrOcv/NIFMjPM IU6lPfX7ryLVZ5OrTLw9Q7nOuEjywPpf8jTZAA4U8VoMWAMFFTiVCBrP8FlxjVU2Tm7s 4XzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=q9JmgtudKvSpR43ugEZ69v7VBA5FMOk1PNioRfdn3Ls=; b=mbGsOlY6DKonKDzESPgygTJz8tqQV6FbDWR0N3LcHGX6TZkqCLtxIYreOJVzAuyHAN 2w4ejuKrKOnabmHRpM0AvkSmbsPDtoYpbJM6BnPf6PQwf5TVEwevJ6fyZcfXBR+37mCD ++CUFdhfNy13O+yQYyUbeA0yqWdEYoVwQRbCL3+PPWok151n8cGF35WgTYoyRh35x9Ds b2KBj2NhUQYCNpHZBzl2cDzr8XPwy6g3uiq/1UMXnpeL6IuPq30Z98ynmPIO+e5ZT7+o 7WjryQsKnjvD4FXgeesglrWgbNG8uWMWvEqnKDsmakYZ2+kVBNISOdEekk+MCSOWjaWE cEvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e7si231890plj.303.2017.06.14.08.26.33; Wed, 14 Jun 2017 08:26:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752677AbdFNP0V (ORCPT + 25 others); Wed, 14 Jun 2017 11:26:21 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7833 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751920AbdFNPEB (ORCPT ); Wed, 14 Jun 2017 11:04:01 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60200; Wed, 14 Jun 2017 23:03:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:16 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 14/22] scsi: hisi_sas: add v3 cq interrupt handler Date: Wed, 14 Jun 2017 23:33:24 +0800 Message-ID: <1497454412-91194-15-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59415041.0270, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ed52963d909a83f180d1f1b30ba309bd Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add v3 cq interrupt handler slot_complete_v3_hw(). Note: The slot error handling needs to be further refined in the future to examine all fields in the error record, and handle appropriately, instead of current solution - just report SAS_OPEN_REJECT. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 340 +++++++++++++++++++++++++++++++++ 1 file changed, 340 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 3065252..4869b73 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -157,6 +157,32 @@ #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) +/* Completion header */ +/* dw0 */ +#define CMPLT_HDR_CMPLT_OFF 0 +#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) +#define CMPLT_HDR_ERROR_PHASE_OFF 2 +#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) +#define CMPLT_HDR_RSPNS_XFRD_OFF 10 +#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) +#define CMPLT_HDR_ERX_OFF 12 +#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) +#define CMPLT_HDR_ABORT_STAT_OFF 13 +#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) +/* abort_stat */ +#define STAT_IO_NOT_VALID 0x1 +#define STAT_IO_NO_DEVICE 0x2 +#define STAT_IO_COMPLETE 0x3 +#define STAT_IO_ABORTED 0x4 +/* dw1 */ +#define CMPLT_HDR_IPTT_OFF 0 +#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) +#define CMPLT_HDR_DEV_ID_OFF 16 +#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) +/* dw3 */ +#define CMPLT_HDR_IO_IN_TARGET_OFF 17 +#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) + struct hisi_sas_complete_v3_hdr { __le32 dw0; __le32 dw1; @@ -164,6 +190,24 @@ struct hisi_sas_complete_v3_hdr { __le32 dw3; }; +struct hisi_sas_err_record_v3 { + /* dw0 */ + __le32 trans_tx_fail_type; + + /* dw1 */ + __le32 trans_rx_fail_type; + + /* dw2 */ + __le16 dma_tx_err_type; + __le16 sipc_rx_err_type; + + /* dw3 */ + __le32 dma_rx_err_type; +}; + +#define RX_DATA_LEN_UNDERFLOW_OFF 6 +#define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) + #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 #define HISI_SAS_MSI_COUNT_V3_HW 32 @@ -625,11 +669,275 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) return IRQ_HANDLED; } +static void +slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, + struct hisi_sas_slot *slot) +{ + struct task_status_struct *ts = &task->task_status; + struct hisi_sas_complete_v3_hdr *complete_queue = + hisi_hba->complete_hdr[slot->cmplt_queue]; + struct hisi_sas_complete_v3_hdr *complete_hdr = + &complete_queue[slot->cmplt_queue_slot]; + struct hisi_sas_err_record_v3 *record = slot->status_buffer; + u32 dma_rx_err_type = record->dma_rx_err_type; + u32 trans_tx_fail_type = record->trans_tx_fail_type; + + switch (task->task_proto) { + case SAS_PROTOCOL_SSP: + if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { + ts->residual = trans_tx_fail_type; + ts->stat = SAS_DATA_UNDERRUN; + } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { + ts->stat = SAS_QUEUE_FULL; + slot->abort = 1; + } else { + ts->stat = SAS_OPEN_REJECT; + ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; + } + break; + case SAS_PROTOCOL_SATA: + case SAS_PROTOCOL_STP: + case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: + if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { + ts->residual = trans_tx_fail_type; + ts->stat = SAS_DATA_UNDERRUN; + } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { + ts->stat = SAS_PHY_DOWN; + slot->abort = 1; + } else { + ts->stat = SAS_OPEN_REJECT; + ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; + } + hisi_sas_sata_done(task, slot); + break; + case SAS_PROTOCOL_SMP: + ts->stat = SAM_STAT_CHECK_CONDITION; + break; + default: + break; + } +} + +static int +slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) +{ + struct sas_task *task = slot->task; + struct hisi_sas_device *sas_dev; + struct device *dev = hisi_hba->dev; + struct task_status_struct *ts; + struct domain_device *device; + enum exec_status sts; + struct hisi_sas_complete_v3_hdr *complete_queue = + hisi_hba->complete_hdr[slot->cmplt_queue]; + struct hisi_sas_complete_v3_hdr *complete_hdr = + &complete_queue[slot->cmplt_queue_slot]; + int aborted; + unsigned long flags; + + if (unlikely(!task || !task->lldd_task || !task->dev)) + return -EINVAL; + + ts = &task->task_status; + device = task->dev; + sas_dev = device->lldd_dev; + + spin_lock_irqsave(&task->task_state_lock, flags); + aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED; + task->task_state_flags &= + ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); + spin_unlock_irqrestore(&task->task_state_lock, flags); + + memset(ts, 0, sizeof(*ts)); + ts->resp = SAS_TASK_COMPLETE; + if (unlikely(aborted)) { + ts->stat = SAS_ABORTED_TASK; + hisi_sas_slot_task_free(hisi_hba, task, slot); + return -1; + } + + if (unlikely(!sas_dev)) { + dev_dbg(dev, "slot complete: port has not device\n"); + ts->stat = SAS_PHY_DOWN; + goto out; + } + + /* + * Use SAS+TMF status codes + */ + switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) + >> CMPLT_HDR_ABORT_STAT_OFF) { + case STAT_IO_ABORTED: + /* this IO has been aborted by abort command */ + ts->stat = SAS_ABORTED_TASK; + goto out; + case STAT_IO_COMPLETE: + /* internal abort command complete */ + ts->stat = TMF_RESP_FUNC_SUCC; + goto out; + case STAT_IO_NO_DEVICE: + ts->stat = TMF_RESP_FUNC_COMPLETE; + goto out; + case STAT_IO_NOT_VALID: + /* + * abort single IO, the controller can't find the IO + */ + ts->stat = TMF_RESP_FUNC_FAILED; + goto out; + default: + break; + } + + /* check for erroneous completion */ + if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { + slot_err_v3_hw(hisi_hba, task, slot); + if (unlikely(slot->abort)) + return ts->stat; + goto out; + } + + switch (task->task_proto) { + case SAS_PROTOCOL_SSP: { + struct ssp_response_iu *iu = slot->status_buffer + + sizeof(struct hisi_sas_err_record); + + sas_ssp_task_response(dev, task, iu); + break; + } + case SAS_PROTOCOL_SMP: { + struct scatterlist *sg_resp = &task->smp_task.smp_resp; + void *to; + + ts->stat = SAM_STAT_GOOD; + to = kmap_atomic(sg_page(sg_resp)); + + dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, + DMA_FROM_DEVICE); + dma_unmap_sg(dev, &task->smp_task.smp_req, 1, + DMA_TO_DEVICE); + memcpy(to + sg_resp->offset, + slot->status_buffer + + sizeof(struct hisi_sas_err_record), + sg_dma_len(sg_resp)); + kunmap_atomic(to); + break; + } + case SAS_PROTOCOL_SATA: + case SAS_PROTOCOL_STP: + case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: + ts->stat = SAM_STAT_GOOD; + hisi_sas_sata_done(task, slot); + break; + default: + ts->stat = SAM_STAT_CHECK_CONDITION; + break; + } + + if (!slot->port->port_attached) { + dev_err(dev, "slot complete: port %d has removed\n", + slot->port->sas_port.id); + ts->stat = SAS_PHY_DOWN; + } + +out: + spin_lock_irqsave(&task->task_state_lock, flags); + task->task_state_flags |= SAS_TASK_STATE_DONE; + spin_unlock_irqrestore(&task->task_state_lock, flags); + spin_lock_irqsave(&hisi_hba->lock, flags); + hisi_sas_slot_task_free(hisi_hba, task, slot); + spin_unlock_irqrestore(&hisi_hba->lock, flags); + sts = ts->stat; + + if (task->task_done) + task->task_done(task); + + return sts; +} + +static void cq_tasklet_v3_hw(unsigned long val) +{ + struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; + struct hisi_hba *hisi_hba = cq->hisi_hba; + struct hisi_sas_slot *slot; + struct hisi_sas_itct *itct; + struct hisi_sas_complete_v3_hdr *complete_queue; + u32 rd_point = cq->rd_point, wr_point, dev_id; + int queue = cq->id; + struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; + + complete_queue = hisi_hba->complete_hdr[queue]; + + spin_lock(&dq->lock); + wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + + (0x14 * queue)); + + while (rd_point != wr_point) { + struct hisi_sas_complete_v3_hdr *complete_hdr; + int iptt; + + complete_hdr = &complete_queue[rd_point]; + + /* Check for NCQ completion */ + if (complete_hdr->act) { + u32 act_tmp = complete_hdr->act; + int ncq_tag_count = ffs(act_tmp); + + dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >> + CMPLT_HDR_DEV_ID_OFF; + itct = &hisi_hba->itct[dev_id]; + + /* The NCQ tags are held in the itct header */ + while (ncq_tag_count) { + __le64 *ncq_tag = &itct->qw4_15[0]; + + ncq_tag_count -= 1; + iptt = (ncq_tag[ncq_tag_count / 5] + >> (ncq_tag_count % 5) * 12) & 0xfff; + + slot = &hisi_hba->slot_info[iptt]; + slot->cmplt_queue_slot = rd_point; + slot->cmplt_queue = queue; + slot_complete_v3_hw(hisi_hba, slot); + + act_tmp &= ~(1 << ncq_tag_count); + ncq_tag_count = ffs(act_tmp); + } + } else { + iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; + slot = &hisi_hba->slot_info[iptt]; + slot->cmplt_queue_slot = rd_point; + slot->cmplt_queue = queue; + slot_complete_v3_hw(hisi_hba, slot); + } + + if (++rd_point >= HISI_SAS_QUEUE_SLOTS) + rd_point = 0; + } + + /* update rd_point */ + cq->rd_point = rd_point; + hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); + spin_unlock(&dq->lock); +} + +static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) +{ + struct hisi_sas_cq *cq = p; + struct hisi_hba *hisi_hba = cq->hisi_hba; + int queue = cq->id; + + hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); + + tasklet_schedule(&cq->tasklet); + + return IRQ_HANDLED; +} + static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) { struct device *dev = hisi_hba->dev; struct pci_dev *pdev = hisi_hba->pci_dev; int vectors, rc; + int i, k; int max_msi = HISI_SAS_MSI_COUNT_V3_HW; vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, @@ -657,9 +965,34 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) goto free_phy_irq; } + /* Init tasklets for cq only */ + for (i = 0; i < hisi_hba->queue_count; i++) { + struct hisi_sas_cq *cq = &hisi_hba->cq[i]; + struct tasklet_struct *t = &cq->tasklet; + + rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), + cq_interrupt_v3_hw, 0, + DRV_NAME " cq", cq); + if (rc) { + dev_err(dev, + "could not request cq%d interrupt, rc=%d\n", + i, rc); + rc = -ENOENT; + goto free_cq_irqs; + } + + tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); + } return 0; +free_cq_irqs: + for (k = 0; k < i; k++) { + struct hisi_sas_cq *cq = &hisi_hba->cq[k]; + + free_irq(pci_irq_vector(pdev, k+16), cq); + } + free_irq(pci_irq_vector(pdev, 2), hisi_hba); free_phy_irq: free_irq(pci_irq_vector(pdev, 1), hisi_hba); free_irq_vectors: @@ -840,8 +1173,15 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) static void hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) { + int i; + free_irq(pci_irq_vector(pdev, 1), hisi_hba); free_irq(pci_irq_vector(pdev, 2), hisi_hba); + for (i = 0; i < hisi_hba->queue_count; i++) { + struct hisi_sas_cq *cq = &hisi_hba->cq[i]; + + free_irq(pci_irq_vector(pdev, i+16), cq); + } pci_free_irq_vectors(pdev); } From patchwork Wed Jun 14 15:33:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105532 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp338151qgd; Wed, 14 Jun 2017 08:04:38 -0700 (PDT) X-Received: by 10.98.217.155 with SMTP id b27mr503408pfl.17.1497452678571; Wed, 14 Jun 2017 08:04:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452678; cv=none; d=google.com; s=arc-20160816; b=uxNJTTygUMrDwvRDG2j5/s2BTl0MGPKiwRvYShtwLMB0fnJNy8jTR7lLG/R/kpF3km UW4s7w1Vq3QR2tYFfWhwhM1rjlCdtH7WP247wezQz0PFT0EWdHcGfa0Y87LCqCHL6/QF rlxnmYQBM+Bh+/GRYpifU1YU6c2vabGmOPfw5K5+febYMAN4k1GEysFDTpz8Up5w2itK 8C1kt+82r4CMW1ZOeo8izcLQRQyKvfpOTLKSTUt5bWj9mEM7qobGW4A34XC5stwSsdtl wTvFzK5BFVArfiSyEh3IVZQB7VdmutL6XC5garRTpuVmytDp+6i036GPyKTo7JMNffig sKKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=JpRLiTEiqALF4z5yr2LGZ2j9xA3AiyiyN20S6X3U4Hk=; b=J7ffQC2G74KAORHdNSdDQClHuVB3PJ792+wL2SwYLgpuw02xlbDpCnSjgI9///8T95 S+fZqQdxOr77GNjjbXao8qzSdduesNZCYzsnuWLF7gKjH3Z4ikKHXPz/JMmiUUIvWaso GaPngIuGeAXjDncY1N86Zwc0wqaA1jU1LFdgRXz+zGXa8DClXmDJtJJHhLA5js/ZRW4A +T1UVYFRgYgc3RHaY1hzxF5kiHjgyNZJMG4c+UUXBInml4Wl7pEJ2koEE0fkEjDpxP3G I0lw36uYt2xOzoA/kBAHPQp6A7QKQ3WKqOMh2+bOPrpFpRZd/RH4PTrMLYIRzB9fF21K LKQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d80si160754pfk.223.2017.06.14.08.04.38; Wed, 14 Jun 2017 08:04:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752693AbdFNPE1 (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:27 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7847 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752624AbdFNPEX (ORCPT ); Wed, 14 Jun 2017 11:04:23 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60191; Wed, 14 Jun 2017 23:03:27 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:16 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 15/22] scsi: hisi_sas: add v3 code to send SSP frame Date: Wed, 14 Jun 2017 23:33:25 +0800 Message-ID: <1497454412-91194-16-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59415040.00F9, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8b34dca1572aed6f2786950893fac6b1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare SSP frame and deliver it to hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 208 +++++++++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 4869b73..c869aca 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -157,6 +157,41 @@ #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) +/* HW dma structures */ +/* Delivery queue header */ +/* dw0 */ +#define CMD_HDR_RESP_REPORT_OFF 5 +#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) +#define CMD_HDR_TLR_CTRL_OFF 6 +#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) +#define CMD_HDR_PORT_OFF 18 +#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) +#define CMD_HDR_PRIORITY_OFF 27 +#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) +#define CMD_HDR_CMD_OFF 29 +#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) +/* dw1 */ +#define CMD_HDR_DIR_OFF 5 +#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) +#define CMD_HDR_VDTL_OFF 10 +#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) +#define CMD_HDR_FRAME_TYPE_OFF 11 +#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) +#define CMD_HDR_DEV_ID_OFF 16 +#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) +/* dw2 */ +#define CMD_HDR_CFL_OFF 0 +#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) +#define CMD_HDR_MRFL_OFF 15 +#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) +#define CMD_HDR_SG_MOD_OFF 24 +#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) +/* dw6 */ +#define CMD_HDR_DIF_SGL_LEN_OFF 0 +#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) +#define CMD_HDR_DATA_SGL_LEN_OFF 16 +#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) + /* Completion header */ /* dw0 */ #define CMPLT_HDR_CMPLT_OFF 0 @@ -217,6 +252,11 @@ enum { HISI_SAS_PHY_INT_NR }; +#define DIR_NO_DATA 0 +#define DIR_TO_INI 1 +#define DIR_TO_DEVICE 2 +#define DIR_RESERVED 3 + static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { void __iomem *regs = hisi_hba->regs + off; @@ -224,6 +264,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) return readl(regs); } +static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) +{ + void __iomem *regs = hisi_hba->regs + off; + + return readl_relaxed(regs); +} + static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { void __iomem *regs = hisi_hba->regs + off; @@ -448,6 +495,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); } +/** + * The callpath to this function and upto writing the write + * queue pointer should be safe from interruption. + */ +static int +get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) +{ + struct device *dev = hisi_hba->dev; + int queue = dq->id; + u32 r, w; + + w = dq->wr_point; + r = hisi_sas_read32_relaxed(hisi_hba, + DLVRY_Q_0_RD_PTR + (queue * 0x14)); + if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { + dev_warn(dev, "full queue=%d r=%d w=%d\n\n", + queue, r, w); + return -EAGAIN; + } + + return 0; +} + +static void start_delivery_v3_hw(struct hisi_sas_dq *dq) +{ + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; + + dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; + hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), + dq->wr_point); +} + +static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, + struct hisi_sas_cmd_hdr *hdr, + struct scatterlist *scatter, + int n_elem) +{ + struct device *dev = hisi_hba->dev; + struct scatterlist *sg; + int i; + + if (n_elem > HISI_SAS_SGE_PAGE_CNT) { + dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", + n_elem); + return -EINVAL; + } + + slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, + &slot->sge_page_dma); + if (!slot->sge_page) + return -ENOMEM; + + for_each_sg(scatter, sg, n_elem, i) { + struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; + + entry->addr = cpu_to_le64(sg_dma_address(sg)); + entry->page_ctrl_0 = entry->page_ctrl_1 = 0; + entry->data_len = cpu_to_le32(sg_dma_len(sg)); + entry->data_off = 0; + } + + hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); + hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); + + return 0; +} + +static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, int is_tmf, + struct hisi_sas_tmf_task *tmf) +{ + struct sas_task *task = slot->task; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct domain_device *device = task->dev; + struct hisi_sas_device *sas_dev = device->lldd_dev; + struct hisi_sas_port *port = slot->port; + struct sas_ssp_task *ssp_task = &task->ssp_task; + struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; + int has_data = 0, rc, priority = is_tmf; + u8 *buf_cmd; + u32 dw1 = 0, dw2 = 0; + + hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | + (2 << CMD_HDR_TLR_CTRL_OFF) | + (port->id << CMD_HDR_PORT_OFF) | + (priority << CMD_HDR_PRIORITY_OFF) | + (1 << CMD_HDR_CMD_OFF)); /* ssp */ + + dw1 = 1 << CMD_HDR_VDTL_OFF; + if (is_tmf) { + dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; + dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; + } else { + dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; + switch (scsi_cmnd->sc_data_direction) { + case DMA_TO_DEVICE: + has_data = 1; + dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; + break; + case DMA_FROM_DEVICE: + has_data = 1; + dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; + break; + default: + dw1 &= ~CMD_HDR_DIR_MSK; + } + } + + /* map itct entry */ + dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; + hdr->dw1 = cpu_to_le32(dw1); + + dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) + + 3) / 4) << CMD_HDR_CFL_OFF) | + ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | + (2 << CMD_HDR_SG_MOD_OFF); + hdr->dw2 = cpu_to_le32(dw2); + hdr->transfer_tags = cpu_to_le32(slot->idx); + + if (has_data) { + rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, + slot->n_elem); + if (rc) + return rc; + } + + hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); + hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); + memcpy(buf_cmd, ssp_task->LUN, 8); + + if (!is_tmf) { + buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); + memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); + } else { + buf_cmd[10] = tmf->tmf; + switch (tmf->tmf) { + case TMF_ABORT_TASK: + case TMF_QUERY_TASK: + buf_cmd[12] = + (tmf->tag_of_task_to_be_managed >> 8) & 0xff; + buf_cmd[13] = + tmf->tag_of_task_to_be_managed & 0xff; + break; + default: + break; + } + } + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1020,6 +1224,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), .sl_notify = sl_notify_v3_hw, + .prep_ssp = prep_ssp_v3_hw, + .get_free_slot = get_free_slot_v3_hw, + .start_delivery = start_delivery_v3_hw, + .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, }; From patchwork Wed Jun 14 15:33:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105542 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp380568obh; Wed, 14 Jun 2017 08:12:13 -0700 (PDT) X-Received: by 10.84.131.163 with SMTP id d32mr665354pld.16.1497453133483; Wed, 14 Jun 2017 08:12:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453133; cv=none; d=google.com; s=arc-20160816; b=cDyNfhWPNX2j1GURME1HGiC4Utg2+VvRT5x96njq3fU2DuukWnx4T70pXL1bA48myc eH5pu5C/a8OU/91ftc4K1q+h1Ukw7viGJkb8/EfP/6aQ5yKOix9jH+pyxoB1qOvW/HsP eA2P2c1B0x2qbYbfDn53nCwfV80GVezznRQPl++yUaB3MI1npx37F3faoH6ZwWD8DLNL kmjmezqm9H1U4vNkXpfGmFVnKOKhdvCiujssdjf4gmylziOZI6BuQtZiY30lzp8Ga5kD AVaMsTXk6HJo9U3NcyLXjNMTdStx/WbLPUrgFkMHX7aWxzCD1hju/vGRC4A3bFM8xkdN u7qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=POtUC5nJHv03+b2WWnbYXN14soFjhh/b21WH94qdutE=; b=Rq4DfqlFpYXNX7DidtTRC3o7cvmsejpzPCT16gUaIJdMCcWo1bPAzhw/RSJfQoT+Uw Q/8pTDAtWqgOgkcDbRu2wLzcWrueWUv8SCQ2XSo2uVhud9kG7CHMeRiMygyG0lpVwW4p tU7++eusBgCdDGeREOrC/wUUpC3cs+t3sUWr+rP5eTHA52uUw+NgeJHdwpn4MPVQfkS1 0nTEZ8E3dG0yVSAH+C2RGNOt8Wv9rlyCXCPtZAPJuvwCEEjdA5lA7wRF2Fe2CWnqMeQw o8d+uVBc7GsQN8iBheZt84Q4aGkhPTm7/0oym0q/N/GXj0YjbjoBZsZhivr4y8Yf42hJ lTGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v30si168561pfl.262.2017.06.14.08.12.13; Wed, 14 Jun 2017 08:12:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752552AbdFNPEM (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:12 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7840 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752495AbdFNPEJ (ORCPT ); Wed, 14 Jun 2017 11:04:09 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60197; Wed, 14 Jun 2017 23:03:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:17 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 16/22] scsi: hisi_sas: add v3 code to send SMP frame Date: Wed, 14 Jun 2017 23:33:26 +0800 Message-ID: <1497454412-91194-17-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59415040.0243, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d7f25f668894ed323fdc6a1973a97a46 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare SMP frame. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index c869aca..515f50c 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -186,6 +186,9 @@ #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) #define CMD_HDR_SG_MOD_OFF 24 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) +/* dw3 */ +#define CMD_HDR_IPTT_OFF 0 +#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) /* dw6 */ #define CMD_HDR_DIF_SGL_LEN_OFF 0 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) @@ -652,6 +655,76 @@ static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba, return 0; } +static int prep_smp_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot) +{ + struct sas_task *task = slot->task; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct domain_device *device = task->dev; + struct device *dev = hisi_hba->dev; + struct hisi_sas_port *port = slot->port; + struct scatterlist *sg_req, *sg_resp; + struct hisi_sas_device *sas_dev = device->lldd_dev; + dma_addr_t req_dma_addr; + unsigned int req_len, resp_len; + int elem, rc; + + /* + * DMA-map SMP request, response buffers + */ + /* req */ + sg_req = &task->smp_task.smp_req; + elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); + if (!elem) + return -ENOMEM; + req_len = sg_dma_len(sg_req); + req_dma_addr = sg_dma_address(sg_req); + + /* resp */ + sg_resp = &task->smp_task.smp_resp; + elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); + if (!elem) { + rc = -ENOMEM; + goto err_out_req; + } + resp_len = sg_dma_len(sg_resp); + if ((req_len & 0x3) || (resp_len & 0x3)) { + rc = -EINVAL; + goto err_out_resp; + } + + /* create header */ + /* dw0 */ + hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | + (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ + (2 << CMD_HDR_CMD_OFF)); /* smp */ + + /* map itct entry */ + hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | + (1 << CMD_HDR_FRAME_TYPE_OFF) | + (DIR_NO_DATA << CMD_HDR_DIR_OFF)); + + /* dw2 */ + hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | + (HISI_SAS_MAX_SMP_RESP_SZ / 4 << + CMD_HDR_MRFL_OFF)); + + hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); + + hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + return 0; + +err_out_resp: + dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, + DMA_FROM_DEVICE); +err_out_req: + dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, + DMA_TO_DEVICE); + return rc; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1225,6 +1298,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), .sl_notify = sl_notify_v3_hw, .prep_ssp = prep_ssp_v3_hw, + .prep_smp = prep_smp_v3_hw, .get_free_slot = get_free_slot_v3_hw, .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, From patchwork Wed Jun 14 15:33:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105530 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp337975qgd; Wed, 14 Jun 2017 08:04:20 -0700 (PDT) X-Received: by 10.99.175.69 with SMTP id s5mr527470pgo.240.1497452660552; Wed, 14 Jun 2017 08:04:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452660; cv=none; d=google.com; s=arc-20160816; b=XM06hY0sUD9ePKHd2kjoxVVknwJn9if4axMXDyx7g6abspnzjHKRM7pscve1/pJpkp EUxB2BzlKUSY72xjUrhZDHC3G8mfSuThbzzCqvl1gWYJdOhRelgxxhNSgTKN+O7ytoKx BWfUz1vUnGSShiy5QFoNB6JqHcM6bGUh6QTeoeW/qsl086y6vbWfT7craJnYEhhsTAea T6CWKlMJRxATDaIvdWWXPxpLEpJeDFjhAk0MehXQnjk4P3eQbbp7LQxaaC8WxL6Qs6ub ljuNMHtYgOBS2LgpdrGv+EZnQBD4aWMmDKyaOLCyVFtyFuEHZ3sMGlx6zvZalPNCkh4G YPqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=efPOO+3euZQ2+nEndEjJyxSsmH4h7WCjipJwvmzXQxo=; b=OqDB892Q727RXm9S0ItEiYT/r9HlENE76x44eQng0ggfQ3itmawdpelyKBy1naFPZJ YbHFd7TCEeR+d4zs5NDjaJGoupzhVvvnVsGJ+zXE6/UybSb5L63FPb4h1Sn7gCTX7wI4 iXriX0ogA2pdVgIm8+lkp6mdsnICHznIVUYIe2O/cDnejSymAVE9SIO9t6/+qSiUVTD5 HRofwShlgX7lk0fhsqaZHQKM60aswjGBiyD17Yl4P5yAmqokuCBrccB4a7WfVzaNnB15 mGiBSdhY5wfyXXj5NZfkLH7SgTVcI5XKhngWHK4MTkIRbj/CVR4nNBSgbnsN9jXyCSf+ Ukdg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t16si167412pfi.97.2017.06.14.08.04.20; Wed, 14 Jun 2017 08:04:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752623AbdFNPES (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:18 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7837 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752555AbdFNPEO (ORCPT ); Wed, 14 Jun 2017 11:04:14 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60192; Wed, 14 Jun 2017 23:03:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:17 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 17/22] scsi: hisi_sas: add v3 code to send ATA frame Date: Wed, 14 Jun 2017 23:33:27 +0800 Message-ID: <1497454412-91194-18-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59415040.0114, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7239be1e222c947268a9c41a5ab9f5b3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare ATA frame for v3 hw Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 106 +++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 515f50c..30c103b 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -171,8 +171,11 @@ #define CMD_HDR_CMD_OFF 29 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) /* dw1 */ +#define CMD_HDR_UNCON_CMD_OFF 3 #define CMD_HDR_DIR_OFF 5 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) +#define CMD_HDR_RESET_OFF 7 +#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) #define CMD_HDR_VDTL_OFF 10 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) #define CMD_HDR_FRAME_TYPE_OFF 11 @@ -182,6 +185,8 @@ /* dw2 */ #define CMD_HDR_CFL_OFF 0 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) +#define CMD_HDR_NCQ_TAG_OFF 10 +#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) #define CMD_HDR_MRFL_OFF 15 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) #define CMD_HDR_SG_MOD_OFF 24 @@ -260,6 +265,11 @@ enum { #define DIR_TO_DEVICE 2 #define DIR_RESERVED 3 +#define CMD_IS_UNCONSTRAINT(cmd) \ + ((cmd == ATA_CMD_READ_LOG_EXT) || \ + (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \ + (cmd == ATA_CMD_DEV_RESET)) + static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { void __iomem *regs = hisi_hba->regs + off; @@ -725,6 +735,101 @@ static int prep_smp_v3_hw(struct hisi_hba *hisi_hba, return rc; } +static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag) +{ + struct ata_queued_cmd *qc = task->uldd_task; + + if (qc) { + if (qc->tf.command == ATA_CMD_FPDMA_WRITE || + qc->tf.command == ATA_CMD_FPDMA_READ) { + *tag = qc->tag; + return 1; + } + } + return 0; +} + +static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot) +{ + struct sas_task *task = slot->task; + struct domain_device *device = task->dev; + struct domain_device *parent_dev = device->parent; + struct hisi_sas_device *sas_dev = device->lldd_dev; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct asd_sas_port *sas_port = device->port; + struct hisi_sas_port *port = to_hisi_sas_port(sas_port); + u8 *buf_cmd; + int has_data = 0, rc = 0, hdr_tag = 0; + u32 dw1 = 0, dw2 = 0; + + hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); + if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) + hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); + else + hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); + + switch (task->data_dir) { + case DMA_TO_DEVICE: + has_data = 1; + dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; + break; + case DMA_FROM_DEVICE: + has_data = 1; + dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; + break; + default: + dw1 &= ~CMD_HDR_DIR_MSK; + } + + if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && + (task->ata_task.fis.control & ATA_SRST)) + dw1 |= 1 << CMD_HDR_RESET_OFF; + + dw1 |= (hisi_sas_get_ata_protocol( + task->ata_task.fis.command, task->data_dir)) + << CMD_HDR_FRAME_TYPE_OFF; + dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; + + if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command)) + dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; + + hdr->dw1 = cpu_to_le32(dw1); + + /* dw2 */ + if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) { + task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); + dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; + } + + dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | + 2 << CMD_HDR_SG_MOD_OFF; + hdr->dw2 = cpu_to_le32(dw2); + + /* dw3 */ + hdr->transfer_tags = cpu_to_le32(slot->idx); + + if (has_data) { + rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, + slot->n_elem); + if (rc) + return rc; + } + + hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); + hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + buf_cmd = slot->command_table; + + if (likely(!task->ata_task.device_control_reg_update)) + task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ + /* fill in command FIS */ + memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1299,6 +1404,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .sl_notify = sl_notify_v3_hw, .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, + .prep_stp = prep_ata_v3_hw, .get_free_slot = get_free_slot_v3_hw, .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, From patchwork Wed Jun 14 15:33:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105538 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp380089obh; Wed, 14 Jun 2017 08:11:11 -0700 (PDT) X-Received: by 10.98.102.151 with SMTP id s23mr571531pfj.22.1497453071474; Wed, 14 Jun 2017 08:11:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453071; cv=none; d=google.com; s=arc-20160816; b=X/fNysmN6oxavGqPiAik+/Z2kpDGW5bt1eRCiyq5XcvgIHr3oOe0yOqyttk/oHwnTa 2DPvQx0FN9iXsyUONQuY2F6YrPrGpbKGWKWmDeVOrMdkxeQoJf1C/CPDLOlLxSwN0s5D G09sl36gZMkwWIky+QYw6fJW29IGV0/VJFULFK1a8OOBB12yPAE1sIUIvFRZ3XSmksJy noXMcLxE/a8uXE+YikhosatVoMi/DJus2acMTQZL6+BYziZ8YjbxL8wDmXeeFiiaY29v ifG2CTJ0jAR6ETweE2BfSuYAN1MaxS0SrALoqb7O3u+uRXeLNjLzRzCanvqQmNocU2vl RfBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=bydYqL3ia9IKskk+tp6aJ7zX3MPkDENa0bOCtZXfCY0=; b=iuEqjMAVMFkgnlLvS3ahDycG/O4erWCcxR0IYhlUQfYwyIa9njjH8L6gEE0/hQX2LM TnFC2dDHbBrDQlr8wSiM/fmmdfiwts24Wcbf6aGOkqMGmjVsXX79i9UAWHeipRqYR4Mh PNhLE2+ehpcRoXooc0SN32SSPS5eXXolrvgYcl/Vc+5bG7d3GAZw4WZM198E+6pBcFuP ryZZJnZedvKNqeIl/kGftRdH974vy8FWIGSgjcNMzbSJNFzDyxc4uwdycA6UEVegVo1J Ada4X67lDHpCavTM2iv2r0iSkmvE9M1+ozwHuHkGlECOUP04PXayB8BHBGsejBDA+tu5 R/yg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s18si170300pfs.171.2017.06.14.08.11.11; Wed, 14 Jun 2017 08:11:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752801AbdFNPLC (ORCPT + 25 others); Wed, 14 Jun 2017 11:11:02 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7843 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752593AbdFNPER (ORCPT ); Wed, 14 Jun 2017 11:04:17 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60198; Wed, 14 Jun 2017 23:03:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:17 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 18/22] scsi: hisi_sas: add v3 code for itct setup and free Date: Wed, 14 Jun 2017 23:33:28 +0800 Message-ID: <1497454412-91194-19-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59415041.00C1, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 94f1a7e6623639253c999629aa1c44b9 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to itct setup and free for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 114 +++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 30c103b..b9ab24d 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -24,6 +24,11 @@ #define PHY_PORT_NUM_MA 0x28 #define PHY_CONN_RATE 0x30 #define AXI_AHB_CLK_CFG 0x3c +#define ITCT_CLR 0x44 +#define ITCT_CLR_EN_OFF 16 +#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) +#define ITCT_DEV_OFF 0 +#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) #define AXI_USER1 0x48 #define AXI_USER2 0x4c #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 @@ -226,6 +231,26 @@ #define CMPLT_HDR_IO_IN_TARGET_OFF 17 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) +/* ITCT header */ +/* qw0 */ +#define ITCT_HDR_DEV_TYPE_OFF 0 +#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) +#define ITCT_HDR_VALID_OFF 2 +#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) +#define ITCT_HDR_MCR_OFF 5 +#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) +#define ITCT_HDR_VLN_OFF 9 +#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) +#define ITCT_HDR_SMP_TIMEOUT_OFF 16 +#define ITCT_HDR_AWT_CONTINUE_OFF 25 +#define ITCT_HDR_PORT_ID_OFF 28 +#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) +/* qw2 */ +#define ITCT_HDR_INLT_OFF 0 +#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) +#define ITCT_HDR_RTOLT_OFF 48 +#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) + struct hisi_sas_complete_v3_hdr { __le32 dw0; __le32 dw1; @@ -460,6 +485,93 @@ static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) __swab32(identify_buffer[5])); } +static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_device *sas_dev) +{ + struct domain_device *device = sas_dev->sas_device; + struct device *dev = hisi_hba->dev; + u64 qw0, device_id = sas_dev->device_id; + struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; + struct domain_device *parent_dev = device->parent; + struct asd_sas_port *sas_port = device->port; + struct hisi_sas_port *port = to_hisi_sas_port(sas_port); + + memset(itct, 0, sizeof(*itct)); + + /* qw0 */ + qw0 = 0; + switch (sas_dev->dev_type) { + case SAS_END_DEVICE: + case SAS_EDGE_EXPANDER_DEVICE: + case SAS_FANOUT_EXPANDER_DEVICE: + qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; + break; + case SAS_SATA_DEV: + case SAS_SATA_PENDING: + if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) + qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; + else + qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; + break; + default: + dev_warn(dev, "setup itct: unsupported dev type (%d)\n", + sas_dev->dev_type); + } + + qw0 |= ((1 << ITCT_HDR_VALID_OFF) | + (device->linkrate << ITCT_HDR_MCR_OFF) | + (1 << ITCT_HDR_VLN_OFF) | + (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | + (1 << ITCT_HDR_AWT_CONTINUE_OFF) | + (port->id << ITCT_HDR_PORT_ID_OFF)); + itct->qw0 = cpu_to_le64(qw0); + + /* qw1 */ + memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); + itct->sas_addr = __swab64(itct->sas_addr); + + /* qw2 */ + if (!dev_is_sata(device)) + itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | + (0x1ULL << ITCT_HDR_RTOLT_OFF)); +} + +static void free_device_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_device *sas_dev) +{ + u64 dev_id = sas_dev->device_id; + struct device *dev = hisi_hba->dev; + struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; + u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + + /* clear the itct interrupt state */ + if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + ENT_INT_SRC3_ITC_INT_MSK); + + /* clear the itct table*/ + reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); + reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); + hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); + + udelay(10); + reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { + dev_dbg(dev, "got clear ITCT done interrupt\n"); + + /* invalid the itct state*/ + memset(itct, 0, sizeof(struct hisi_sas_itct)); + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + ENT_INT_SRC3_ITC_INT_MSK); + hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED; + hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL; + + /* clear the itct */ + hisi_sas_write32(hisi_hba, ITCT_CLR, 0); + dev_dbg(dev, "clear ITCT ok\n"); + } +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -1399,8 +1511,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, + .setup_itct = setup_itct_v3_hw, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .free_device = free_device_v3_hw, .sl_notify = sl_notify_v3_hw, .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, From patchwork Wed Jun 14 15:33:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105527 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp337808qgd; Wed, 14 Jun 2017 08:04:05 -0700 (PDT) X-Received: by 10.99.53.197 with SMTP id c188mr484050pga.165.1497452645245; Wed, 14 Jun 2017 08:04:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452645; cv=none; d=google.com; s=arc-20160816; b=Mm8raKe01dtHM+Kx8cMahqhDnIuVcgjBnl5nFCBiWRESrXqxbEoYvCZEH5/ixrBpcs 3E8QQJIxqpHLhWQlOzpryIjRj3QOQX/qrfXFZfik+qhJUEA81icOBDZnt1zxfcOEvFLx rEVvfQCFRemcGppbYAtkIHNMuPTt95VwCSta06TGbY8+4zzWPOUqvTv3IYp9yg237kA3 630CXrWiXoJTI8IPvP5dcyo3xZei9DTtowNKb/WT0iE8Atpl8dQG0nHJqOKbuyh/b0Rx Qp6w6NVJ4IiOO34GdBZkHiZ6Y/c7Q9vtDlFl6wf4Tr1DDsQvFTByjxhrZDzBpo1iJ8eB oZHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=LjG9vvEBpZVoOHhlrl15N5vgyflCFrMNXO5gD5qJZXo=; b=jGQMV1iNnPDZYoe4Yxy/YgB3+Y3KjF0yegZTG8ZKlS95YfsIRKgnMkDbaitR+XIvnw 86FKAUvCgwJDOXzDzyPCREwHB4lMO0ixMVgF6bHpOHdPieA7vaV+69uxnSYEjLIN/am5 mDwQKPMMEwyaK08I1IT4eEbCfsAsTF2vB2UdFLr1asLmfWxYmskBkPjRq4P3U3htUS2C iWorGy+eTdw8mWQz/MF1b/vE0fbWPU+7iqDbyeiIp1erZrsB8KVAj83i9M4TxnuNO+n5 WhnDttID0bUarPNApoQY/PGb2tX1Dp4XXtU+Dr/+2hLGOJ/BDb+Df7DYANLS3ywSDCF6 VUUA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t16si167412pfi.97.2017.06.14.08.04.04; Wed, 14 Jun 2017 08:04:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752440AbdFNPEC (ORCPT + 25 others); Wed, 14 Jun 2017 11:04:02 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7832 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752265AbdFNPEA (ORCPT ); Wed, 14 Jun 2017 11:04:00 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60199; Wed, 14 Jun 2017 23:03:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:18 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 19/22] scsi: hisi_sas: add v3 code to send internal abort command Date: Wed, 14 Jun 2017 23:33:29 +0800 Message-ID: <1497454412-91194-20-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59415041.01B9, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 69c6f23a6330dff37405842912cbebd1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to prepare internal abort command. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index b9ab24d..ef5c158 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -165,6 +165,10 @@ /* HW dma structures */ /* Delivery queue header */ /* dw0 */ +#define CMD_HDR_ABORT_FLAG_OFF 0 +#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) +#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 +#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) #define CMD_HDR_RESP_REPORT_OFF 5 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) #define CMD_HDR_TLR_CTRL_OFF 6 @@ -204,6 +208,11 @@ #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) #define CMD_HDR_DATA_SGL_LEN_OFF 16 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) +/* dw7 */ +#define CMD_HDR_ADDR_MODE_SEL_OFF 15 +#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) +#define CMD_HDR_ABORT_IPTT_OFF 16 +#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) /* Completion header */ /* dw0 */ @@ -942,6 +951,34 @@ static int prep_ata_v3_hw(struct hisi_hba *hisi_hba, return 0; } +static int prep_abort_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, + int device_id, int abort_flag, int tag_to_abort) +{ + struct sas_task *task = slot->task; + struct domain_device *dev = task->dev; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct hisi_sas_port *port = slot->port; + + /* dw0 */ + hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ + (port->id << CMD_HDR_PORT_OFF) | + ((dev_is_sata(dev) ? 1:0) + << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | + (abort_flag + << CMD_HDR_ABORT_FLAG_OFF)); + + /* dw1 */ + hdr->dw1 = cpu_to_le32(device_id + << CMD_HDR_DEV_ID_OFF); + + /* dw7 */ + hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); + hdr->transfer_tags = cpu_to_le32(slot->idx); + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1519,6 +1556,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, .prep_stp = prep_ata_v3_hw, + .prep_abort = prep_abort_v3_hw, .get_free_slot = get_free_slot_v3_hw, .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, From patchwork Wed Jun 14 15:33:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105547 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp381225obh; Wed, 14 Jun 2017 08:13:35 -0700 (PDT) X-Received: by 10.84.174.3 with SMTP id q3mr669461plb.52.1497453215796; Wed, 14 Jun 2017 08:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497453215; cv=none; d=google.com; s=arc-20160816; b=OV5qwlN2upnSSr6jl6GDLcybD7d2kBEJB68Qq00qHiTGcmr7O4w1cb9iX/se3Pe202 Wo9omZ6e7rk+zn6yKekvuitus0c6wWalyK/GYmY715Vn43imcUP8gieFA8gzfa+IZMSj Qa0hkxvh9KYbJ4A6NXit06EgIB5Nq+xGAEhd/9v2AuLAjWNu2rx7iByciPq8Xz0lC7uP Z6Cfm6ugxhL3r5EV3Cw8l56hcj/aiJBGNDbCXyqSG1LJENsi5k6coHTrHT4LVPlfhr30 j7MeYCI2r/477Wr2JQF5ZYT7hR6sIfCj7RV578Pp8dYa3GfPPMBL7dNQPXQiEe8yheAJ dOrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=V0eWyw2I7v5RWppXDCWiYPHQtUwkniAn5nbSXCLeAFQ=; b=ccOes1wRBLV0Xno9a3Ek6QSs1UdwT1QEGhYLW3201ZLtXVffQYMmTne8ZTBy/dfdUZ A/Qhnf6fTP5ogYfTx7qfOyWHw6GqJ40v/BDgS3ag2ks7p0zUznosOgfXFhZ0kuGz+Vn/ pnEnqqmUdNs100rcDdunAab+bveibms7QoK5mWARmloeoTgmQj9zUCXODvyBMHsjTBCq w2hwxjUUaN7VYDvxYy6M97GsbQqDfnUz9dCGij7hzLf5BfSEmgB3qTgmjjkGVYVk+UP6 KOJ4pmqrWQChTZTl0W6cNoFMttC41G5VNTfIa7MtP+gjVuZheIpLuudS7InZ8PzjWewR FPkA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a6si172661pgc.392.2017.06.14.08.13.35; Wed, 14 Jun 2017 08:13:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752784AbdFNPNB (ORCPT + 25 others); Wed, 14 Jun 2017 11:13:01 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:7423 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752447AbdFNPEL (ORCPT ); Wed, 14 Jun 2017 11:04:11 -0400 Received: from 172.30.72.54 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.54]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APJ61005; Wed, 14 Jun 2017 23:03:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:19 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 21/22] scsi: hisi_sas: add v3 code to fill some more hw function pointers Date: Wed, 14 Jun 2017 23:33:31 +0800 Message-ID: <1497454412-91194-22-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59415042.008E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d8e05f512f58180fceafc0db143622a3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate, and phy enable/disable. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 3cd4b9a..cf1eb47 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -129,6 +129,8 @@ #define TXID_AUTO (PORT_BASE + 0xb8) #define CT3_OFF 1 #define CT3_MSK (0x1 << CT3_OFF) +#define TX_HARDRST_OFF 2 +#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) @@ -596,6 +598,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } +static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg &= ~PHY_CFG_ENA_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { config_id_frame_v3_hw(hisi_hba, phy_no); @@ -603,6 +613,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) enable_phy_v3_hw(hisi_hba, phy_no); } +static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + disable_phy_v3_hw(hisi_hba, phy_no); +} + static void start_phys_v3_hw(struct hisi_hba *hisi_hba) { int i; @@ -611,6 +626,26 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba) start_phy_v3_hw(hisi_hba, i); } +static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; + u32 txid_auto; + + stop_phy_v3_hw(hisi_hba, phy_no); + if (phy->identify.device_type == SAS_END_DEVICE) { + txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); + hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, + txid_auto | TX_HARDRST_MSK); + } + msleep(100); + start_phy_v3_hw(hisi_hba, phy_no); +} + +enum sas_linkrate phy_get_max_linkrate_v3_hw(void) +{ + return SAS_LINK_RATE_12_0_GBPS; +} + static void phys_init_v3_hw(struct hisi_hba *hisi_hba) { start_phys_v3_hw(hisi_hba); @@ -1574,6 +1609,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, + .phy_enable = enable_phy_v3_hw, + .phy_disable = disable_phy_v3_hw, + .phy_hard_reset = phy_hard_reset_v3_hw, + .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, }; static struct Scsi_Host * From patchwork Wed Jun 14 15:33:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 105533 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp338608qgd; Wed, 14 Jun 2017 08:05:27 -0700 (PDT) X-Received: by 10.84.217.89 with SMTP id e25mr548814plj.275.1497452726241; Wed, 14 Jun 2017 08:05:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497452726; cv=none; d=google.com; s=arc-20160816; b=jSktvuzFDTjGoLkZKTWsCfkQVENQ4X5wicjpAKNUzNKYFsTIURWIBfAWguOuoKKAmq vntIfst75YW/nYTyDx+QTSZdThvW5srwWuKP7D22P65wyZy+p+DHrJsnobdTX76goa55 KepOEOeub+7xnNVZKi/ekKt1ldIgqI1DBsjU7rnMEQs1ENl1MlmUR9ulK2yNJMLp4CCA wonCJ0u/kdDFk6k6dcI4PFyD8kFF3hxt3BQZbutaE0amwDLnz0cZJRWTgMqq6ZnVbHPx 9jlNKf9fkzuyN3kZ5WOPzErwqDt8K8v59+IXVjNfFobTrtuMSYwCBgdScD3+CAw8jNmd flyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=C+UBrjYJ3gSVIzbFhVzg2zrsaC2Hda0BYH1vC9s4tD4=; b=dvu2f9XY5/5ySHRQbYsV8+nmGIth77RPKgfFz2CU97h0azjaUw3Iz0MWUfCbQqHKuG OeSKht7Fchje8k+949He5miKkAf7yZVSoqzpcrKMA5RnrZC7eBtZ+rWYLkQIdgb5HLfZ GaLaR5/EfKIjqlpXJ6/GuY/GHJDWujIJOrJDqP/lFNr891ZZudOMhm+VgwYbIMCHVYFf iGpRB6B4k2BFLWN8/4jSUC6tj3fGld1GLiG2bsluQFNj98S0f//czGMrr/qHIAujwvX1 eMkquYH1ge17/aPtmx4uKr9Xe7AQnFFW0xUElUBUwXto0/urtr2jd5dgUebbOJJT6HkC 8QbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h26si166442pfk.157.2017.06.14.08.05.25; Wed, 14 Jun 2017 08:05:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752327AbdFNPFD (ORCPT + 25 others); Wed, 14 Jun 2017 11:05:03 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:7839 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752332AbdFNPEU (ORCPT ); Wed, 14 Jun 2017 11:04:20 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id API60202; Wed, 14 Jun 2017 23:03:29 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 14 Jun 2017 23:03:19 +0800 From: John Garry To: , CC: , , , , , "Xiang Chen" , John Garry Subject: [PATCH v6 22/22] scsi: hisi_sas: modify internal abort dev flow for v3 hw Date: Wed, 14 Jun 2017 23:33:32 +0800 Message-ID: <1497454412-91194-23-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497454412-91194-1-git-send-email-john.garry@huawei.com> References: <1497454412-91194-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5941504E.00D0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 411e8f700674ec946861227424a43353 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen There is a change for abort dev for v3 hw: add registers to configure unaborted iptt for a device, and then inform this to logic. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index e89f6ae..4fc2308 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -188,6 +188,8 @@ struct hisi_sas_hw { void (*free_device)(struct hisi_hba *hisi_hba, struct hisi_sas_device *dev); int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id); + void (*dereg_device)(struct hisi_hba *hisi_hba, + struct domain_device *device); int (*soft_reset)(struct hisi_hba *hisi_hba); int max_command_entries; int complete_hdr_size; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 0a32211..0e2db9a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -727,6 +727,13 @@ static void hisi_sas_release_tasks(struct hisi_hba *hisi_hba) } } +static void hisi_sas_dereg_device(struct hisi_hba *hisi_hba, + struct domain_device *device) +{ + if (hisi_hba->hw->dereg_device) + hisi_hba->hw->dereg_device(hisi_hba, device); +} + static void hisi_sas_dev_gone(struct domain_device *device) { struct hisi_sas_device *sas_dev = device->lldd_dev; @@ -740,6 +747,8 @@ static void hisi_sas_dev_gone(struct domain_device *device) hisi_sas_internal_task_abort(hisi_hba, device, HISI_SAS_INT_ABT_DEV, 0); + hisi_sas_dereg_device(hisi_hba, device); + hisi_hba->hw->free_device(hisi_hba, sas_dev); device->lldd_dev = NULL; memset(sas_dev, 0, sizeof(*sas_dev)); @@ -1071,6 +1080,7 @@ static int hisi_sas_abort_task(struct sas_task *task) if (task->dev->dev_type == SAS_SATA_DEV) { hisi_sas_internal_task_abort(hisi_hba, device, HISI_SAS_INT_ABT_DEV, 0); + hisi_sas_dereg_device(hisi_hba, device); rc = hisi_sas_softreset_ata_disk(device); } } else if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SMP) { @@ -1137,6 +1147,10 @@ static int hisi_sas_I_T_nexus_reset(struct domain_device *device) return TMF_RESP_FUNC_FAILED; sas_dev->dev_status = HISI_SAS_DEV_NORMAL; + hisi_sas_internal_task_abort(hisi_hba, device, + HISI_SAS_INT_ABT_DEV, 0); + hisi_sas_dereg_device(hisi_hba, device); + rc = hisi_sas_debug_I_T_nexus_reset(device); if (rc == TMF_RESP_FUNC_COMPLETE) { @@ -1164,6 +1178,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun) HISI_SAS_INT_ABT_DEV, 0); if (rc == TMF_RESP_FUNC_FAILED) goto out; + hisi_sas_dereg_device(hisi_hba, device); phy = sas_get_local_phy(device); diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index cf1eb47..c998b81 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -50,6 +50,10 @@ #define CFG_ABT_SET_QUERY_IPTT 0xd4 #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) +#define CFG_SET_ABORTED_EN_OFF 12 +#define CFG_ABT_SET_IPTT_DONE 0xd8 +#define CFG_ABT_SET_IPTT_DONE_OFF 0 +#define HGC_IOMB_PROC1_STATUS 0x104 #define CFG_1US_TIMER_TRSH 0xcc #define CHNL_INT_STATUS 0x148 #define INT_COAL_EN 0x19c @@ -583,6 +587,29 @@ static void free_device_v3_hw(struct hisi_hba *hisi_hba, } } +static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, + struct domain_device *device) +{ + struct hisi_sas_slot *slot, *slot2; + struct hisi_sas_device *sas_dev = device->lldd_dev; + u32 cfg_abt_set_query_iptt; + + cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, + CFG_ABT_SET_QUERY_IPTT); + list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { + cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; + cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | + (slot->idx << CFG_SET_ABORTED_IPTT_OFF); + hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, + cfg_abt_set_query_iptt); + } + cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); + hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, + cfg_abt_set_query_iptt); + hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, + 1 << CFG_ABT_SET_IPTT_DONE_OFF); +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -1613,6 +1640,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .phy_disable = disable_phy_v3_hw, .phy_hard_reset = phy_hard_reset_v3_hw, .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, + .dereg_device = dereg_device_v3_hw, }; static struct Scsi_Host *