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Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Gregor Herburger Signed-off-by: Matthias Schiffer --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3dbddec070281..1c28a48915bb2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1576,7 +1576,7 @@ config GPIO_TPS68470 are "output only" GPIOs. config GPIO_TQMX86 - tristate "TQ-Systems QTMX86 GPIO" + tristate "TQ-Systems TQMx86 GPIO" depends on MFD_TQMX86 || COMPILE_TEST depends on HAS_IOPORT_MAP select GPIOLIB_IRQCHIP From patchwork Wed May 29 07:45:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 800354 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C4FD168C02; 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Reading the register will always return current inputs rather than the previously set outputs (regardless of the current direction setting). Therefore, using a RMW pattern does not make sense when setting output values. Instead, the previously set output register value needs to be stored as a shadow register. As there is no reliable way to get the current output values from the hardware, also initialize all channels to 0, to ensure that stored and actual output values match. This should usually not have any effect in practise, as the TQMx86 UEFI sets all outputs to 0 during boot. Also prepare for extension of the driver to more than 8 GPIOs by using DECLARE_BITMAP. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 3a28c1f273c39..b7e2dbbdc4ebe 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -6,6 +6,7 @@ * Vadim V.Vlasov */ +#include #include #include #include @@ -38,6 +39,7 @@ struct tqmx86_gpio_data { void __iomem *io_base; int irq; raw_spinlock_t spinlock; + DECLARE_BITMAP(output, TQMX86_NGPIO); u8 irq_type[TQMX86_NGPI]; }; @@ -64,15 +66,10 @@ static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, { struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); unsigned long flags; - u8 val; raw_spin_lock_irqsave(&gpio->spinlock, flags); - val = tqmx86_gpio_read(gpio, TQMX86_GPIOD); - if (value) - val |= BIT(offset); - else - val &= ~BIT(offset); - tqmx86_gpio_write(gpio, val, TQMX86_GPIOD); + __assign_bit(offset, gpio->output, value); + tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -277,6 +274,13 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD); + /* + * Reading the previous output state is not possible with TQMx86 hardware. + * Initialize all outputs to 0 to have a defined state that matches the + * shadow register. + */ + tqmx86_gpio_write(gpio, 0, TQMX86_GPIOD); + chip = &gpio->chip; chip->label = "gpio-tqmx86"; chip->owner = THIS_MODULE; From patchwork Wed May 29 07:45:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 800069 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B240169373; 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X-CSE-ConnectionGUID: Fwzm9xSdSQWM1W/xem86mQ== X-CSE-MsgGUID: CUx555adQGGBrbSKHtEI9g== X-IronPort-AV: E=Sophos;i="6.08,197,1712613600"; d="scan'208";a="37119673" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 29 May 2024 09:46:43 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E1D14165384; Wed, 29 May 2024 09:46:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1716968799; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=DRpcV/xV6CYVXujsbd6BhKEAOgQyChA+v6Iq6iozEKo=; b=gQ8kk6WyfQCRDTR57uGcM2uoAnFvq6UQrmROSSAWxPAFW+0VxmYZS4+llZGP5tCio3fXF4 yy65v57EuBxY2BjUhUsqFP55f1yzb05TLs9vcw1LPqAxP9gOKwpAWtlZdM2phAtpx+zQIF MPISRwsqBZDpHez7SFo/3s2kP7h5daAGbxCtYEwwlSqCjSS4z9Whyu3n+JWd3VhMX//0R+ 2gjX6jeIXlQiKj0DGoH38krWqVMmkQJxKN9RRPsyqYdwgor9l7sKfOeojtl9ZjMKrbwAtt hOK/QNFU9M907Jov3kqPVPFLqxECv7fu1tZrAj7Edpv0qAzVi5C+UBkXV5K7dw== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 3/8] gpio: tqmx86: change tqmx86_gpio_write() order of arguments to match regmap API Date: Wed, 29 May 2024 09:45:15 +0200 Message-ID: <56cb8a4f19ac0596318d740ed14091d6904d3f7f.1716967982.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Conversion to actually use regmap does not seem useful for this driver, as regmap can't properly represent separate read-only and write-only registers at the same address, but we can at least match the API to make the code clearer. No functional change intended. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index b7e2dbbdc4ebe..613ab9ef2e744 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -48,8 +48,8 @@ static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) return ioread8(gd->io_base + reg); } -static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val, - unsigned int reg) +static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, unsigned int reg, + u8 val) { iowrite8(val, gd->io_base + reg); } @@ -69,7 +69,7 @@ static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, raw_spin_lock_irqsave(&gpio->spinlock, flags); __assign_bit(offset, gpio->output, value); - tqmx86_gpio_write(gpio, bitmap_get_value8(gpio->output, 0), TQMX86_GPIOD); + tqmx86_gpio_write(gpio, TQMX86_GPIOD, bitmap_get_value8(gpio->output, 0)); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -117,7 +117,7 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) raw_spin_lock_irqsave(&gpio->spinlock, flags); gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); gpiic &= ~mask; - tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + tqmx86_gpio_write(gpio, TQMX86_GPIIC, gpiic); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); } @@ -137,7 +137,7 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); gpiic &= ~mask; gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS); - tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + tqmx86_gpio_write(gpio, TQMX86_GPIIC, gpiic); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -170,7 +170,7 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS)); gpiic |= new_type << (offset * TQMX86_GPII_BITS); - tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC); + tqmx86_gpio_write(gpio, TQMX86_GPIIC, gpiic); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); return 0; @@ -188,7 +188,7 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irq_chip, desc); irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS); - tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); + tqmx86_gpio_write(gpio, TQMX86_GPIIS, irq_status); irq_bits = irq_status; for_each_set_bit(i, &irq_bits, TQMX86_NGPI) @@ -272,14 +272,14 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) raw_spin_lock_init(&gpio->spinlock); gpio->io_base = io_base; - tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD); + tqmx86_gpio_write(gpio, TQMX86_GPIODD, (u8)~TQMX86_DIR_INPUT_MASK); /* * Reading the previous output state is not possible with TQMx86 hardware. * Initialize all outputs to 0 to have a defined state that matches the * shadow register. */ - tqmx86_gpio_write(gpio, 0, TQMX86_GPIOD); + tqmx86_gpio_write(gpio, TQMX86_GPIOD, 0); chip = &gpio->chip; chip->label = "gpio-tqmx86"; @@ -300,11 +300,11 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) u8 irq_status; /* Mask all interrupts */ - tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC); + tqmx86_gpio_write(gpio, TQMX86_GPIIC, 0); /* Clear all pending interrupts */ irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS); - tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); + tqmx86_gpio_write(gpio, TQMX86_GPIIS, irq_status); girq = &chip->irq; gpio_irq_chip_set_chip(girq, &tqmx86_gpio_irq_chip); From patchwork Wed May 29 07:45:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 800353 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C90AA167DBB; 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X-CSE-ConnectionGUID: kCpDvH+ZRbuNsJETzP5ZHw== X-CSE-MsgGUID: s3TzDlp9RDSo0MneQyqbfg== X-IronPort-AV: E=Sophos;i="6.08,197,1712613600"; d="scan'208";a="37119677" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 29 May 2024 09:46:47 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 42EA3165514; Wed, 29 May 2024 09:46:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1716968803; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=3Mg8rq7zdLPhOpKV49x/S2Vbpx0uGiGQv0E3qedMQBE=; b=AabwbyZUYN9WLVaWNZeygd9tBTcjvN0WZZVVvJMNs9YyEfdO/pqHxKMO1FKcVxLvVC5gp8 u03BZZbqdpGkmNm5EUvdCuegJQiYcANmQ4kXQiGJ8fo8j611qC3h+4o9ae46l1iWSBJrj7 +VgpYlb6Hg8t0KCQRbbzrqMawC0b2onsrTjrHKNcMvy9+sGbthszKgsIQaDHP45S12byu+ fCVHjHw4yZ7DWT809NNaERnWYtLQz0eZ8NZJuFxnPZxVQmqUAelsEabtTwvc/SmFxm01z+ AbJYMj13wgmJRUTECIFJCxPhsz6MdQHQQCwnifjxohPe7U0ROu2xnZWWhtEL7g== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 4/8] gpio: tqmx86: introduce _tqmx86_gpio_update_bits() helper Date: Wed, 29 May 2024 09:45:16 +0200 Message-ID: <0a21e3f14742e9adcf29361f7f2867199cd0dd4a.1716967982.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Simplify a lot of code in the driver by introducing helpers for the common RMW pattern. No tqmx86_gpio_update_bits() function with builtin locking is added, as it would become redundant with the following fixes, which further consolidate interrupt configuration register setup. No functional change intended. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 40 ++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 613ab9ef2e744..7a851e1730dd1 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -54,6 +54,17 @@ static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, unsigned int reg, iowrite8(val, gd->io_base + reg); } +static void _tqmx86_gpio_update_bits(struct tqmx86_gpio_data *gd, + unsigned int reg, u8 mask, u8 val) +{ + u8 tmp = tqmx86_gpio_read(gd, reg); + + tmp &= ~mask; + tmp |= val & mask; + + tqmx86_gpio_write(gd, reg, tmp); +} + static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); @@ -110,15 +121,13 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; - u8 gpiic, mask; + u8 mask; mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); - raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~mask; - tqmx86_gpio_write(gpio, TQMX86_GPIIC, gpiic); + _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, 0); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); } @@ -128,16 +137,14 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; - u8 gpiic, mask; - - mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + u8 mask, val; gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); + + mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + val = gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS); raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~mask; - gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS); - tqmx86_gpio_write(gpio, TQMX86_GPIIC, gpiic); + _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -148,7 +155,7 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) unsigned int offset = (data->hwirq - TQMX86_NGPO); unsigned int edge_type = type & IRQF_TRIGGER_MASK; unsigned long flags; - u8 new_type, gpiic; + u8 new_type, mask, val; switch (edge_type) { case IRQ_TYPE_EDGE_RISING: @@ -166,11 +173,10 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) gpio->irq_type[offset] = new_type; + mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + val = new_type << (offset * TQMX86_GPII_BITS); raw_spin_lock_irqsave(&gpio->spinlock, flags); - gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); - gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS)); - gpiic |= new_type << (offset * TQMX86_GPII_BITS); - tqmx86_gpio_write(gpio, TQMX86_GPIIC, gpiic); + _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); return 0; From patchwork Wed May 29 07:45:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 800068 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5394C169AD1; Wed, 29 May 2024 07:46:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716968816; cv=none; b=KvJa4lTPb3126RE8hIIGF99GiQlnI+SK0srDeH7FAKsECYtFuz4+7rBvuxDL9ptNd0PcJUm5mUxZBte+4U4fGQsNk/jc9qJHpd6BLbLnCEPgViK9bhdZuRMRZ+YvLsvonBT1+5C31xNI+6ljKTVlHpyHu+eAUTX8H8OEjFgro/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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29 May 2024 09:46:52 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 94C0F165515; Wed, 29 May 2024 09:46:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1716968807; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=tQA7zmYXOg/1xwBxM2JFCsYV85xxh4w97CwmaIjuDsc=; b=heV64doRR904WyxfzLHEIn9HNWiaCMeuYQf6JE/+MWyoBzHO38Q9EJfIqLCFxWg/rn631p lhHrfFB74Yf9Zk8xbEdDG4TxO9cFMG9U42v3oLzi5LbIFOIxji96rdSaX5k+yWODmYOjXs gICt18z1lXlYorTneU7hL4JhuJ0QO1qtsbOU5UEXRPEKZhbdBfsI65YSw2GMx0RjX36xxQ LkjzmlQsm17JOcbngzgJ1QF0+8X0h0ERxTPrMfjpUifcH54FelmienpEuDZQg++DCd86Tj hiWetsGOPxzK5kXgjOVjQBHrMVTS/0lMLSw4KlsY5vE6h77EBsyDioVg3mLwWw== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 5/8] gpio: tqmx86: add macros for interrupt configuration Date: Wed, 29 May 2024 09:45:17 +0200 Message-ID: X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The new macros introduce a distinction between flags used by the driver to represent interrupt configuration (TQMX86_INT_ prefix) and the flags actually written to the hardware (TQMX86_GPII_ prefix). The TQMX86_INT_TRIG_ values are chosen such that they can be converted to register values by a simple shift (in the TQMX86_GPII_CONFIG() macro), at least for the NONE/FALLING/RISING triggers. No functional change intended. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 7a851e1730dd1..d6e77f604f4df 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -29,10 +29,14 @@ #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ -#define TQMX86_GPII_FALLING BIT(0) -#define TQMX86_GPII_RISING BIT(1) -#define TQMX86_GPII_MASK (BIT(0) | BIT(1)) -#define TQMX86_GPII_BITS 2 +#define TQMX86_INT_TRIG_NONE 0x0 +#define TQMX86_INT_TRIG_FALLING 0x1 +#define TQMX86_INT_TRIG_RISING 0x2 +#define TQMX86_INT_TRIG_BOTH 0x3 +#define TQMX86_INT_TRIG_MASK 0x3 + +#define TQMX86_GPII_CONFIG(i, v) ((v) << (2 * (i))) +#define TQMX86_GPII_MASK(i) TQMX86_GPII_CONFIG(i, TQMX86_INT_TRIG_MASK) struct tqmx86_gpio_data { struct gpio_chip chip; @@ -123,7 +127,7 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) unsigned long flags; u8 mask; - mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); + mask = TQMX86_GPII_MASK(offset); raw_spin_lock_irqsave(&gpio->spinlock, flags); _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, 0); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); @@ -141,8 +145,8 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); - mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); - val = gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS); + mask = TQMX86_GPII_MASK(offset); + val = TQMX86_GPII_CONFIG(offset, gpio->irq_type[offset]); raw_spin_lock_irqsave(&gpio->spinlock, flags); _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); @@ -159,13 +163,13 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) switch (edge_type) { case IRQ_TYPE_EDGE_RISING: - new_type = TQMX86_GPII_RISING; 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The additional irq_type indices remain unused, but the tqmx86_gpio_data size increase is insignificant. No functional change intended. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index d6e77f604f4df..4b37cc3bdd455 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -44,7 +44,7 @@ struct tqmx86_gpio_data { int irq; raw_spinlock_t spinlock; DECLARE_BITMAP(output, TQMX86_NGPIO); - u8 irq_type[TQMX86_NGPI]; + u8 irq_type[TQMX86_NGPIO]; }; static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) @@ -146,7 +146,7 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); mask = TQMX86_GPII_MASK(offset); - val = TQMX86_GPII_CONFIG(offset, gpio->irq_type[offset]); + val = TQMX86_GPII_CONFIG(offset, gpio->irq_type[data->hwirq]); raw_spin_lock_irqsave(&gpio->spinlock, flags); _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); 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29 May 2024 09:47:00 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5100E1653AF; Wed, 29 May 2024 09:46:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1716968816; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=caOZbQUWt+zI8G+ePC5/yzmPLu8LPl6qOM0XKEOKGSI=; b=AbbykAQk48vIParFn5Hv0sDBd8BoQxx74naZyfBOFuokIRfaFADSgqH1YeoIoQoUBMyhPn XjOxCwcXXXvuLVxyuCvYKINBDdhJO0NtyhqTvmy8ZTJakyJBVIl4CQKmB1UPjCBuS9OPxy xdCbLkUTRlnA0PcfGz9SiOqzu4OJWFpBS6LmY1Md42W/t4iCPgYPXNRe+4SZhoCvCUxKAI zH1z8iHt2x0T9cuo/zGfi9QFGAfws38x9Yp8iIGC2ShFyHQ9WKmDzOC1sOh9jidWpBLuWC koVYIfSqt+A3tcKMJJLvcxtuTT/cEcUmZN9+vncwWK5QtEXFwFD+NqUzuVBfDA== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 7/8] gpio: tqmx86: store IRQ trigger type and unmask status separately Date: Wed, 29 May 2024 09:45:19 +0200 Message-ID: X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 irq_set_type() should not implicitly unmask the IRQ. All accesses to the interrupt configuration register are moved to a new helper _tqmx86_gpio_irq_config(). We also introduce the new rule that accessing irq_type must happen while locked, which will become significant for fixing EDGE_BOTH handling. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 41 +++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index 4b37cc3bdd455..c957be3341774 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -34,6 +34,7 @@ #define TQMX86_INT_TRIG_RISING 0x2 #define TQMX86_INT_TRIG_BOTH 0x3 #define TQMX86_INT_TRIG_MASK 0x3 +#define TQMX86_INT_UNMASKED BIT(2) #define TQMX86_GPII_CONFIG(i, v) ((v) << (2 * (i))) #define TQMX86_GPII_MASK(i) TQMX86_GPII_CONFIG(i, TQMX86_INT_TRIG_MASK) @@ -42,6 +43,7 @@ struct tqmx86_gpio_data { struct gpio_chip chip; void __iomem *io_base; int irq; + /* Lock must be held for accessing output and irq_type fields */ raw_spinlock_t spinlock; DECLARE_BITMAP(output, TQMX86_NGPIO); u8 irq_type[TQMX86_NGPIO]; @@ -119,17 +121,28 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip, return GPIO_LINE_DIRECTION_OUT; } +static void _tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) +{ + unsigned int offset = hwirq - TQMX86_NGPO; + u8 type = TQMX86_INT_TRIG_NONE, mask, val; + + if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) + type = gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK; + + mask = TQMX86_GPII_MASK(offset); + val = TQMX86_GPII_CONFIG(offset, type); + _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); +} + static void tqmx86_gpio_irq_mask(struct irq_data *data) { - unsigned int offset = (data->hwirq - TQMX86_NGPO); struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; - u8 mask; - mask = TQMX86_GPII_MASK(offset); raw_spin_lock_irqsave(&gpio->spinlock, flags); - _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, 0); + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_UNMASKED; + _tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(data)); @@ -137,18 +150,15 @@ static void tqmx86_gpio_irq_mask(struct irq_data *data) static void tqmx86_gpio_irq_unmask(struct irq_data *data) { - unsigned int offset = (data->hwirq - TQMX86_NGPO); struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); unsigned long flags; - u8 mask, val; gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); - mask = TQMX86_GPII_MASK(offset); - val = TQMX86_GPII_CONFIG(offset, gpio->irq_type[data->hwirq]); raw_spin_lock_irqsave(&gpio->spinlock, flags); - _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); + gpio->irq_type[data->hwirq] |= TQMX86_INT_UNMASKED; + _tqmx86_gpio_irq_config(gpio, data->hwirq); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); } @@ -156,10 +166,9 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) { struct tqmx86_gpio_data *gpio = gpiochip_get_data( irq_data_get_irq_chip_data(data)); - unsigned int offset = (data->hwirq - TQMX86_NGPO); unsigned int edge_type = type & IRQF_TRIGGER_MASK; unsigned long flags; - u8 new_type, mask, val; + u8 new_type; switch (edge_type) { case IRQ_TYPE_EDGE_RISING: @@ -175,12 +184,12 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; /* not supported */ } - gpio->irq_type[data->hwirq] = new_type; - - mask = TQMX86_GPII_MASK(offset); - val = TQMX86_GPII_CONFIG(offset, new_type); raw_spin_lock_irqsave(&gpio->spinlock, flags); - _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); + + gpio->irq_type[data->hwirq] &= ~TQMX86_INT_TRIG_MASK; + gpio->irq_type[data->hwirq] |= new_type; + _tqmx86_gpio_irq_config(gpio, data->hwirq); + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); return 0; From patchwork Wed May 29 07:45:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 800351 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2EBE169361; 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X-CSE-ConnectionGUID: EaU7X7mNTratvwXWAZb0Zg== X-CSE-MsgGUID: qdE9Eec3SjmEOzh16s/Hzg== X-IronPort-AV: E=Sophos;i="6.08,197,1712613600"; d="scan'208";a="37119692" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 29 May 2024 09:47:05 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A57421653AB; Wed, 29 May 2024 09:47:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1716968821; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=jr7fCGaDvK5T7b6qLgLPpM6rhJVmlldtFLw2mTSr8uw=; b=ZJT8jAYgmnnSI475P0T/ckUTC6jaFyiPh64UJh1ZT9s64k+6C0ONUO1/Abtyo7oEYqe7DG wgO6hr8Nmt/4TKH0U2ao19npBheotBq8XzfOHjoLWB74K05l9h9qdsptvMVle/096Sw6cG czQP3n4S4X7dY2qiIJM7CzZg3dWNfxvWJjsZ2MbYsxoIYXnQkyLkplZfQ032phth0cb4ls e7WXKbmBWo36qosA/6K2abBpg1jc0rFrn/b5+2xfUGUAFg4X1cDnIdFkpxVRwpHDI3Ex0t ltteaWNrrqMBzGGyv6pyHs4ExEs8u5VupCZzSuhvpN8oMHni4gv7Onslh5FVpQ== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 8/8] gpio: tqmx86: fix broken IRQ_TYPE_EDGE_BOTH interrupt type Date: Wed, 29 May 2024 09:45:20 +0200 Message-ID: <2c265b6bcfcde7d2327b94c4f6e3ad6d4f1e2de7.1716967982.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The TQMx86 GPIO controller only supports falling and rising edge triggers, but not both. Fix this by implementing a software both-edge mode that toggles the edge type after every interrupt. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Co-developed-by: Gregor Herburger Signed-off-by: Gregor Herburger Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 42 +++++++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index c957be3341774..400415676ad5d 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -126,9 +126,15 @@ static void _tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int hwirq) unsigned int offset = hwirq - TQMX86_NGPO; u8 type = TQMX86_INT_TRIG_NONE, mask, val; - if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) + if (gpio->irq_type[hwirq] & TQMX86_INT_UNMASKED) { type = gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK; + if (type == TQMX86_INT_TRIG_BOTH) + type = tqmx86_gpio_get(&gpio->chip, hwirq) + ? TQMX86_INT_TRIG_FALLING + : TQMX86_INT_TRIG_RISING; + } + mask = TQMX86_GPII_MASK(offset); val = TQMX86_GPII_CONFIG(offset, type); _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); @@ -200,8 +206,8 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip); struct irq_chip *irq_chip = irq_desc_get_chip(desc); - unsigned long irq_bits; - int i = 0; + unsigned long irq_bits, flags; + int i, hwirq; u8 irq_status; chained_irq_enter(irq_chip, desc); @@ -210,6 +216,36 @@ static void tqmx86_gpio_irq_handler(struct irq_desc *desc) tqmx86_gpio_write(gpio, TQMX86_GPIIS, irq_status); irq_bits = irq_status; + + raw_spin_lock_irqsave(&gpio->spinlock, flags); + for_each_set_bit(i, &irq_bits, TQMX86_NGPI) { + hwirq = i + TQMX86_NGPO; + + /* + * Edge-both triggers are implemented by flipping the edge + * trigger after each interrupt, as the controller only supports + * either rising or falling edge triggers, but not both. + * + * Internally, the TQMx86 GPIO controller has separate status + * registers for rising and falling edge interrupts. GPIIC + * configures which bits from which register are visible in the + * interrupt status register GPIIS and defines what triggers the + * parent IRQ line. Writing to GPIIS always clears both rising + * and falling interrupt flags internally, regardless of the + * currently configured trigger. + * + * In consequence, we can cleanly implement the edge-both + * trigger in software by first clearing the interrupt and then + * setting the new trigger based on the current GPIO input in + * _tqmx86_gpio_irq_config() - even if an edge arrives between + * reading the input and setting the trigger, we will have a new + * interrupt pending. + */ + if ((gpio->irq_type[hwirq] & TQMX86_INT_TRIG_MASK) == TQMX86_INT_TRIG_BOTH) + _tqmx86_gpio_irq_config(gpio, hwirq); + } + raw_spin_unlock_irqrestore(&gpio->spinlock, flags); + for_each_set_bit(i, &irq_bits, TQMX86_NGPI) generic_handle_domain_irq(gpio->chip.irq.domain, i + TQMX86_NGPO);