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Tue, 28 May 2024 13:43:35 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b885sm1095493e87.127.2024.05.28.13.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 13:43:35 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 28 May 2024 23:43:19 +0300 Subject: [PATCH 01/10] dt-bindings: clock: qcom: split the non-PD schema for GCC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240528-qcom-gdscs-v1-1-03cf1b102a4f@linaro.org> References: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> In-Reply-To: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2430; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=9s74QROIdj/ssBLgC2P/yPwTNYf9hFSl4T/EYVO/gcM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVkH0ZLT9jQ32tNp7V9NTRcYxPnV9a7gJrfixM VLTecuQIOaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlZB9AAKCRCLPIo+Aiko 1fV7B/9/7Oj9mVPGNj9VASEnJSUSU37lfcviaOul0IUwCDeiNybOhCT7GxrcnaUVo3kfrvyQvVK SCzF9Ce9U0s2h6vQ6HjP9b5E+0U8+IgaZEjZE1HLkXuZOk+ZHrbj4SWmH2FYsxQTLmTPC5xM9YI XonWxUEZkEbTaILORSr1KboKMzKVMOXrq6FWyY3J5wG1H5qotkyV3hAGHPLU38hnu0qpMFFrXCn R/yZ4lxFfaczz2eLhYxG+9HVua8rXgAqtmOREwDlxV/sv6UV/w4mfsCNYK/2nh2wmGtdTmxrnvj MiUSEpKzGA+8OEpwVQzzVgMQzfV7Th7g6O9eprXZWI41ACzn X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Split no-PD version from the common qcom,gcc schema. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,gcc-nopd.yaml | 38 ++++++++++++++++++++++ .../devicetree/bindings/clock/qcom,gcc.yaml | 19 ++--------- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml new file mode 100644 index 000000000000..a941e75a930a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-nopd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Common Properties + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Common bindings for Qualcomm global clock control module providing the + clocks and resets. + +properties: + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 788825105f24..e7ec15b1780d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -14,27 +14,14 @@ description: | Common bindings for Qualcomm global clock control module providing the clocks, resets and power domains. -properties: - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 +allOf: + - $ref: qcom,gcc-nopd.yaml +properties: '#power-domain-cells': const: 1 - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - - reg - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' additionalProperties: true From patchwork Tue May 28 20:43:20 2024 Content-Type: text/plain; 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Tue, 28 May 2024 13:43:36 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b885sm1095493e87.127.2024.05.28.13.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 13:43:36 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 28 May 2024 23:43:20 +0300 Subject: [PATCH 02/10] dt-bindings: clock: qcom,gcc-apq8064: use non-power-domain version of GCC schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240528-qcom-gdscs-v1-2-03cf1b102a4f@linaro.org> References: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> In-Reply-To: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Switch it to use new qcom,gcc-nopd.yaml schema. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 19211176ee0b..f06720fcb531 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -19,7 +19,7 @@ description: | include/dt-bindings/reset/qcom,gcc-msm8960.h allOf: - - $ref: qcom,gcc.yaml# + - $ref: qcom,gcc-nopd.yaml# properties: compatible: From patchwork Tue May 28 20:43:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799980 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BF1B17A931 for ; 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Tue, 28 May 2024 13:43:37 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b885sm1095493e87.127.2024.05.28.13.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 13:43:36 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 28 May 2024 23:43:21 +0300 Subject: [PATCH 03/10] dt-bindings: clock: qcom,gcc-msm8660: use non-power-domain version of GCC schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240528-qcom-gdscs-v1-3-03cf1b102a4f@linaro.org> References: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> In-Reply-To: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Switch it to use new qcom,gcc-nopd.yaml schema. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml index c9e985548621..d2dcfaf2e4cf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml @@ -19,7 +19,7 @@ description: | include/dt-bindings/reset/qcom,gcc-msm8660.h allOf: - - $ref: qcom,gcc.yaml# + - $ref: qcom,gcc-nopd.yaml# properties: compatible: From patchwork Tue May 28 20:43:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799979 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1062317B411 for ; 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Tue, 28 May 2024 13:43:38 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b885sm1095493e87.127.2024.05.28.13.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 13:43:37 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 28 May 2024 23:43:22 +0300 Subject: [PATCH 04/10] dt-bindings: clock: qcom,gcc-ipq6018: use non-power-domain version of GCC schema Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240528-qcom-gdscs-v1-4-03cf1b102a4f@linaro.org> References: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> In-Reply-To: <20240528-qcom-gdscs-v1-0-03cf1b102a4f@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Switch it to use new qcom,gcc-nopd.yaml schema. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml index af5d883cfdc8..4e811698d30b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml @@ -20,7 +20,7 @@ description: | include/dt-bindings/reset/qcom,gcc-ipq6018.h allOf: - - $ref: qcom,gcc.yaml# + - $ref: qcom,gcc-nopd.yaml# properties: compatible: From patchwork Tue May 28 20:43:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799579 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C651B17B430 for ; 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Several platforms used 'gcc' here. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml index a941e75a930a..fa9a3d3a3c67 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-nopd.yaml @@ -14,7 +14,12 @@ description: | Common bindings for Qualcomm global clock control module providing the clocks and resets. +select: false + properties: + $nodename: + pattern: "^clock-controller@[0-9a-f]+$" + '#clock-cells': const: 1 From patchwork Tue May 28 20:43:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799978 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E68517DE09 for ; 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 11e60b74c3c9..178a3b424670 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -684,7 +684,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; clocks = <&cxo_board>, <&pxo_board>, From patchwork Tue May 28 20:43:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799977 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 377B217DE24 for ; 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index 455ba4bf1bf4..a66c474cd1aa 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -113,7 +113,6 @@ tlmm: pinctrl@800000 { gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&pxo_board>, <&cxo_board>; From patchwork Tue May 28 20:43:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799577 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3F9817966D for ; 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 922f9e49468a..a9c6d2dbb460 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -129,7 +129,6 @@ msmgpio: pinctrl@800000 { gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, From patchwork Tue May 28 20:43:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799578 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 746C817F371 for ; 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Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 17ab6c475958..a84cf62d843c 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -396,7 +396,7 @@ qpic_pins: qpic-state { }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq6018"; reg = <0x0 0x01800000 0x0 0x80000>; clocks = <&xo>, <&sleep_clk>; From patchwork Tue May 28 20:43:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 799976 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6579B17F398 for ; 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Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d42de829e75..27cf8d50f254 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -363,7 +363,7 @@ qpic_pins: qpic-state { }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; clocks = <&xo>,