From patchwork Fri May 24 08:18:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matti Vaittinen X-Patchwork-Id: 799781 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB125433D0; Fri, 24 May 2024 08:18:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716538705; cv=none; b=iHeKzYVaLRsREAADoQOEggm5Saf5MDDwbr9SB772mZkd0alt15SjzsnV2uAS56Kcyq7CJ5ZOSN+AqJpZ9GboKX3ENs4wIrDeS39Z71N9fMQb68p8h+F7BSyI8lpV09vP+UTIszJQ2AlaE1vZTUNcFym3cj1K8SV8qozgF7VGcgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716538705; c=relaxed/simple; bh=Q4L+7cmm5wlsvjeiaGYq94i/cBxMapFDsBmfw1NOmrA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Pisp8qBgqabg0t2KFq2FaZ+6RwrffQIhTl77ZAWr59B+GL2cvmCp7ikkOTT7A2hS3DNemZvw62pqgQz7hL7pCCACMP1R1M2Id9RR4+qELQWJcIO7JlG6Zaaj6bUgUirITxoy38XVlYgj8tehXrSC0NwYpNIXFT1z+4ECKy+24lI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YCA7Jlb+; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YCA7Jlb+" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-5296935252dso522193e87.3; Fri, 24 May 2024 01:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716538702; x=1717143502; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=ZIXY8M5wld/5UWfsJKf3I9aeRArILg4Glit4gM+exUY=; b=YCA7Jlb+WJSHvE5Yn1hoDvpzfP1/6uAiMjNrfOhIP8WGDxdeUGi0B/XrJvVKHZ3GrY IcbeGPEKMlEXzv7os3aw4Ut0XMf/+BlMO3kIgT2AP0fKohnQIYxshA248/5v500coDiR dhu0B79fyiSHGCO0CpPRF8TrfDp6UZu4lycUSPFdWExKslbPKmfbw3hlRHsgy2m9amva xPCFwmaV60UWgvHdxvRCoFMstgzGRQfXPU4AxUa/f+HZgOli8ZuMCybsQfGvbdYkZiBH JbH9vhgSWEdipemnixXt94/73TkNH2diHieL50AoW0ILzTUEEGrpqMsxNqAmaU51a2rq 6uug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716538702; x=1717143502; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ZIXY8M5wld/5UWfsJKf3I9aeRArILg4Glit4gM+exUY=; b=EdHp5oTP+YRLrBanm1Y+mlE8hWP9Gb1D4Kj7H9wZxUVWdppLGuiWtRyVuU7Dcwr9GB irZ/SkIgjK+CPN3LnW1RWifDRHo3GPL8vNGYMsPEM4MnM0uCuJ9f87VW7wOw34Mh2ESb ZhC0Gboys+XiIFztVQiGQGK+x/eGHQaUWSwbWp+qNaFKHKx0ABryCHVmgEoXJ2umZv2/ saoGVW4iKeq3f82tBsubfUt/3qQEJmt3d8HlQjlAK0eV1QF8noj44+QsnMpGVvGRvOTy u1ZLPgxVZZztZRZTSNbOMVOXvGSxjzr2RFuA3J7i11+aPjvIFR8n0lpQyHtZ17wBD6cU KTiA== X-Forwarded-Encrypted: i=1; AJvYcCWqMniYRVgpmPPgP29I8tdYxTHHX5hHVxNIpmbl/pcMm2mMwstuMM5Qlfkbvn8h4V3rdCDYMtOoXenl/kX+W09MNqum68XlFI3Nipmeg16qH64Py0CUM6grRwhFOxQ7V8JE+4/tuQGNnSxEgiY= X-Gm-Message-State: AOJu0YwriaQiHc9srrnCmKwTK/+Y1Ty6Q53KoI981PLaujYTKK2hMc8q Eqgt0lkXFVi2twqrbQ/5+xcQ0FAx53CcEeu/AvN1sjGV/s2Tr47j8WZD5Q== X-Google-Smtp-Source: AGHT+IEj8gNf3J+mPiLBcG1rW+bOiY2+NqDqOtXOdd7yup3/IDqrqC+hZ8JlhqvWiqi9bh6gsjYZMA== X-Received: by 2002:a05:6512:1112:b0:520:98ff:5554 with SMTP id 2adb3069b0e04-5296547aa0amr1148969e87.30.1716538701597; Fri, 24 May 2024 01:18:21 -0700 (PDT) Received: from fedora ([213.255.186.46]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5296e885c9asm125633e87.33.2024.05.24.01.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 01:18:20 -0700 (PDT) Date: Fri, 24 May 2024 11:18:16 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Mark Brown , Wim Van Sebroeck , Guenter Roeck , Matti Vaittinen , linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 05/10] watchdog: ROHM BD96801 PMIC WDG driver Message-ID: <29693d8478aa66b535555c04b33d316385c4cb13.1716533790.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Introduce driver for WDG block on ROHM BD96801 scalable PMIC. This driver only supports watchdog with I2C feeding and delayed response detection. Whether the watchdog toggles PRSTB pin or just causes an interrupt can be configured via device-tree. The BD96801 PMIC HW supports also window watchdog (too early feeding detection) and Q&A mode. These are not supported by this driver. Signed-off-by: Matti Vaittinen --- Revision history: v1 => v2: - Drop the forward declaration for emergency_reboot() - Typofixes - Do error checks before assignments in find_closest_fast() - Improve prints for unsupported (HW) timeout values - Use FIELD_GET() and FIELD_PREP() - Use error severity when unsupported Q&A WDG mode is tried to be used. - Minor styling fixes RFCv2 => v1: - Fix watchdog time-outs to match DS4 - Fix target timeout overflow - Improve dbg prints RFCv1 => RFCv2: - remove always running - add IRQ handling - call emergency_restart() - drop MODULE_ALIAS and add MODULE_DEVICE_TABLE watchdog: bd96801: styling fix --- drivers/watchdog/Kconfig | 13 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/bd96801_wdt.c | 416 +++++++++++++++++++++++++++++++++ 3 files changed, 430 insertions(+) create mode 100644 drivers/watchdog/bd96801_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 6bee137cfbe0..d97e735e1faa 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -181,6 +181,19 @@ config BD957XMUF_WATCHDOG watchdog. Alternatively say M to compile the driver as a module, which will be called bd9576_wdt. +config BD96801_WATCHDOG + tristate "ROHM BD96801 PMIC Watchdog" + depends on MFD_ROHM_BD96801 + select WATCHDOG_CORE + help + Support for the watchdog in the ROHM BD96801 PMIC. Watchdog can be + configured to only generate IRQ or to trigger system reset via reset + pin. + + Say Y here to include support for the ROHM BD96801 watchdog. + Alternatively say M to compile the driver as a module, + which will be called bd96801_wdt. + config CROS_EC_WATCHDOG tristate "ChromeOS EC-based watchdog" select WATCHDOG_CORE diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 3710c218f05e..31bc94436c81 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -217,6 +217,7 @@ obj-$(CONFIG_XEN_WDT) += xen_wdt.o # Architecture Independent obj-$(CONFIG_BD957XMUF_WATCHDOG) += bd9576_wdt.o +obj-$(CONFIG_BD96801_WATCHDOG) += bd96801_wdt.o obj-$(CONFIG_CROS_EC_WATCHDOG) += cros_ec_wdt.o obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o obj-$(CONFIG_DA9055_WATCHDOG) += da9055_wdt.o diff --git a/drivers/watchdog/bd96801_wdt.c b/drivers/watchdog/bd96801_wdt.c new file mode 100644 index 000000000000..ff51f42ced2a --- /dev/null +++ b/drivers/watchdog/bd96801_wdt.c @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 ROHM Semiconductors + * + * ROHM BD96801 watchdog driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static bool nowayout; +module_param(nowayout, bool, 0); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=\"false\")"); + +#define BD96801_WD_TMO_SHORT_MASK 0x70 +#define BD96801_WD_RATIO_MASK 0x3 +#define BD96801_WD_TYPE_MASK 0x4 +#define BD96801_WD_TYPE_SLOW 0x4 +#define BD96801_WD_TYPE_WIN 0x0 + +#define BD96801_WD_EN_MASK 0x3 +#define BD96801_WD_IF_EN 0x1 +#define BD96801_WD_QA_EN 0x2 +#define BD96801_WD_DISABLE 0x0 + +#define BD96801_WD_ASSERT_MASK 0x8 +#define BD96801_WD_ASSERT_RST 0x8 +#define BD96801_WD_ASSERT_IRQ 0x0 + +#define BD96801_WD_FEED_MASK 0x1 +#define BD96801_WD_FEED 0x1 + +/* 1.1 mS */ +#define FASTNG_MIN 11 +#define FASTNG_MAX_US (100 * FASTNG_MIN << 7) +#define SLOWNG_MAX_US (16 * FASTNG_MAX_US) + +#define BD96801_WDT_DEFAULT_MARGIN_MS 1843 +/* Unit is seconds */ +#define DEFAULT_TIMEOUT 30 + +/* + * BD96801 WDG supports window mode so the TMO consists of SHORT and LONG + * timeout values. SHORT time is meaningful only in window mode where feeding + * period shorter than SHORT would be an error. LONG time is used to detect if + * feeding is not occurring within given time limit (SoC SW hangs). The LONG + * timeout time is a multiple of (2, 4, 8 or 16 times) the SHORT timeout. + */ + +struct wdtbd96801 { + struct device *dev; + struct regmap *regmap; + struct watchdog_device wdt; +}; + +static int bd96801_wdt_ping(struct watchdog_device *wdt) +{ + struct wdtbd96801 *w = watchdog_get_drvdata(wdt); + + return regmap_update_bits(w->regmap, BD96801_REG_WD_FEED, + BD96801_WD_FEED_MASK, BD96801_WD_FEED); +} + +static int bd96801_wdt_start(struct watchdog_device *wdt) +{ + struct wdtbd96801 *w = watchdog_get_drvdata(wdt); + + return regmap_update_bits(w->regmap, BD96801_REG_WD_CONF, + BD96801_WD_EN_MASK, BD96801_WD_IF_EN); +} + +static int bd96801_wdt_stop(struct watchdog_device *wdt) +{ + struct wdtbd96801 *w = watchdog_get_drvdata(wdt); + + return regmap_update_bits(w->regmap, BD96801_REG_WD_CONF, + BD96801_WD_EN_MASK, BD96801_WD_DISABLE); +} + +static const struct watchdog_info bd96801_wdt_info = { + .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | + WDIOF_SETTIMEOUT, + .identity = "BD96801 Watchdog", +}; + +static const struct watchdog_ops bd96801_wdt_ops = { + .start = bd96801_wdt_start, + .stop = bd96801_wdt_stop, + .ping = bd96801_wdt_ping, +}; + +static int find_closest_fast(unsigned int target, int *sel, unsigned int *val) +{ + unsigned int window = FASTNG_MIN; + int i; + + for (i = 0; i < 8 && window < target; i++) + window <<= 1; + + if (i == 8) + return -EINVAL; + + *val = window; + *sel = i; + + return 0; +} + +static int find_closest_slow_by_fast(unsigned int fast_val, unsigned int *target, + int *slowsel) +{ + static const int multipliers[] = {2, 4, 8, 16}; + int sel; + + for (sel = 0; sel < ARRAY_SIZE(multipliers) && + multipliers[sel] * fast_val < *target; sel++) + ; + + if (sel == ARRAY_SIZE(multipliers)) + return -EINVAL; + + *slowsel = sel; + *target = multipliers[sel] * fast_val; + + return 0; +} + +static int find_closest_slow(unsigned int *target, int *slow_sel, int *fast_sel) +{ + static const int multipliers[] = {2, 4, 8, 16}; + unsigned int window = FASTNG_MIN; + unsigned int val = 0; + int i, j; + + for (i = 0; i < 8; i++) { + for (j = 0; j < ARRAY_SIZE(multipliers); j++) { + unsigned int slow; + + slow = window * multipliers[j]; + if (slow >= *target && (!val || slow < val)) { + val = slow; + *fast_sel = i; + *slow_sel = j; + } + } + window <<= 1; + } + if (!val) + return -EINVAL; + + *target = val; + + return 0; +} + +static int bd96801_set_wdt_mode(struct wdtbd96801 *w, unsigned int hw_margin, + unsigned int hw_margin_min) +{ + int fastng, slowng, type, ret, reg, mask; + struct device *dev = w->dev; + + + if (hw_margin_min * 1000 > FASTNG_MAX_US) { + dev_err(dev, "Unsupported fast timeout %u uS [max %u]\n", + hw_margin_min * 1000, FASTNG_MAX_US); + + return -EINVAL; + } + + if (hw_margin * 1000 > SLOWNG_MAX_US) { + dev_err(dev, "Unsupported slow timeout %u uS [max %u]\n", + hw_margin * 1000, SLOWNG_MAX_US); + + return -EINVAL; + } + + /* + * Convert to 100uS to guarantee reasonable timeouts fit in + * 32bit maintaining also a decent accuracy. + */ + hw_margin *= 10; + hw_margin_min *= 10; + + if (hw_margin_min) { + unsigned int min; + + type = BD96801_WD_TYPE_WIN; + dev_dbg(dev, "Setting type WINDOW 0x%x\n", type); + ret = find_closest_fast(hw_margin_min, &fastng, &min); + if (ret) + return ret; + + ret = find_closest_slow_by_fast(min, &hw_margin, &slowng); + if (ret) { + dev_err(dev, + "can't support slow timeout %u uS using fast %u uS. [max slow %u uS]\n", + hw_margin * 100, min * 100, min * 100 * 16); + + return ret; + } + w->wdt.min_hw_heartbeat_ms = min / 10; + } else { + type = BD96801_WD_TYPE_SLOW; + dev_dbg(dev, "Setting type SLOW 0x%x\n", type); + ret = find_closest_slow(&hw_margin, &slowng, &fastng); + if (ret) + return ret; + } + + w->wdt.max_hw_heartbeat_ms = hw_margin / 10; + + fastng = FIELD_PREP(BD96801_WD_TMO_SHORT_MASK, fastng); + + reg = slowng | fastng; + mask = BD96801_WD_RATIO_MASK | BD96801_WD_TMO_SHORT_MASK; + ret = regmap_update_bits(w->regmap, BD96801_REG_WD_TMO, + mask, reg); + if (ret) + return ret; + + ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF, + BD96801_WD_TYPE_MASK, type); + + return ret; +} + +static int bd96801_set_heartbeat_from_hw(struct wdtbd96801 *w, + unsigned int conf_reg) +{ + int ret; + unsigned int val, sel, fast; + + /* + * The BD96801 supports a somewhat peculiar QA-mode, which we do not + * support in this driver. If the QA-mode is enabled then we just + * warn and bail-out. + */ + if ((conf_reg & BD96801_WD_EN_MASK) != BD96801_WD_IF_EN) { + dev_err(w->dev, "watchdog set to Q&A mode - exiting\n"); + return -EINVAL; + } + + ret = regmap_read(w->regmap, BD96801_REG_WD_TMO, &val); + if (ret) + return ret; + + sel = FIELD_GET(BD96801_WD_TMO_SHORT_MASK, val); + fast = FASTNG_MIN << sel; + + sel = (val & BD96801_WD_RATIO_MASK) + 1; + w->wdt.max_hw_heartbeat_ms = (fast << sel) / USEC_PER_MSEC; + + if ((conf_reg & BD96801_WD_TYPE_MASK) == BD96801_WD_TYPE_WIN) + w->wdt.min_hw_heartbeat_ms = fast / USEC_PER_MSEC; + + return 0; +} + +static int init_wdg_hw(struct wdtbd96801 *w) +{ + u32 hw_margin[2]; + int count, ret; + u32 hw_margin_max = BD96801_WDT_DEFAULT_MARGIN_MS, hw_margin_min = 0; + + count = device_property_count_u32(w->dev->parent, "rohm,hw-timeout-ms"); + if (count < 0 && count != -EINVAL) + return count; + + if (count > 0) { + if (count > ARRAY_SIZE(hw_margin)) + return -EINVAL; + + ret = device_property_read_u32_array(w->dev->parent, + "rohm,hw-timeout-ms", + &hw_margin[0], count); + if (ret < 0) + return ret; + + if (count == 1) + hw_margin_max = hw_margin[0]; + + if (count == 2) { + if (hw_margin[1] > hw_margin[0]) { + hw_margin_max = hw_margin[1]; + hw_margin_min = hw_margin[0]; + } else { + hw_margin_max = hw_margin[0]; + hw_margin_min = hw_margin[1]; + } + } + } + + ret = bd96801_set_wdt_mode(w, hw_margin_max, hw_margin_min); + if (ret) + return ret; + + ret = device_property_match_string(w->dev->parent, "rohm,wdg-action", + "prstb"); + if (ret >= 0) { + ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF, + BD96801_WD_ASSERT_MASK, + BD96801_WD_ASSERT_RST); + return ret; + } + + ret = device_property_match_string(w->dev->parent, "rohm,wdg-action", + "intb-only"); + if (ret >= 0) { + ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF, + BD96801_WD_ASSERT_MASK, + BD96801_WD_ASSERT_IRQ); + return ret; + } + + return 0; +} + +static irqreturn_t bd96801_irq_hnd(int irq, void *data) +{ + emergency_restart(); + + return IRQ_NONE; +} + +static int bd96801_wdt_probe(struct platform_device *pdev) +{ + struct wdtbd96801 *w; + int ret, irq; + unsigned int val; + + w = devm_kzalloc(&pdev->dev, sizeof(*w), GFP_KERNEL); + if (!w) + return -ENOMEM; + + w->regmap = dev_get_regmap(pdev->dev.parent, NULL); + w->dev = &pdev->dev; + + w->wdt.info = &bd96801_wdt_info; + w->wdt.ops = &bd96801_wdt_ops; + w->wdt.parent = pdev->dev.parent; + w->wdt.timeout = DEFAULT_TIMEOUT; + watchdog_set_drvdata(&w->wdt, w); + + ret = regmap_read(w->regmap, BD96801_REG_WD_CONF, &val); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to get the watchdog state\n"); + + /* + * If the WDG is already enabled we assume it is configured by boot. + * In this case we just update the hw-timeout based on values set to + * the timeout / mode registers and leave the hardware configs + * untouched. + */ + if ((val & BD96801_WD_EN_MASK) != BD96801_WD_DISABLE) { + dev_dbg(&pdev->dev, "watchdog was running during probe\n"); + ret = bd96801_set_heartbeat_from_hw(w, val); + if (ret) + return ret; + + set_bit(WDOG_HW_RUNNING, &w->wdt.status); + } else { + /* If WDG is not running so we will initializate it */ + ret = init_wdg_hw(w); + if (ret) + return ret; + } + + dev_dbg(w->dev, "heartbeat set to %u - %u\n", + w->wdt.min_hw_heartbeat_ms, w->wdt.max_hw_heartbeat_ms); + + watchdog_init_timeout(&w->wdt, 0, pdev->dev.parent); + watchdog_set_nowayout(&w->wdt, nowayout); + watchdog_stop_on_reboot(&w->wdt); + + irq = platform_get_irq_byname(pdev, "bd96801-wdg"); + if (irq > 0) { + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + bd96801_irq_hnd, + IRQF_ONESHOT, "bd96801-wdg", + NULL); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to register IRQ\n"); + } + + return devm_watchdog_register_device(&pdev->dev, &w->wdt); +} + +static const struct platform_device_id bd96801_wdt_id[] = { + { "bd96801-wdt", }, + { } +}; +MODULE_DEVICE_TABLE(platform, bd96801_wdt_id); + +static struct platform_driver bd96801_wdt = { + .driver = { + .name = "bd96801-wdt" + }, + .probe = bd96801_wdt_probe, + .id_table = bd96801_wdt_id, +}; +module_platform_driver(bd96801_wdt); + +MODULE_AUTHOR("Matti Vaittinen "); +MODULE_DESCRIPTION("BD96801 watchdog driver"); +MODULE_LICENSE("GPL"); From patchwork Fri May 24 08:18:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matti Vaittinen X-Patchwork-Id: 798889 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 215B0433D0; Fri, 24 May 2024 08:18:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716538721; cv=none; b=LwBRnpO0aOorfgNi3yymzLF4TFOedfNRv7UTm/bayN1HAHLBtidWmHvXqge02qnP6340iruIb9G5w5oRUSLsFsgWLA2cXwQm1f4wRPTpdR/kR+F4M8revf4lY7aRFm5uDxd515IoCLIVCJ7tgstcfUtonrjsF5O1Y0GHkNF7Csw= ARC-Message-Signature: i=1; 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Fri, 24 May 2024 01:18:36 -0700 (PDT) Date: Fri, 24 May 2024 11:18:33 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Liam Girdwood , Mark Brown , Matti Vaittinen , Wim Van Sebroeck , Guenter Roeck , linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2 06/10] MAINTAINERS: Add ROHM BD96801 'scalable PMIC' entries Message-ID: <9b97cdb620ef732c53664389fb8d388aee183313.1716533790.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Add maintainer entries for ROHM BD96801 a.k.a 'scalable PMIC' drivers to be reviewed by ROHM people. Signed-off-by: Matti Vaittinen --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..da68144d51ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19111,17 +19111,21 @@ F: drivers/gpio/gpio-bd71828.c F: drivers/mfd/rohm-bd71828.c F: drivers/mfd/rohm-bd718x7.c F: drivers/mfd/rohm-bd9576.c +F: drivers/mfd/rohm-bd96801.c F: drivers/regulator/bd71815-regulator.c F: drivers/regulator/bd71828-regulator.c F: drivers/regulator/bd718x7-regulator.c F: drivers/regulator/bd9576-regulator.c +F: drivers/regulator/bd96801-regulator.c F: drivers/regulator/rohm-regulator.c F: drivers/rtc/rtc-bd70528.c F: drivers/watchdog/bd9576_wdt.c +F: drivers/watchdog/bd96801_wdt.c F: include/linux/mfd/rohm-bd71815.h F: include/linux/mfd/rohm-bd71828.h F: include/linux/mfd/rohm-bd718x7.h F: include/linux/mfd/rohm-bd957x.h +F: include/linux/mfd/rohm-bd96801.h F: include/linux/mfd/rohm-generic.h F: include/linux/mfd/rohm-shared.h